166 lines
3.9 KiB
C
166 lines
3.9 KiB
C
/*!
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@file Ia32.h
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@brief Intel SDM defined constants and structures.
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@author Satoshi Tanda
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@copyright Copyright (c) 2020 - , Satoshi Tanda. All rights reserved.
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*/
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#pragma once
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//
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// "nonstandard extension used: bit field types other than int"
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//
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#pragma warning(disable: 4214)
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//
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// "nonstandard extension used: nameless struct/union"
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//
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#pragma warning(push)
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#pragma warning(disable: 4201)
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#include "ia32-doc/out/ia32.h"
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#pragma warning(pop)
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#if !defined(CHAR_BIT)
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#define CHAR_BIT (8)
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#endif
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//
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// The entry count within an EPT page table.
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//
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#define EPT_PTE_ENTRY_COUNT 512
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//
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// The entry counts within paging structures.
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//
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#define PML4_ENTRY_COUNT 512
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#define PDPT_ENTRY_COUNT 512
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#define PDT_ENTRY_COUNT 512
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#define PT_ENTRY_COUNT 512
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//
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// The entry count within the IDT.
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//
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#define IDT_ENTRY_COUNT 256
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//
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// The levels of paging structures.
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//
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#define PT_LEVEL_PML4E 4
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#define PT_LEVEL_PDPTE 3
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#define PT_LEVEL_PDE 2
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#define PT_LEVEL_PTE 1
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//
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// Bits useful for working with paging structures and EPTs.
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//
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#ifndef PAGE_SHIFT
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#define PAGE_SHIFT 12
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#endif
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#define PAGE_SHIFT_2BM 21
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#define PAGE_SHIFT_1GB 30
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#define PAGE_MASK (PAGE_SIZE - 1)
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//
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// See: 11.11.2.2 Fixed Range MTRRs
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//
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typedef union _IA32_MTRR_FIXED_RANGE_MSR
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{
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struct
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{
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UINT8 Types[8];
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} u;
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UINT64 Flags;
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} IA32_MTRR_FIXED_RANGE_MSR;
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//
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// See: Table 11-10. Memory Ranges That Can Be Encoded With PAT
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//
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typedef UINT32 IA32_MEMORY_TYPE;
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typedef UINT64 VMCS_FIELD;
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typedef SEGMENT_DESCRIPTOR_REGISTER_64 GDTR, IDTR;
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typedef UINT32 IA32_MSR_ADDRESS;
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//
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// See: Table 30-1. VM-Instruction Error Numbers
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//
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typedef UINT32 VMX_ERROR_NUMBER;
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//
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// The helper structure for translating the guest physical address to the
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// host physical address.
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//
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typedef union _ADDRESS_TRANSLATION_HELPER
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{
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//
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// Indexes to locate paging-structure entries corresponds to this virtual
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// address.
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//
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struct
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{
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UINT64 Unused : 12; //< [11:0]
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UINT64 Pt : 9; //< [20:12]
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UINT64 Pd : 9; //< [29:21]
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UINT64 Pdpt : 9; //< [38:30]
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UINT64 Pml4 : 9; //< [47:39]
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} AsIndex;
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//
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// The page offset for each type of pages. For example, for 4KB pages, bits
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// [11:0] are treated as the page offset and Mapping4Kb can be used for it.
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//
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union
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{
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UINT64 Mapping4Kb : 12; //< [11:0]
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UINT64 Mapping2Mb : 21; //< [20:0]
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UINT64 Mapping1Gb : 30; //< [29:0]
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} AsPageOffset;
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UINT64 AsUInt64;
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} ADDRESS_TRANSLATION_HELPER;
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//
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// See: Figure 7-11. 64-Bit TSS Format
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//
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#pragma pack(push, 1)
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typedef struct _TASK_STATE_SEGMENT_64
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{
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UINT32 Reserved0;
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UINT64 Rsp0;
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UINT64 Rsp1;
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UINT64 Rsp2;
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UINT64 Reserved1;
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UINT64 Ist[7];
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UINT64 Reserved3;
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UINT16 Reserved4;
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UINT16 IoMapBaseAddress;
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} TASK_STATE_SEGMENT_64;
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C_ASSERT(sizeof(TASK_STATE_SEGMENT_64) == 104);
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#pragma pack(pop)
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//
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// The page-aligned, 4KB size region used as a MSR bitmap. The MSR bitmap is
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// used to indicate which MSR should cause VM-exit on RDMSR and WRMSR. Each
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// bit in this 4KB region represents ON or OFF of VM-exit, where 0 indicates
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// not to trigger, and 1 indicates to trigger VM-exit. This hypervisor does
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// not intend to handle MSR accesses and so, all bits are left as 0. It is
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// important that this bitmap governs VM-exit behavior only for certain sets
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// of MSRs. An access to any MSR that is not governed by this bitmap still
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// causes VM-exit unconditionally. For this reason, this hypervisor still
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// has RDMSR and WRMSR handling logic.
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//
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// See: 24.6.9 MSR-Bitmap Address
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//
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typedef struct _MSR_BITMAPS
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{
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UINT8 ReadBitmapLow[1024];
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UINT8 ReadBitmapHigh[1024];
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UINT8 WriteBitmapLow[1024];
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UINT8 WriteBitmapHigh[1024];
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} MSR_BITMAPS;
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C_ASSERT(sizeof(MSR_BITMAPS) == PAGE_SIZE);
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