331 lines
10 KiB
C
331 lines
10 KiB
C
/*!
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@file EfiHostInitialization.c
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@brief EFI specific implementation of host environment initialization.
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@details On EFI, the host uses its own paging structures (CR3) and interrupt
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descriptor table (IDT).
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Its own paging structures is preferable and the most straightforward
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approach to void impact from the physical mode to the virtual mode
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transition happens during OS startup time. After this transition (ie,
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SetVirtualAddressMap is called from a boot loader), the paging structures
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that is used at the physical mode and the host would be using it becomes
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invalid, as nothing runs on the physical mode anymore. This results in
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crash (triple fault) when VM-exit occurs. One solution could be to
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subscribe the SetVirtualAddressMap event and notify the host to switch
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to the new CR3 for the virtual mode, but this has to be done for all
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logical processors requiring some inter processor calls. The MP protocol
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could do the job but is no longer available at the moment of the transition
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notification because the system is already switched from the boot time to
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the run time.
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Its own interrupt descriptor table is required for the same reason. After
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transitioning to the virtual mode, the existing IDT becomes invalid. One
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might think the host IDT is not relevant as interrupts are disabled. The
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fact is that NMI still occurs while the host is running, and also, having
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basic diagnose handlers are useful in case of access violation, for example.
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@author Satoshi Tanda
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@copyright Copyright (c) 2020 - , Satoshi Tanda. All rights reserved.
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*/
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#include "EfiHostInitialization.h"
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#include "EfiAsm.h"
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#include "EfiPlatform.h"
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#include "../../Utils.h"
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//
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// The format of the IDT.
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//
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typedef struct _INTERRUPT_GATE_DESCRIPTOR
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{
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UINT16 Offset15To0 : 16;
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UINT16 SegmentSelector : 16;
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UINT8 Reserved0;
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UINT8 GateType;
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UINT16 Offset31To16;
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UINT32 Offset63To32;
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UINT32 Reserved1;
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} INTERRUPT_GATE_DESCRIPTOR;
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C_ASSERT(sizeof(INTERRUPT_GATE_DESCRIPTOR) == 16);
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//
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// Collections of paging structures. Only the single PDPT is accommodated to
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// handle only up to 512GB of physical memory.
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//
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typedef struct _PAGING_STRUCTURES
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{
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//
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// There is only one PML4, unless 5-level page mapping is enabled.
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//
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DECLSPEC_ALIGN(PAGE_SIZE) PML4E_64 Pml4[PML4_ENTRY_COUNT];
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//
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// Only one PDPT is used for PML4[0]. This covers 512GB of the physical memory
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// range and is sufficient for our purpose.
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//
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DECLSPEC_ALIGN(PAGE_SIZE) PDPTE_64 Pdpt[1][PDPT_ENTRY_COUNT];
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//
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// PDs are assigned for each PDPT entry, meaning that 512 (PDPTEs) multiplied
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// by the PDT entry count.
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//
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DECLSPEC_ALIGN(PAGE_SIZE) PDE_2MB_64 Pdt[1][PDPT_ENTRY_COUNT][PDT_ENTRY_COUNT];
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} PAGING_STRUCTURES;
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//
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// Paging related.
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//
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static PAGING_STRUCTURES g_HostPagingStructures;
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static CR3 g_HostCr3;
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//
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// IDT related.
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//
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static INTERRUPT_GATE_DESCRIPTOR g_HostIdt[IDT_ENTRY_COUNT];
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static IDTR g_HostIdtr;
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/*!
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@brief Initializes the host paging structures.
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@details This function fills out the statically allocated paging structures
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and builds the identity mapping. All translation is done with 2MB pages
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since not 4KB granularity configuration is not needed.
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The identity mapping works because when the host is loaded, the EFI system
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also uses the identity mapping, meaning that it is essentially making a
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clone of existing paging structures.
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Note that page protections are all writable and executable. One may drop
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the executable attribute for outside the range of the .text section of
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this module and drop writable for the same range to be W^X.
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*/
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static
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VOID
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InitializeHostPagingStructures (
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)
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{
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PML4E_64* pml4;
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PDPTE_64* pdpt;
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PDE_2MB_64* pdt;
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UINT32 pml4Index;
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pml4Index = 0;
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pml4 = g_HostPagingStructures.Pml4;
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pdpt = g_HostPagingStructures.Pdpt[pml4Index];
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//
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// Fill out PML4, PDPT, PDT.
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//
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pml4[0].Present = TRUE;
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pml4[0].Write = TRUE;
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pml4[0].PageFrameNumber = GetPhysicalAddress(pdpt) >> PAGE_SHIFT;
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for (UINT32 pdptIndex = 0; pdptIndex < PDPT_ENTRY_COUNT; ++pdptIndex)
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{
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pdt = g_HostPagingStructures.Pdt[pml4Index][pdptIndex];
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pdpt[pdptIndex].Present = TRUE;
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pdpt[pdptIndex].Write = TRUE;
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pdpt[pdptIndex].PageFrameNumber = GetPhysicalAddress(pdt) >> PAGE_SHIFT;
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for (UINT32 pdIndex = 0; pdIndex < PDT_ENTRY_COUNT; ++pdIndex)
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{
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UINT64 physicalAddress;
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physicalAddress = ComputeAddressFromIndexes(pml4Index,
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pdptIndex,
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pdIndex,
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0);
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pdt[pdIndex].Present = TRUE;
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pdt[pdIndex].Write = TRUE;
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pdt[pdIndex].LargePage = TRUE;
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pdt[pdIndex].PageFrameNumber = physicalAddress >> PAGE_SHIFT_2BM;
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}
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}
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//
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// Then initialize the CR3 to point to the PML4.
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//
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g_HostCr3.AddressOfPageDirectory = GetPhysicalAddress(pml4) >> PAGE_SHIFT;
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}
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/*!
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@brief Initializes the host IDT.
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@details This function fills out the IDT with AsmDefaultExceptionHandlers[N]
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where N is the interrupt number, updates IDT[2] with AsmNmiExceptionHandler,
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and initializes IDTR to point to the IDT.
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AsmDefaultExceptionHandlers is the array of stub functions to transfer
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execution to the main common logic in AsmCommonExceptionHandler.
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*/
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static
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VOID
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InitializeHostIdt (
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)
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{
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UINT64 handlerBase;
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//
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// Get the beginning of the AsmDefaultExceptionHandlers to index.
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//
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handlerBase = (UINT64)&AsmDefaultExceptionHandlers;
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//
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// Fill out all IDT entries.
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//
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for (UINT32 i = 0; i < IDT_ENTRY_COUNT; ++i)
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{
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static const UINT64 sizeOfHandlerTill0x7f = 9;
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static const UINT64 sizeOfHandlerFrom0x80 = 12;
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UINT64 sizeOfHandler;
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UINT64 handlerAddress;
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//
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// Compute the address of AsmDefaultExceptionHandlers[i]. Each stub
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// function is 9 bytes up to 0x7f, and 12 bytes after that.
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//
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if (i < 0x80)
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{
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sizeOfHandler = sizeOfHandlerTill0x7f;
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}
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else
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{
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sizeOfHandler = sizeOfHandlerFrom0x80;
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}
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handlerAddress = (handlerBase + i * sizeOfHandler);
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//
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// Fill out the IDT entry. The type is 32-bit Interrupt gate: 0x8E
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// P=1, DPL=00b, S=0, type=1110b => type_attr=1000_1110b=0x8E)
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//
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g_HostIdt[i].Offset15To0 = (UINT16)handlerAddress;
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g_HostIdt[i].Offset31To16 = (UINT16)(handlerAddress >> 16);
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g_HostIdt[i].Offset63To32 = (UINT32)(handlerAddress >> 32);
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g_HostIdt[i].SegmentSelector = AsmReadCs();
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g_HostIdt[i].GateType = 0x8E;
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}
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//
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// Interrupt 0x2 is NMI. This needs special handling.
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//
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g_HostIdt[2].Offset15To0 = (UINT16)((UINT64)&AsmNmiExceptionHandler);
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g_HostIdt[2].Offset31To16 = (UINT16)((UINT64)&AsmNmiExceptionHandler >> 16);
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g_HostIdt[2].Offset63To32 = (UINT32)((UINT64)&AsmNmiExceptionHandler >> 32);
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//
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// Finally initialize the IDTR to point to the IDT.
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//
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g_HostIdtr.Limit = sizeof(g_HostIdt) - 1;
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g_HostIdtr.BaseAddress = (UINT64)(&g_HostIdt[0]);
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}
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VOID
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InitializeHostEnvironment (
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)
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{
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InitializeHostPagingStructures();
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InitializeHostIdt();
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}
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CR3
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GetHostCr3 (
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)
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{
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return g_HostCr3;
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}
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CONST IDTR*
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GetHostIdtr (
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)
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{
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return &g_HostIdtr;
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}
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VOID
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InitializeGdt (
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TASK_STATE_SEGMENT_64* NewTss,
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SEGMENT_DESCRIPTOR_64* NewGdt,
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UINT64 NewGdtSize,
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GDTR* OriginalGdtr
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)
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{
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GDTR newGdtr;
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SEGMENT_SELECTOR taskRegister;
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SEGMENT_DESCRIPTOR_64 tssDescriptor;
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SEGMENT_DESCRIPTOR_64* tssDescriptorInGdt;
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UINT64 tssAddress;
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SEGMENT_DESCRIPTOR_32* newGdt32;
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//
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// Get the current GDTR.
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//
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_sgdt(&newGdtr);
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*OriginalGdtr = newGdtr;
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//
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// Copy contents of the existing GDT to the new GDT in the processor context.
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//
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RtlCopyMemory(NewGdt, (VOID*)newGdtr.BaseAddress, newGdtr.Limit);
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//
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// Set up TR pointing to the entry going to be added below in the GDT. Divide
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// by the size of SEGMENT_DESCRIPTOR_32 because the limit field is in bytes
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// while the index is index in the entry count.
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//
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taskRegister.Flags = 0;
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taskRegister.Index = (newGdtr.Limit + 1ull) / sizeof(SEGMENT_DESCRIPTOR_32);
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//
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// Update the GDTR. Change the base to the new location and increase the
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// limit to add one more entry for TR. Make sure we have enough space
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// in the processor context to copy the contents of GDT.
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//
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newGdtr.BaseAddress = (UINT64)NewGdt;
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newGdtr.Limit += sizeof(SEGMENT_DESCRIPTOR_64);
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MV_ASSERT(newGdtr.Limit < NewGdtSize);
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//
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// At this point, the TR points to uninitialized entry in the GDT. Set up
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// the Task State Segment Descriptor to be written to GDT.
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//
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tssAddress = (UINT64)NewTss;
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RtlZeroMemory(&tssDescriptor, sizeof(tssDescriptor));
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tssDescriptor.SegmentLimitLow = sizeof(*NewTss) - 1;
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tssDescriptor.BaseAddressLow = (tssAddress & MAXUINT16);
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tssDescriptor.BaseAddressMiddle = ((tssAddress >> 16) & MAXUINT8);
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tssDescriptor.BaseAddressHigh = ((tssAddress >> 24) & MAXUINT8);
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tssDescriptor.BaseAddressUpper = ((tssAddress >> 32) & MAXUINT32);
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tssDescriptor.Type = SEGMENT_DESCRIPTOR_TYPE_TSS_AVAILABLE;
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tssDescriptor.Present = TRUE;
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//
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// Update the GDT by writing entry for TSS, which is pointed by the TR.
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//
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newGdt32 = (SEGMENT_DESCRIPTOR_32*)NewGdt;
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tssDescriptorInGdt = (SEGMENT_DESCRIPTOR_64*)(&newGdt32[taskRegister.Index]);
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*tssDescriptorInGdt = tssDescriptor;
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//
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// Finally, update the GDTR and TR of the current processor. The VT-x
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// requires the guest task segment register to be configured correctly
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// and the UEFI platform typically does not (ie, TR being zero). Update TR
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// to point to the task segment just set up.
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//
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// See: 26.3.1.2 Checks on Guest Segment Registers
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//
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_lgdt(&newGdtr);
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AsmWriteTr(taskRegister.Flags);
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}
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VOID
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CleanupGdt (
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CONST GDTR* OriginalGdtr
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)
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{
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MV_ASSERT(OriginalGdtr->BaseAddress != 0);
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_lgdt((VOID*)OriginalGdtr);
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}
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