diff --git a/.github/codecov.yml b/.github/codecov.yml index a9f23950..a1559ecf 100644 --- a/.github/codecov.yml +++ b/.github/codecov.yml @@ -9,4 +9,5 @@ coverage: - "internal/packages" - "internal/typepatch" - "internal/github" + - "internal/firmware" - "xtool" diff --git a/.github/workflows/targets.yml b/.github/workflows/targets.yml index 09477cfc..c704a675 100644 --- a/.github/workflows/targets.yml +++ b/.github/workflows/targets.yml @@ -36,145 +36,5 @@ jobs: - name: Build targets run: | - cd _demo/empty - for target in \ - ae-rp2040 \ - arduino-leonardo \ - arduino-mega1280 \ - arduino-mega2560 \ - arduino-mkr1000 \ - arduino-mkrwifi1010 \ - arduino-nano-new \ - arduino-nano \ - arduino-nano33 \ - arduino-zero \ - arduino \ - atmega1280 \ - atmega1284p \ - atmega2560 \ - atmega328p \ - atmega328pb \ - atmega32u4 \ - atsamd21e18a \ - atsamd21g18a \ - atsamd51g19a \ - atsamd51j19a \ - atsamd51j20a \ - atsamd51p19a \ - atsamd51p20a \ - atsame51j19a \ - atsame54-xpro \ - atsame54p20a \ - attiny1616 \ - attiny85 \ - badger2040-w \ - badger2040 \ - bluepill-clone \ - bluepill \ - btt-skr-pico \ - challenger-rp2040 \ - circuitplay-express \ - cortex-m-qemu \ - cortex-m0 \ - cortex-m0plus \ - cortex-m3 \ - cortex-m33 \ - cortex-m4 \ - cortex-m7 \ - digispark \ - elecrow-rp2040 \ - elecrow-rp2350 \ - esp-c3-32s-kit \ - esp32-c3-devkit-rust-1 \ - esp32c3-12f \ - esp32c3-supermini \ - esp32c3 \ - fe310 \ - feather-m0-express \ - feather-m0 \ - feather-m4-can \ - feather-m4 \ - feather-rp2040 \ - feather-stm32f405 \ - gameboy-advance \ - gemma-m0 \ - gnse \ - gobadge \ - gopher-badge \ - gopherbot \ - grandcentral-m4 \ - hifive1b \ - itsybitsy-m0 \ - itsybitsy-m4 \ - k210 \ - kb2040 \ - lgt92 \ - lorae5 \ - m5stamp-c3 \ - macropad-rp2040 \ - maixbit \ - makerfabs-esp32c3spi35 \ - matrixportal-m4 \ - metro-m4-airlift \ - mksnanov3 \ - nano-rp2040 \ - nintendoswitch \ - nucleo-f103rb \ - nucleo-f722ze \ - nucleo-l031k6 \ - nucleo-l432kc \ - nucleo-l476rg \ - nucleo-l552ze \ - nucleo-wl55jc \ - p1am-100 \ - pga2350 \ - pico-plus2 \ - pico-w \ - pico \ - pico2-w \ - pico2 \ - pybadge \ - pygamer \ - pyportal \ - qtpy-esp32c3 \ - qtpy-rp2040 \ - qtpy \ - riscv-qemu \ - riscv32 \ - riscv64 \ - rp2040 \ - rp2350 \ - rp2350b \ - simavr \ - stm32f469disco \ - stm32f4disco-1 \ - stm32f4disco \ - stm32l0x2 \ - stm32wl5x_cm4 \ - stm32wle5 \ - swan \ - teensy36 \ - teensy40 \ - teensy41 \ - thingplus-rp2040 \ - thumby \ - tiny2350 \ - tkey \ - trinket-m0 \ - trinkey-qt2040 \ - tufty2040 \ - wasip2 \ - wasm-unknown \ - waveshare-rp2040-tiny \ - waveshare-rp2040-zero \ - wioterminal \ - xiao-esp32c3 \ - xiao-rp2040 \ - xiao; do - ../../llgo.sh build -v -target $target -o hello.out . >/dev/null 2>&1 - if [ $? -eq 0 ]; then - echo ✅ $target `file hello.out` - else - echo ❌ $target - fi - done + cd _demo/targetsbuild + bash build.sh diff --git a/_demo/empty/empty.go b/_demo/empty/empty.go deleted file mode 100644 index da29a2ca..00000000 --- a/_demo/empty/empty.go +++ /dev/null @@ -1,4 +0,0 @@ -package main - -func main() { -} diff --git a/_demo/targetsbuild/C/c.go b/_demo/targetsbuild/C/c.go new file mode 100644 index 00000000..5110bac7 --- /dev/null +++ b/_demo/targetsbuild/C/c.go @@ -0,0 +1,21 @@ +package C + +func XhandleHardFault() { + +} + +func Reset_Handler() { + +} + +func XhandleInterrupt() { + +} + +type dyn64 struct { + // Fields for dynamic loader +} + +// For nintendo switch +func X__dynamic_loader(base uintptr, dyn *dyn64) { +} diff --git a/_demo/targetsbuild/build.sh b/_demo/targetsbuild/build.sh new file mode 100644 index 00000000..3f6bd4fe --- /dev/null +++ b/_demo/targetsbuild/build.sh @@ -0,0 +1,180 @@ +#!/bin/bash + +# Function to display usage information +show_usage() { + cat << EOF +Usage: $(basename "$0") [OPTIONS] [TARGET_FILE] + +Build targets for llgo across multiple platforms. + +OPTIONS: + -h, --help Show this help message and exit + +ARGUMENTS: + TARGET_FILE Optional. A text file containing target names, one per line. + Lines starting with # are treated as comments and ignored. + Empty lines are also ignored. + +BEHAVIOR: + Without TARGET_FILE: + - Automatically discovers all targets from ../../targets/*.json files + - Extracts target names from JSON filenames + + With TARGET_FILE: + - Reads target names from the specified file + - Supports comments (lines starting with #) + - Ignores empty lines and whitespace + +IGNORED TARGETS: + The following targets are automatically ignored and not built: + atmega1280, atmega2560, atmega328p, atmega32u4, attiny85, + fe310, k210, riscv32, riscv64, rp2040 + +RESULT CATEGORIES: + ✅ Successful: Build completed successfully + 🔕 Ignored: Target is in the ignore list + ⚠️ Warned: Build failed with configuration warnings + ❌ Failed: Build failed with errors + +EXIT CODES: + 0 All builds successful, ignored, or warned only + 1 One or more builds failed with errors + +EXAMPLES: + $(basename "$0") # Build all targets from JSON files + $(basename "$0") my-targets.txt # Build targets from file + $(basename "$0") --help # Show this help + +TARGET FILE FORMAT: + # This is a comment + esp32 + cortex-m4 + + # Another comment + riscv64 +EOF +} + +# Check for help flag +if [[ "$1" == "-h" || "$1" == "--help" ]]; then + show_usage + exit 0 +fi + +# Check for invalid number of arguments +if [ $# -gt 1 ]; then + echo "Error: Too many arguments." + echo "Use '$(basename "$0") --help' for usage information." + exit 1 +fi + +# Initialize arrays to store results +successful_targets=() +ignored_targets=() +warned_targets=() +failed_targets=() +targets_to_build=() + +# Define ignore list +ignore_list=( + "atmega1280" + "atmega2560" + "atmega328p" + "atmega32u4" + "attiny85" + "fe310" + "k210" + "riscv32" + "riscv64" + "rp2040" +) + +# Build the targets list based on input method +if [ $# -eq 1 ]; then + # Read targets from file + target_file="$1" + if [ ! -f "$target_file" ]; then + echo "Error: Target file '$target_file' not found." + echo "Use '$(basename "$0") --help' for usage information." + exit 1 + fi + + while IFS= read -r target || [[ -n "$target" ]]; do + # Skip empty lines and comments + if [[ -z "$target" || "$target" =~ ^[[:space:]]*# ]]; then + continue + fi + + # Trim whitespace + target=$(echo "$target" | xargs) + targets_to_build+=("$target") + done < "$target_file" +else + # Use targets from *.json files + for target_file in ../../targets/*.json; do + # Extract target name from filename (remove path and .json extension) + target=$(basename "$target_file" .json) + targets_to_build+=("$target") + done +fi + +# Process each target +for target in "${targets_to_build[@]}"; do + # Check if target is in ignore list + if [[ " ${ignore_list[@]} " =~ " ${target} " ]]; then + echo 🔕 $target "(ignored)" + ignored_targets+=("$target") + continue + fi + + output=$(../../llgo.sh build -target $target -o hello.out . 2>&1) + if [ $? -eq 0 ]; then + echo ✅ $target `file hello.out` + successful_targets+=("$target") + else + # Check if output contains warning messages + if echo "$output" | grep -q "does not have a valid LLVM target triple\|does not have a valid CPU configuration"; then + echo ⚠️ $target + echo "$output" + warned_targets+=("$target") + else + echo ❌ $target + echo "$output" + failed_targets+=("$target") + fi + fi +done + +echo "" +echo "----------------------------------------" + +# Output successful targets +echo "Successful targets (${#successful_targets[@]} total):" +for target in "${successful_targets[@]}"; do + echo "$target" +done + +echo "" +echo "Ignored targets (${#ignored_targets[@]} total):" +for target in "${ignored_targets[@]}"; do + echo "$target" +done + +echo "" +echo "Warned targets (${#warned_targets[@]} total):" +for target in "${warned_targets[@]}"; do + echo "$target" +done + +echo "" +echo "Failed targets (${#failed_targets[@]} total):" +for target in "${failed_targets[@]}"; do + echo "$target" +done + +# Exit with error code if there are any failed targets +if [ ${#failed_targets[@]} -gt 0 ]; then + echo "" + echo "Build failed with ${#failed_targets[@]} failed targets." + exit 1 +fi diff --git a/_demo/targetsbuild/empty.go b/_demo/targetsbuild/empty.go new file mode 100644 index 00000000..71be2ff7 --- /dev/null +++ b/_demo/targetsbuild/empty.go @@ -0,0 +1,6 @@ +package main + +import _ "github.com/goplus/llgo/_demo/targetsbuild/C" + +func main() { +} diff --git a/go.mod b/go.mod index c0be0ef7..dcdf7f39 100644 --- a/go.mod +++ b/go.mod @@ -15,6 +15,8 @@ require ( golang.org/x/tools v0.36.0 ) +require github.com/sigurn/crc16 v0.0.0-20240131213347-83fcde1e29d1 + require ( golang.org/x/mod v0.27.0 // indirect golang.org/x/sync v0.16.0 // indirect diff --git a/go.sum b/go.sum index 0dee84cd..6dbac84e 100644 --- a/go.sum +++ b/go.sum @@ -12,6 +12,8 @@ github.com/goplus/mod v0.17.1 h1:ITovxDcc5zbURV/Wrp3/SBsYLgC1KrxY6pq1zMM2V94= github.com/goplus/mod v0.17.1/go.mod h1:iXEszBKqi38BAyQApBPyQeurLHmQN34YMgC2ZNdap50= github.com/qiniu/x v1.15.1 h1:avE+YQaowp8ZExjylOeSM73rUo3MQKBAYVxh4NJ8dY8= github.com/qiniu/x v1.15.1/go.mod h1:AiovSOCaRijaf3fj+0CBOpR1457pn24b0Vdb1JpwhII= +github.com/sigurn/crc16 v0.0.0-20240131213347-83fcde1e29d1 h1:NVK+OqnavpyFmUiKfUMHrpvbCi2VFoWTrcpI7aDaJ2I= +github.com/sigurn/crc16 v0.0.0-20240131213347-83fcde1e29d1/go.mod h1:9/etS5gpQq9BJsJMWg1wpLbfuSnkm8dPF6FdW2JXVhA= golang.org/x/mod v0.27.0 h1:kb+q2PyFnEADO2IEF935ehFUXlWiNjJWtRNgBLSfbxQ= golang.org/x/mod v0.27.0/go.mod h1:rWI627Fq0DEoudcK+MBkNkCe0EetEaDSwJJkCcjpazc= golang.org/x/sync v0.16.0 h1:ycBJEhp9p4vXvUZNszeOq0kGTPghopOL8q0fq3vstxw= diff --git a/internal/build/build.go b/internal/build/build.go index e2fa4a10..2b2ce4f0 100644 --- a/internal/build/build.go +++ b/internal/build/build.go @@ -39,13 +39,14 @@ import ( "github.com/goplus/llgo/cl" "github.com/goplus/llgo/internal/cabi" + "github.com/goplus/llgo/internal/clang" "github.com/goplus/llgo/internal/crosscompile" "github.com/goplus/llgo/internal/env" + "github.com/goplus/llgo/internal/firmware" "github.com/goplus/llgo/internal/mockable" "github.com/goplus/llgo/internal/packages" "github.com/goplus/llgo/internal/typepatch" "github.com/goplus/llgo/ssa/abi" - "github.com/goplus/llgo/xtool/clang" xenv "github.com/goplus/llgo/xtool/env" "github.com/goplus/llgo/xtool/env/llvm" @@ -156,7 +157,7 @@ func Do(args []string, conf *Config) ([]Package, error) { conf.Goarch = runtime.GOARCH } // Handle crosscompile configuration first to set correct GOOS/GOARCH - export, err := crosscompile.UseWithTarget(conf.Goos, conf.Goarch, IsWasiThreadsEnabled(), conf.Target) + export, err := crosscompile.Use(conf.Goos, conf.Goarch, IsWasiThreadsEnabled(), conf.Target) if err != nil { return nil, fmt.Errorf("failed to setup crosscompile: %w", err) } @@ -389,19 +390,27 @@ type context struct { } func (c *context) compiler() *clang.Cmd { - cmd := c.env.Clang() - if c.crossCompile.CC != "" { - cmd = clang.New(c.crossCompile.CC) - } + config := clang.NewConfig( + c.crossCompile.CC, + c.crossCompile.CCFLAGS, + c.crossCompile.CFLAGS, + c.crossCompile.LDFLAGS, + c.crossCompile.Linker, + ) + cmd := clang.NewCompiler(config) cmd.Verbose = c.buildConf.Verbose return cmd } func (c *context) linker() *clang.Cmd { - cmd := c.env.Clang() - if c.crossCompile.Linker != "" { - cmd = clang.New(c.crossCompile.Linker) - } + config := clang.NewConfig( + c.crossCompile.CC, + c.crossCompile.CCFLAGS, + c.crossCompile.CFLAGS, + c.crossCompile.LDFLAGS, + c.crossCompile.Linker, + ) + cmd := clang.NewLinker(config) cmd.Verbose = c.buildConf.Verbose return cmd } @@ -552,23 +561,145 @@ func createGlobals(ctx *context, prog llssa.Program, pkgs []*aPackage) (llssa.Pa return global, nil } -func linkMainPkg(ctx *context, pkg *packages.Package, pkgs []*aPackage, global llssa.Package, conf *Config, mode Mode, verbose bool) { - pkgPath := pkg.PkgPath - name := path.Base(pkgPath) - app := conf.OutFile - if app == "" { - if mode == ModeBuild && len(ctx.initial) > 1 { +// compileExtraFiles compiles extra files (.s/.c) from target configuration and returns object files +func compileExtraFiles(ctx *context, verbose bool) ([]string, error) { + if len(ctx.crossCompile.ExtraFiles) == 0 { + return nil, nil + } + + var objFiles []string + llgoRoot := env.LLGoROOT() + + for _, extraFile := range ctx.crossCompile.ExtraFiles { + // Resolve the file path relative to llgo root + srcFile := filepath.Join(llgoRoot, extraFile) + + // Check if file exists + if _, err := os.Stat(srcFile); os.IsNotExist(err) { + return nil, fmt.Errorf("extra file not found: %s", srcFile) + } + + // Generate output file name + objFile, err := os.CreateTemp("", "extra-*"+filepath.Base(extraFile)) + if err != nil { + return nil, fmt.Errorf("failed to create temp file for %s: %w", extraFile, err) + } + objFile.Close() + + var outputFile string + ext := filepath.Ext(srcFile) + + if ctx.buildConf.GenLL { + outputFile = objFile.Name() + ".ll" + } else { + outputFile = objFile.Name() + ".o" + } + + // Prepare compilation arguments + var args []string + + // Handle different file types + switch ext { + case ".c": + args = append(args, "-x", "c") + case ".S", ".s": + args = append(args, "-x", "assembler-with-cpp") + } + + // Add output flags + if ctx.buildConf.GenLL { + args = append(args, "-emit-llvm", "-S", "-o", outputFile, "-c", srcFile) + } else { + args = append(args, "-o", outputFile, "-c", srcFile) + } + + if verbose { + fmt.Fprintf(os.Stderr, "Compiling extra file: clang %s\n", strings.Join(args, " ")) + } + + // Compile the file + cmd := ctx.compiler() + if err := cmd.Compile(args...); err != nil { + return nil, fmt.Errorf("failed to compile extra file %s: %w", srcFile, err) + } + + objFiles = append(objFiles, outputFile) + os.Remove(objFile.Name()) // Remove the temp file we created for naming + } + + return objFiles, nil +} + +// generateOutputFilenames generates the final output filename (app) and intermediate filename (orgApp) +// based on configuration and build context. +func generateOutputFilenames(outFile, binPath, appExt, binExt, pkgName string, mode Mode, isMultiplePkgs bool) (app, orgApp string, err error) { + if outFile == "" { + if mode == ModeBuild && isMultiplePkgs { // For multiple packages in ModeBuild mode, use temporary file - tmpFile, err := os.CreateTemp("", name+"*"+conf.AppExt) - check(err) + name := pkgName + if binExt != "" { + name += "*" + binExt + } else { + name += "*" + appExt + } + tmpFile, err := os.CreateTemp("", name) + if err != nil { + return "", "", err + } app = tmpFile.Name() tmpFile.Close() } else { - app = filepath.Join(conf.BinPath, name+conf.AppExt) + app = filepath.Join(binPath, pkgName+appExt) + } + orgApp = app + } else { + // outFile is not empty, use it as base part + base := outFile + if binExt != "" { + // If binExt has value, use temporary file as orgApp for firmware conversion + tmpFile, err := os.CreateTemp("", "llgo-*"+appExt) + if err != nil { + return "", "", err + } + orgApp = tmpFile.Name() + tmpFile.Close() + // Check if base already ends with binExt, if so, don't add it again + if strings.HasSuffix(base, binExt) { + app = base + } else { + app = base + binExt + } + } else { + // No binExt, use base + AppExt directly + if filepath.Ext(base) == "" { + app = base + appExt + } else { + app = base + } + orgApp = app } - } else if filepath.Ext(app) == "" { - app += conf.AppExt } + return app, orgApp, nil +} + +func linkMainPkg(ctx *context, pkg *packages.Package, pkgs []*aPackage, global llssa.Package, conf *Config, mode Mode, verbose bool) { + pkgPath := pkg.PkgPath + name := path.Base(pkgPath) + binFmt := ctx.crossCompile.BinaryFormat + binExt := firmware.BinaryExt(binFmt) + + // app: converted firmware output file or executable file + // orgApp: before converted output file + app, orgApp, err := generateOutputFilenames( + conf.OutFile, + conf.BinPath, + conf.AppExt, + binExt, + name, + mode, + len(ctx.initial) > 1, + ) + check(err) needRuntime := false needPyInit := false @@ -600,6 +731,11 @@ func linkMainPkg(ctx *context, pkg *packages.Package, pkgs []*aPackage, global l // defer os.Remove(entryLLFile) objFiles = append(objFiles, entryObjFile) + // Compile extra files from target configuration + extraObjFiles, err := compileExtraFiles(ctx, verbose) + check(err) + objFiles = append(objFiles, extraObjFiles...) + if global != nil { export, err := exportObject(ctx, pkg.PkgPath+".global", pkg.ExportFile+"-global", []byte(global.String())) check(err) @@ -619,9 +755,15 @@ func linkMainPkg(ctx *context, pkg *packages.Package, pkgs []*aPackage, global l linkArgs = append(linkArgs, exargs...) } - err = linkObjFiles(ctx, app, objFiles, linkArgs, verbose) + err = linkObjFiles(ctx, orgApp, objFiles, linkArgs, verbose) check(err) + if orgApp != app { + fmt.Printf("cross compile: %#v\n", ctx.crossCompile) + err = firmware.MakeFirmwareImage(orgApp, app, ctx.crossCompile.BinaryFormat, ctx.crossCompile.FormatDetail) + check(err) + } + switch mode { case ModeTest: cmd := exec.Command(app, conf.RunArgs...) @@ -685,8 +827,6 @@ func linkObjFiles(ctx *context, app string, objFiles, linkArgs []string, verbose buildArgs = append(buildArgs, "-gdwarf-4") } - buildArgs = append(buildArgs, ctx.crossCompile.LDFLAGS...) - buildArgs = append(buildArgs, ctx.crossCompile.EXTRAFLAGS...) buildArgs = append(buildArgs, objFiles...) cmd := ctx.linker() @@ -698,6 +838,18 @@ func isWasmTarget(goos string) bool { return slices.Contains([]string{"wasi", "js", "wasip1"}, goos) } +func needStart(conf *Config) bool { + if conf.Target == "" { + return !isWasmTarget(conf.Goos) + } + switch conf.Target { + case "wasip2": + return false + default: + return true + } +} + func genMainModuleFile(ctx *context, rtPkgPath string, pkg *packages.Package, needRuntime, needPyInit bool) (path string, err error) { var ( pyInitDecl string @@ -751,8 +903,10 @@ define weak void @_start() { } ` mainDefine := "define i32 @main(i32 noundef %0, ptr nocapture noundef readnone %1) local_unnamed_addr" - if isWasmTarget(ctx.buildConf.Goos) { + if !needStart(ctx.buildConf) && isWasmTarget(ctx.buildConf.Goos) { mainDefine = "define hidden noundef i32 @__main_argc_argv(i32 noundef %0, ptr nocapture noundef readnone %1) local_unnamed_addr" + } + if !needStart(ctx.buildConf) { startDefine = "" } mainCode := fmt.Sprintf(`; ModuleID = 'main' @@ -883,8 +1037,6 @@ func exportObject(ctx *context, pkgPath string, exportFile string, data []byte) } exportFile += ".o" args := []string{"-o", exportFile, "-c", f.Name(), "-Wno-override-module"} - args = append(args, ctx.crossCompile.CCFLAGS...) - args = append(args, ctx.crossCompile.CFLAGS...) if ctx.buildConf.Verbose { fmt.Fprintln(os.Stderr, "clang", args) } @@ -1126,8 +1278,6 @@ func clFile(ctx *context, args []string, cFile, expFile string, procFile func(li llFile += ".o" args = append(args, "-o", llFile, "-c", cFile) } - args = append(args, ctx.crossCompile.CCFLAGS...) - args = append(args, ctx.crossCompile.CFLAGS...) if verbose { fmt.Fprintln(os.Stderr, "clang", args) } diff --git a/internal/build/build_test.go b/internal/build/build_test.go index f2f8730f..b43ff6a4 100644 --- a/internal/build/build_test.go +++ b/internal/build/build_test.go @@ -8,6 +8,7 @@ import ( "fmt" "io" "os" + "strings" "testing" "github.com/goplus/llgo/internal/mockable" @@ -93,3 +94,173 @@ func TestExtest(t *testing.T) { func TestCmpTest(t *testing.T) { mockRun([]string{"../../cl/_testgo/runtest"}, &Config{Mode: ModeCmpTest}) } + +func TestGenerateOutputFilenames(t *testing.T) { + tests := []struct { + name string + outFile string + binPath string + appExt string + binExt string + pkgName string + mode Mode + isMultiplePkgs bool + wantAppSuffix string + wantOrgAppDiff bool // true if orgApp should be different from app + wantErr bool + }{ + { + name: "empty outFile, single package", + outFile: "", + binPath: "/usr/local/bin", + appExt: "", + binExt: "", + pkgName: "hello", + mode: ModeBuild, + isMultiplePkgs: false, + wantAppSuffix: "/usr/local/bin/hello", + wantOrgAppDiff: false, + }, + { + name: "empty outFile with appExt", + outFile: "", + binPath: "/usr/local/bin", + appExt: ".exe", + binExt: "", + pkgName: "hello", + mode: ModeBuild, + isMultiplePkgs: false, + wantAppSuffix: "/usr/local/bin/hello.exe", + wantOrgAppDiff: false, + }, + { + name: "outFile without binExt", + outFile: "myapp", + binPath: "/usr/local/bin", + appExt: ".exe", + binExt: "", + pkgName: "hello", + mode: ModeBuild, + isMultiplePkgs: false, + wantAppSuffix: "myapp.exe", + wantOrgAppDiff: false, + }, + { + name: "outFile with existing extension, no binExt", + outFile: "myapp.exe", + binPath: "/usr/local/bin", + appExt: ".exe", + binExt: "", + pkgName: "hello", + mode: ModeBuild, + isMultiplePkgs: false, + wantAppSuffix: "myapp.exe", + wantOrgAppDiff: false, + }, + { + name: "outFile with binExt, different from existing extension", + outFile: "myapp", + binPath: "/usr/local/bin", + appExt: ".exe", + binExt: ".bin", + pkgName: "hello", + mode: ModeBuild, + isMultiplePkgs: false, + wantAppSuffix: "myapp.bin", + wantOrgAppDiff: true, + }, + { + name: "outFile already ends with binExt", + outFile: "t.bin", + binPath: "/usr/local/bin", + appExt: ".exe", + binExt: ".bin", + pkgName: "hello", + mode: ModeBuild, + isMultiplePkgs: false, + wantAppSuffix: "t.bin", + wantOrgAppDiff: true, + }, + { + name: "outFile with full path already ends with binExt", + outFile: "/path/to/t.bin", + binPath: "/usr/local/bin", + appExt: ".exe", + binExt: ".bin", + pkgName: "hello", + mode: ModeBuild, + isMultiplePkgs: false, + wantAppSuffix: "/path/to/t.bin", + wantOrgAppDiff: true, + }, + } + + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + app, orgApp, err := generateOutputFilenames( + tt.outFile, + tt.binPath, + tt.appExt, + tt.binExt, + tt.pkgName, + tt.mode, + tt.isMultiplePkgs, + ) + + if (err != nil) != tt.wantErr { + t.Errorf("generateOutputFilenames() error = %v, wantErr %v", err, tt.wantErr) + return + } + + if tt.wantAppSuffix != "" { + if app != tt.wantAppSuffix { + t.Errorf("generateOutputFilenames() app = %v, want %v", app, tt.wantAppSuffix) + } + } + + if tt.wantOrgAppDiff { + if app == orgApp { + t.Errorf("generateOutputFilenames() orgApp should be different from app, but both are %v", app) + } + // Clean up temp file + if orgApp != "" && strings.Contains(orgApp, "llgo-") { + os.Remove(orgApp) + } + } else { + if app != orgApp { + t.Errorf("generateOutputFilenames() orgApp = %v, want %v (same as app)", orgApp, app) + } + } + }) + } +} + +func TestGenerateOutputFilenames_EdgeCases(t *testing.T) { + // Test case where outFile has same extension as binExt + app, orgApp, err := generateOutputFilenames( + "firmware.bin", + "/usr/local/bin", + ".exe", + ".bin", + "esp32app", + ModeBuild, + false, + ) + + if err != nil { + t.Fatalf("Unexpected error: %v", err) + } + + if app != "firmware.bin" { + t.Errorf("Expected app to be 'firmware.bin', got '%s'", app) + } + + if app == orgApp { + t.Errorf("Expected orgApp to be different from app when binExt is present, but both are '%s'", app) + } + + // Clean up temp file + if orgApp != "" && strings.Contains(orgApp, "llgo-") { + os.Remove(orgApp) + } +} diff --git a/internal/clang/clang.go b/internal/clang/clang.go new file mode 100644 index 00000000..eab57740 --- /dev/null +++ b/internal/clang/clang.go @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2024 The GoPlus Authors (goplus.org). All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +package clang + +import ( + "fmt" + "io" + "os" + "os/exec" + "runtime" + "strings" + + "github.com/goplus/llgo/xtool/safesplit" +) + +// Config represents clang configuration parameters. +type Config struct { + CC string // Compiler to use (e.g., "clang", "clang++") + CCFLAGS []string // Compiler flags for C/C++ compilation + CFLAGS []string // C-specific flags + LDFLAGS []string // Linker flags + Linker string // Linker to use (e.g., "ld.lld", "avr-ld") +} + +// NewConfig creates a new Config with the specified parameters. +func NewConfig(cc string, ccflags, cflags, ldflags []string, linker string) Config { + return Config{ + CC: cc, + CCFLAGS: ccflags, + CFLAGS: cflags, + LDFLAGS: ldflags, + Linker: linker, + } +} + +// Cmd represents a clang command with environment and configuration support. +type Cmd struct { + app string + config Config + Env []string + Verbose bool + Stdin io.Reader + Stdout io.Writer + Stderr io.Writer +} + +// New creates a new clang command with configuration. +func New(app string, config Config) *Cmd { + if app == "" { + app = "clang" + } + return &Cmd{ + app: app, + config: config, + Env: nil, + Verbose: false, + Stdin: nil, + Stdout: os.Stdout, + Stderr: os.Stderr, + } +} + +// NewCompiler creates a compiler command with proper flag merging. +func NewCompiler(config Config) *Cmd { + app := "clang" + if config.CC != "" { + app = config.CC + } + return New(app, config) +} + +// NewLinker creates a linker command with proper flag merging. +func NewLinker(config Config) *Cmd { + app := "clang" + if config.Linker != "" { + app = config.Linker + } else if config.CC != "" { + app = config.CC + } + return New(app, config) +} + +// Compile executes a compilation command with merged flags. +func (c *Cmd) Compile(args ...string) error { + flags := c.mergeCompilerFlags() + allArgs := make([]string, 0, len(flags)+len(args)) + allArgs = append(allArgs, flags...) + allArgs = append(allArgs, args...) + return c.exec(allArgs...) +} + +// Link executes a linking command with merged flags. +func (c *Cmd) Link(args ...string) error { + flags := c.mergeLinkerFlags() + allArgs := make([]string, 0, len(flags)+len(args)) + allArgs = append(allArgs, flags...) + allArgs = append(allArgs, args...) + return c.exec(allArgs...) +} + +// mergeCompilerFlags merges environment CCFLAGS/CFLAGS with config flags. +func (c *Cmd) mergeCompilerFlags() []string { + var flags []string + + // Add environment CCFLAGS + if envCCFlags := os.Getenv("CCFLAGS"); envCCFlags != "" { + flags = append(flags, safesplit.SplitPkgConfigFlags(envCCFlags)...) + } + + // Add environment CFLAGS + if envCFlags := os.Getenv("CFLAGS"); envCFlags != "" { + flags = append(flags, safesplit.SplitPkgConfigFlags(envCFlags)...) + } + + // Add config CCFLAGS + flags = append(flags, c.config.CCFLAGS...) + + // Add config CFLAGS + flags = append(flags, c.config.CFLAGS...) + + return flags +} + +// mergeLinkerFlags merges environment CCFLAGS/LDFLAGS with config flags. +func (c *Cmd) mergeLinkerFlags() []string { + var flags []string + + // Add environment CCFLAGS (for linker) + if envCCFlags := os.Getenv("CCFLAGS"); envCCFlags != "" { + flags = append(flags, safesplit.SplitPkgConfigFlags(envCCFlags)...) + } + + // Add environment LDFLAGS + if envLDFlags := os.Getenv("LDFLAGS"); envLDFlags != "" { + flags = append(flags, safesplit.SplitPkgConfigFlags(envLDFlags)...) + } + + // Add config LDFLAGS + flags = append(flags, c.config.LDFLAGS...) + + return flags +} + +// exec executes the clang command with given arguments. +func (c *Cmd) exec(args ...string) error { + cmd := exec.Command(c.app, args...) + if c.Verbose { + fmt.Fprintf(os.Stderr, "%v\n", cmd) + } + cmd.Stdin = c.Stdin + cmd.Stdout = c.Stdout + cmd.Stderr = c.Stderr + if c.Env != nil { + cmd.Env = c.Env + } + return cmd.Run() +} + +// CheckLinkArgs validates linking arguments by attempting a test compile. +func (c *Cmd) CheckLinkArgs(cmdArgs []string, wasm bool) error { + // Create a temporary file with appropriate extension + extension := "" + if wasm { + extension = ".wasm" + } else if runtime.GOOS == "windows" { + extension = ".exe" + } + + tmpFile, err := os.CreateTemp("", "llgo_check*"+extension) + if err != nil { + return fmt.Errorf("failed to create temporary file: %w", err) + } + tmpFile.Close() + tmpPath := tmpFile.Name() + + // Make sure to delete the temporary file when done + defer os.Remove(tmpPath) + + // Set up compilation arguments + args := append([]string{}, cmdArgs...) + args = append(args, []string{"-x", "c", "-o", tmpPath, "-"}...) + src := "int main() {return 0;}" + srcIn := strings.NewReader(src) + c.Stdin = srcIn + + // Execute the command with linker flags + return c.Link(args...) +} diff --git a/internal/clang/clang_test.go b/internal/clang/clang_test.go new file mode 100644 index 00000000..390bcb1b --- /dev/null +++ b/internal/clang/clang_test.go @@ -0,0 +1,513 @@ +//go:build !llgo +// +build !llgo + +/* + * Copyright (c) 2024 The GoPlus Authors (goplus.org). All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +package clang + +import ( + "bytes" + "os" + "reflect" + "strings" + "testing" +) + +func TestConfig(t *testing.T) { + t.Run("NewConfig", func(t *testing.T) { + ccflags := []string{"-O2", "-g"} + cflags := []string{"-std=c99"} + ldflags := []string{"-lm"} + + config := NewConfig("clang++", ccflags, cflags, ldflags, "ld.lld") + + if config.CC != "clang++" { + t.Errorf("Expected CC to be 'clang++', got %q", config.CC) + } + if !reflect.DeepEqual(config.CCFLAGS, ccflags) { + t.Errorf("Expected CCFLAGS %v, got %v", ccflags, config.CCFLAGS) + } + if !reflect.DeepEqual(config.CFLAGS, cflags) { + t.Errorf("Expected CFLAGS %v, got %v", cflags, config.CFLAGS) + } + if !reflect.DeepEqual(config.LDFLAGS, ldflags) { + t.Errorf("Expected LDFLAGS %v, got %v", ldflags, config.LDFLAGS) + } + if config.Linker != "ld.lld" { + t.Errorf("Expected Linker to be 'ld.lld', got %q", config.Linker) + } + }) +} + +func TestNew(t *testing.T) { + t.Run("WithApp", func(t *testing.T) { + config := Config{CC: "gcc"} + cmd := New("clang++", config) + + if cmd.app != "clang++" { + t.Errorf("Expected app to be 'clang++', got %q", cmd.app) + } + if !reflect.DeepEqual(cmd.config, config) { + t.Errorf("Expected config %+v, got %+v", config, cmd.config) + } + if cmd.Stdout != os.Stdout { + t.Error("Expected Stdout to be os.Stdout") + } + if cmd.Stderr != os.Stderr { + t.Error("Expected Stderr to be os.Stderr") + } + }) + + t.Run("WithoutApp", func(t *testing.T) { + config := Config{} + cmd := New("", config) + + if cmd.app != "clang" { + t.Errorf("Expected app to be 'clang', got %q", cmd.app) + } + }) +} + +func TestNewCompiler(t *testing.T) { + t.Run("WithCC", func(t *testing.T) { + config := Config{CC: "gcc"} + cmd := NewCompiler(config) + + if cmd.app != "gcc" { + t.Errorf("Expected app to be 'gcc', got %q", cmd.app) + } + }) + + t.Run("WithoutCC", func(t *testing.T) { + config := Config{} + cmd := NewCompiler(config) + + if cmd.app != "clang" { + t.Errorf("Expected app to be 'clang', got %q", cmd.app) + } + }) +} + +func TestNewLinker(t *testing.T) { + t.Run("WithLinker", func(t *testing.T) { + config := Config{Linker: "ld.lld"} + cmd := NewLinker(config) + + if cmd.app != "ld.lld" { + t.Errorf("Expected app to be 'ld.lld', got %q", cmd.app) + } + }) + + t.Run("WithoutLinkerButWithCC", func(t *testing.T) { + config := Config{CC: "gcc"} + cmd := NewLinker(config) + + if cmd.app != "gcc" { + t.Errorf("Expected app to be 'gcc', got %q", cmd.app) + } + }) + + t.Run("WithoutLinkerAndCC", func(t *testing.T) { + config := Config{} + cmd := NewLinker(config) + + if cmd.app != "clang" { + t.Errorf("Expected app to be 'clang', got %q", cmd.app) + } + }) +} + +func TestMergeCompilerFlags(t *testing.T) { + // Save original environment + origCCFlags := os.Getenv("CCFLAGS") + origCFlags := os.Getenv("CFLAGS") + defer func() { + os.Setenv("CCFLAGS", origCCFlags) + os.Setenv("CFLAGS", origCFlags) + }() + + t.Run("WithEnvironmentAndConfig", func(t *testing.T) { + os.Setenv("CCFLAGS", "-O2 -g") + os.Setenv("CFLAGS", "-std=c99") + + config := Config{ + CCFLAGS: []string{"-Wall"}, + CFLAGS: []string{"-pedantic"}, + } + cmd := New("clang", config) + + flags := cmd.mergeCompilerFlags() + expected := []string{"-O2", "-g", "-std=c99", "-Wall", "-pedantic"} + + if !reflect.DeepEqual(flags, expected) { + t.Errorf("Expected flags %v, got %v", expected, flags) + } + }) + + t.Run("WithOnlyConfig", func(t *testing.T) { + os.Unsetenv("CCFLAGS") + os.Unsetenv("CFLAGS") + + config := Config{ + CCFLAGS: []string{"-Wall"}, + CFLAGS: []string{"-pedantic"}, + } + cmd := New("clang", config) + + flags := cmd.mergeCompilerFlags() + expected := []string{"-Wall", "-pedantic"} + + if !reflect.DeepEqual(flags, expected) { + t.Errorf("Expected flags %v, got %v", expected, flags) + } + }) + + t.Run("WithOnlyEnvironment", func(t *testing.T) { + os.Setenv("CCFLAGS", "-O3") + os.Setenv("CFLAGS", "-fPIC") + + config := Config{} + cmd := New("clang", config) + + flags := cmd.mergeCompilerFlags() + expected := []string{"-O3", "-fPIC"} + + if !reflect.DeepEqual(flags, expected) { + t.Errorf("Expected flags %v, got %v", expected, flags) + } + }) + + t.Run("Empty", func(t *testing.T) { + os.Unsetenv("CCFLAGS") + os.Unsetenv("CFLAGS") + + config := Config{} + cmd := New("clang", config) + + flags := cmd.mergeCompilerFlags() + + if len(flags) != 0 { + t.Errorf("Expected empty flags, got %v", flags) + } + }) +} + +func TestMergeLinkerFlags(t *testing.T) { + // Save original environment + origCCFlags := os.Getenv("CCFLAGS") + origLDFlags := os.Getenv("LDFLAGS") + defer func() { + os.Setenv("CCFLAGS", origCCFlags) + os.Setenv("LDFLAGS", origLDFlags) + }() + + t.Run("WithEnvironmentAndConfig", func(t *testing.T) { + os.Setenv("CCFLAGS", "-O2") + os.Setenv("LDFLAGS", "-lm -lpthread") + + config := Config{ + LDFLAGS: []string{"-static"}, + } + cmd := New("clang", config) + + flags := cmd.mergeLinkerFlags() + expected := []string{"-O2", "-lm", "-lpthread", "-static"} + + if !reflect.DeepEqual(flags, expected) { + t.Errorf("Expected flags %v, got %v", expected, flags) + } + }) + + t.Run("WithOnlyConfig", func(t *testing.T) { + os.Unsetenv("CCFLAGS") + os.Unsetenv("LDFLAGS") + + config := Config{ + LDFLAGS: []string{"-static", "-lm"}, + } + cmd := New("clang", config) + + flags := cmd.mergeLinkerFlags() + expected := []string{"-static", "-lm"} + + if !reflect.DeepEqual(flags, expected) { + t.Errorf("Expected flags %v, got %v", expected, flags) + } + }) +} + +func TestCompile(t *testing.T) { + // This test uses echo instead of clang to avoid dependency on clang installation + config := Config{ + CCFLAGS: []string{"-Wall"}, + CFLAGS: []string{"-std=c99"}, + } + cmd := New("echo", config) + + var stdout bytes.Buffer + cmd.Stdout = &stdout + + err := cmd.Compile("-c", "test.c") + if err != nil { + t.Errorf("Compile failed: %v", err) + } + + output := strings.TrimSpace(stdout.String()) + expectedArgs := "-Wall -std=c99 -c test.c" + if output != expectedArgs { + t.Errorf("Expected output %q, got %q", expectedArgs, output) + } +} + +func TestLink(t *testing.T) { + // This test uses echo instead of clang to avoid dependency on clang installation + config := Config{ + LDFLAGS: []string{"-lm"}, + } + cmd := New("echo", config) + + var stdout bytes.Buffer + cmd.Stdout = &stdout + + err := cmd.Link("test.o", "-o", "test") + if err != nil { + t.Errorf("Link failed: %v", err) + } + + output := strings.TrimSpace(stdout.String()) + expectedArgs := "-lm test.o -o test" + if output != expectedArgs { + t.Errorf("Expected output %q, got %q", expectedArgs, output) + } +} + +func TestVerboseMode(t *testing.T) { + config := Config{} + cmd := New("echo", config) + cmd.Verbose = true + + // Since verbose output goes to os.Stderr directly, we'll test + // that verbose flag is set and command executes successfully + var stderr bytes.Buffer + cmd.Stderr = &stderr + cmd.Stdout = &bytes.Buffer{} // Suppress stdout + + err := cmd.Compile("-c", "test.c") + if err != nil { + t.Errorf("Compile failed: %v", err) + } + + // The test passes if verbose is set and no error occurred + if !cmd.Verbose { + t.Error("Expected Verbose to be true") + } +} + +func TestCmdEnvironment(t *testing.T) { + config := Config{} + cmd := New("echo", config) + cmd.Env = []string{"TEST_VAR=test_value"} + + var stdout bytes.Buffer + cmd.Stdout = &stdout + + // Use a command that will show environment variables + // Note: This is a simplified test that just ensures the Env field is set + err := cmd.Compile("-c", "test.c") + if err != nil { + t.Errorf("Compile failed: %v", err) + } + + if len(cmd.Env) != 1 || cmd.Env[0] != "TEST_VAR=test_value" { + t.Errorf("Expected environment to be set correctly") + } +} + +func TestCmdIO(t *testing.T) { + config := Config{} + cmd := New("cat", config) // Use cat to test stdin/stdout + + input := "test input" + cmd.Stdin = strings.NewReader(input) + + var stdout bytes.Buffer + cmd.Stdout = &stdout + + // cat will read from stdin and write to stdout + err := cmd.exec() // Call exec directly with no args + if err != nil { + t.Errorf("exec failed: %v", err) + } + + output := stdout.String() + if output != input { + t.Errorf("Expected output %q, got %q", input, output) + } +} + +func TestCheckLinkArgs(t *testing.T) { + t.Run("BasicTest", func(t *testing.T) { + // Use echo instead of clang to avoid dependency + config := Config{} + cmd := New("echo", config) + + // Redirect output to avoid clutter + cmd.Stdout = &bytes.Buffer{} + cmd.Stderr = &bytes.Buffer{} + + // This should succeed with echo + err := cmd.CheckLinkArgs([]string{"-o"}, false) + if err != nil { + t.Errorf("CheckLinkArgs failed: %v", err) + } + }) + + t.Run("WasmExtension", func(t *testing.T) { + config := Config{} + cmd := New("echo", config) + + cmd.Stdout = &bytes.Buffer{} + cmd.Stderr = &bytes.Buffer{} + + // Test with wasm=true + err := cmd.CheckLinkArgs([]string{"-o"}, true) + if err != nil { + t.Errorf("CheckLinkArgs with wasm failed: %v", err) + } + }) +} + +// Additional table-driven test for flag merging scenarios +func TestFlagMergingScenarios(t *testing.T) { + tests := []struct { + name string + envCCFlags string + envCFlags string + envLDFlags string + config Config + expectComp []string + expectLink []string + }{ + { + name: "empty everything", + envCCFlags: "", + envCFlags: "", + envLDFlags: "", + config: Config{}, + expectComp: []string{}, + expectLink: []string{}, + }, + { + name: "only environment flags", + envCCFlags: "-O2", + envCFlags: "-std=c99", + envLDFlags: "-lm", + config: Config{}, + expectComp: []string{"-O2", "-std=c99"}, + expectLink: []string{"-O2", "-lm"}, + }, + { + name: "only config flags", + envCCFlags: "", + envCFlags: "", + envLDFlags: "", + config: Config{ + CCFLAGS: []string{"-Wall"}, + CFLAGS: []string{"-pedantic"}, + LDFLAGS: []string{"-static"}, + }, + expectComp: []string{"-Wall", "-pedantic"}, + expectLink: []string{"-static"}, + }, + { + name: "mixed environment and config", + envCCFlags: "-O3", + envCFlags: "-fPIC", + envLDFlags: "-lm -lpthread", + config: Config{ + CCFLAGS: []string{"-Wall", "-Wextra"}, + CFLAGS: []string{"-std=c11"}, + LDFLAGS: []string{"-static"}, + }, + expectComp: []string{"-O3", "-fPIC", "-Wall", "-Wextra", "-std=c11"}, + expectLink: []string{"-O3", "-lm", "-lpthread", "-static"}, + }, + } + + // Save original environment + origCCFlags := os.Getenv("CCFLAGS") + origCFlags := os.Getenv("CFLAGS") + origLDFlags := os.Getenv("LDFLAGS") + defer func() { + os.Setenv("CCFLAGS", origCCFlags) + os.Setenv("CFLAGS", origCFlags) + os.Setenv("LDFLAGS", origLDFlags) + }() + + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + // Set environment variables + os.Setenv("CCFLAGS", tt.envCCFlags) + os.Setenv("CFLAGS", tt.envCFlags) + os.Setenv("LDFLAGS", tt.envLDFlags) + + cmd := New("clang", tt.config) + + // Test compiler flags + compFlags := cmd.mergeCompilerFlags() + if len(tt.expectComp) == 0 && len(compFlags) == 0 { + // Both are empty, consider them equal + } else if !reflect.DeepEqual(compFlags, tt.expectComp) { + t.Errorf("mergeCompilerFlags() = %v, want %v", compFlags, tt.expectComp) + } + + // Test linker flags + linkFlags := cmd.mergeLinkerFlags() + if len(tt.expectLink) == 0 && len(linkFlags) == 0 { + // Both are empty, consider them equal + } else if !reflect.DeepEqual(linkFlags, tt.expectLink) { + t.Errorf("mergeLinkerFlags() = %v, want %v", linkFlags, tt.expectLink) + } + }) + } +} + +// Benchmark tests +func BenchmarkMergeCompilerFlags(b *testing.B) { + config := Config{ + CCFLAGS: []string{"-Wall", "-O2"}, + CFLAGS: []string{"-std=c99", "-pedantic"}, + } + cmd := New("clang", config) + + b.ResetTimer() + for i := 0; i < b.N; i++ { + _ = cmd.mergeCompilerFlags() + } +} + +func BenchmarkMergeLinkerFlags(b *testing.B) { + config := Config{ + LDFLAGS: []string{"-lm", "-lpthread", "-static"}, + } + cmd := New("clang", config) + + b.ResetTimer() + for i := 0; i < b.N; i++ { + _ = cmd.mergeLinkerFlags() + } +} diff --git a/internal/crosscompile/crosscompile.go b/internal/crosscompile/crosscompile.go index 17bd05aa..e5f302e3 100644 --- a/internal/crosscompile/crosscompile.go +++ b/internal/crosscompile/crosscompile.go @@ -5,6 +5,7 @@ import ( "fmt" "io/fs" "os" + "os/exec" "path/filepath" "runtime" "strings" @@ -15,40 +16,261 @@ import ( ) type Export struct { - CC string // Compiler to use - CCFLAGS []string - CFLAGS []string - LDFLAGS []string - EXTRAFLAGS []string + CC string // Compiler to use + CCFLAGS []string + CFLAGS []string + LDFLAGS []string // Additional fields from target configuration - LLVMTarget string - CPU string - Features string - BuildTags []string - GOOS string - GOARCH string - Linker string // Linker to use (e.g., "ld.lld", "avr-ld") + BuildTags []string + GOOS string + GOARCH string + Linker string // Linker to use (e.g., "ld.lld", "avr-ld") + ExtraFiles []string // Extra files to compile and link (e.g., .s, .c files) + ClangRoot string // Root directory of custom clang installation + ClangBinPath string // Path to clang binary directory + + BinaryFormat string // Binary format (e.g., "elf", "esp", "uf2") + FormatDetail string // For uf2, it's uf2FamilyID } -const wasiSdkUrl = "https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-25/wasi-sdk-25.0-x86_64-macos.tar.gz" +// URLs and configuration that can be overridden for testing +var ( + wasiSdkUrl = "https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-25/wasi-sdk-25.0-x86_64-macos.tar.gz" + wasiMacosSubdir = "wasi-sdk-25.0-x86_64-macos" +) + +var ( + espClangBaseUrl = "https://github.com/goplus/espressif-llvm-project-prebuilt/releases/download/19.1.2_20250820" + espClangVersion = "19.1.2_20250820" +) + +// cacheRoot can be overridden for testing +var cacheRoot = env.LLGoCacheDir func cacheDir() string { - return filepath.Join(env.LLGoCacheDir(), "crosscompile") + return filepath.Join(cacheRoot(), "crosscompile") } -func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { +// expandEnv expands template variables in a string +// Supports variables like {port}, {hex}, {bin}, {root}, {tmpDir}, etc. +// Special case: {} expands to the first available file variable (hex, bin, img, zip) +func expandEnv(template string, envs map[string]string) string { + return expandEnvWithDefault(template, envs) +} + +// expandEnvWithDefault expands template variables with optional default for {} +func expandEnvWithDefault(template string, envs map[string]string, defaultValue ...string) string { + if template == "" { + return "" + } + + result := template + + // Handle special case of {} - use provided default or first available file variable + if strings.Contains(result, "{}") { + defaultVal := "" + if len(defaultValue) > 0 && defaultValue[0] != "" { + defaultVal = defaultValue[0] + } else { + // Priority order: hex, bin, img, zip + for _, key := range []string{"hex", "bin", "img", "zip"} { + if value, exists := envs[key]; exists && value != "" { + defaultVal = value + break + } + } + } + result = strings.ReplaceAll(result, "{}", defaultVal) + } + + // Replace named variables + for key, value := range envs { + if key != "" { // Skip empty key used for {} default + result = strings.ReplaceAll(result, "{"+key+"}", value) + } + } + return result +} + +// expandEnvSlice expands template variables in a slice of strings +func expandEnvSlice(templates []string, envs map[string]string) []string { + return expandEnvSliceWithDefault(templates, envs) +} + +// expandEnvSliceWithDefault expands template variables in a slice with optional default for {} +func expandEnvSliceWithDefault(templates []string, envs map[string]string, defaultValue ...string) []string { + if len(templates) == 0 { + return templates + } + + result := make([]string, len(templates)) + for i, template := range templates { + result[i] = expandEnvWithDefault(template, envs, defaultValue...) + } + return result +} + +// buildEnvMap creates a map of template variables for the current context +func buildEnvMap(llgoRoot string) map[string]string { + envs := make(map[string]string) + + // Basic paths + envs["root"] = llgoRoot + envs["tmpDir"] = os.TempDir() + + // These will typically be set by calling code when actual values are known + // envs["port"] = "" // Serial port (e.g., "/dev/ttyUSB0", "COM3") + // envs["hex"] = "" // Path to hex file + // envs["bin"] = "" // Path to binary file + // envs["img"] = "" // Path to image file + // envs["zip"] = "" // Path to zip file + + return envs +} + +// getCanonicalArchName returns the canonical architecture name for a target triple +func getCanonicalArchName(triple string) string { + arch := strings.Split(triple, "-")[0] + if arch == "arm64" { + return "aarch64" + } + if strings.HasPrefix(arch, "arm") || strings.HasPrefix(arch, "thumb") { + return "arm" + } + if arch == "mipsel" { + return "mips" + } + return arch +} + +// getMacOSSysroot returns the macOS SDK path using xcrun +func getMacOSSysroot() (string, error) { + cmd := exec.Command("xcrun", "--sdk", "macosx", "--show-sdk-path") + output, err := cmd.Output() + if err != nil { + return "", err + } + return strings.TrimSpace(string(output)), nil +} + +// getESPClangRoot returns the ESP Clang root directory, checking LLGoROOT first, +// then downloading if needed and platform is supported +func getESPClangRoot() (clangRoot string, err error) { + llgoRoot := env.LLGoROOT() + + // First check if clang exists in LLGoROOT + espClangRoot := filepath.Join(llgoRoot, "crosscompile", "clang") + if _, err = os.Stat(espClangRoot); err == nil { + clangRoot = espClangRoot + return + } + + // Try to download ESP Clang if platform is supported + platformSuffix := getESPClangPlatform(runtime.GOOS, runtime.GOARCH) + if platformSuffix != "" { + cacheClangDir := filepath.Join(cacheRoot(), "crosscompile", "esp-clang-"+espClangVersion) + if _, err = os.Stat(cacheClangDir); err != nil { + if !errors.Is(err, fs.ErrNotExist) { + return + } + fmt.Fprintln(os.Stderr, "ESP Clang not found in LLGO_ROOT or cache, will download.") + if err = checkDownloadAndExtractESPClang(platformSuffix, cacheClangDir); err != nil { + return + } + } + clangRoot = cacheClangDir + return + } + + err = fmt.Errorf("ESP Clang not found in LLGoROOT and platform %s/%s is not supported for download", runtime.GOOS, runtime.GOARCH) + return +} + +// getESPClangPlatform returns the platform suffix for ESP Clang downloads +func getESPClangPlatform(goos, goarch string) string { + switch goos { + case "darwin": + switch goarch { + case "amd64": + return "x86_64-apple-darwin" + case "arm64": + return "aarch64-apple-darwin" + } + case "linux": + switch goarch { + case "amd64": + return "x86_64-linux-gnu" + case "arm64": + return "aarch64-linux-gnu" + case "arm": + return "arm-linux-gnueabihf" + } + case "windows": + switch goarch { + case "amd64": + return "x86_64-w64-mingw32" + } + } + return "" +} + +func use(goos, goarch string, wasiThreads bool) (export Export, err error) { targetTriple := llvm.GetTargetTriple(goos, goarch) + llgoRoot := env.LLGoROOT() + + // Check for ESP Clang support for target-based builds + clangRoot, err := getESPClangRoot() + if err != nil { + return + } + + // Set ClangRoot and CC if clang is available + export.ClangRoot = clangRoot + export.CC = filepath.Join(clangRoot, "bin", "clang++") if runtime.GOOS == goos && runtime.GOARCH == goarch { + clangLib := filepath.Join(clangRoot, "lib") + clangInc := filepath.Join(clangRoot, "include") // not cross compile // Set up basic flags for non-cross-compile export.LDFLAGS = []string{ + "-L" + clangLib, "-target", targetTriple, - "-Wno-override-module", + "-Qunused-arguments", + "-Wno-unused-command-line-argument", "-Wl,--error-limit=0", "-fuse-ld=lld", } + export.CFLAGS = append(export.CFLAGS, "-I"+clangInc) + export.CCFLAGS = []string{ + "-Qunused-arguments", + "-Wno-unused-command-line-argument", + } + + // Add platform-specific rpath flags + switch goos { + case "darwin": + export.LDFLAGS = append(export.LDFLAGS, "-Wl,-rpath,"+clangLib) + case "linux": + export.LDFLAGS = append(export.LDFLAGS, "-Wl,-rpath,"+clangLib) + case "windows": + // Windows doesn't support rpath, DLLs should be in PATH or same directory + default: + // For other Unix-like systems, try the generic rpath + export.LDFLAGS = append(export.LDFLAGS, "-Wl,-rpath,"+clangLib) + } + + // Add sysroot for macOS only + if goos == "darwin" { + sysrootPath, sysrootErr := getMacOSSysroot() + if sysrootErr != nil { + err = fmt.Errorf("failed to get macOS SDK path: %w", sysrootErr) + return + } + export.CCFLAGS = append(export.CCFLAGS, []string{"--sysroot=" + sysrootPath}...) + export.LDFLAGS = append(export.LDFLAGS, []string{"--sysroot=" + sysrootPath}...) + } // Add OS-specific flags switch goos { @@ -85,13 +307,13 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { // Configure based on GOOS switch goos { case "wasip1": - sdkDir := filepath.Join(cacheDir(), llvm.GetTargetTriple(goos, goarch)) - if _, err = os.Stat(sdkDir); err != nil { - if !errors.Is(err, fs.ErrNotExist) { - return - } + // Set wasiSdkRoot path + wasiSdkRoot := filepath.Join(llgoRoot, "crosscompile", "wasi-libc") - if err = downloadAndExtract(wasiSdkUrl, sdkDir); err != nil { + // If not exists in LLGoROOT, download and use cached wasiSdkRoot + if _, err = os.Stat(wasiSdkRoot); err != nil { + sdkDir := filepath.Join(cacheDir(), llvm.GetTargetTriple(goos, goarch)) + if wasiSdkRoot, err = checkDownloadAndExtractWasiSDK(sdkDir); err != nil { return } } @@ -101,8 +323,7 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { triple = "wasm32-wasip1-threads" } - // Set up flags for the WASI-SDK - wasiSdkRoot := filepath.Join(sdkDir, "wasi-sdk-25.0-x86_64-macos") + // Set up flags for the WASI-SDK or wasi-libc sysrootDir := filepath.Join(wasiSdkRoot, "share", "wasi-sysroot") libclangDir := filepath.Join(wasiSdkRoot, "lib", "clang", "19") includeDir := filepath.Join(sysrootDir, "include", triple) @@ -119,6 +340,8 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { } export.CFLAGS = []string{ "-I" + includeDir, + "-Qunused-arguments", + "-Wno-unused-command-line-argument", } // Add WebAssembly linker flags export.LDFLAGS = append(export.LDFLAGS, export.CCFLAGS...) @@ -169,6 +392,8 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { // Add compiler flags export.CCFLAGS = []string{ "-target", targetTriple, + "-Qunused-arguments", + "-Wno-unused-command-line-argument", } export.CFLAGS = []string{} // Add WebAssembly linker flags for Emscripten @@ -186,7 +411,7 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { // "-z", "stack-size=10485760", // 10MB // "-Wl,--export=malloc", "-Wl,--export=free", } - export.EXTRAFLAGS = []string{ + export.LDFLAGS = append(export.LDFLAGS, []string{ "-sENVIRONMENT=web,worker", "-DPLATFORM_WEB", "-sEXPORT_KEEPALIVE=1", @@ -198,7 +423,7 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { "-sEXPORT_ALL=1", "-sASYNCIFY=1", "-sSTACK_SIZE=5242880", // 50MB - } + }...) default: err = errors.New("unsupported GOOS for WebAssembly: " + goos) @@ -216,25 +441,55 @@ func useTarget(targetName string) (export Export, err error) { return export, fmt.Errorf("failed to resolve target %s: %w", targetName, err) } + target := config.LLVMTarget + if target == "" { + return export, fmt.Errorf("target '%s' does not have a valid LLVM target triple", targetName) + } + + cpu := config.CPU + if cpu == "" { + return export, fmt.Errorf("target '%s' does not have a valid CPU configuration", targetName) + } + + // Check for ESP Clang support for target-based builds + clangRoot, err := getESPClangRoot() + if err != nil { + return + } + + // Set ClangRoot and CC if clang is available + export.ClangRoot = clangRoot + export.CC = filepath.Join(clangRoot, "bin", "clang++") + // Convert target config to Export - only export necessary fields export.BuildTags = config.BuildTags export.GOOS = config.GOOS export.GOARCH = config.GOARCH + export.ExtraFiles = config.ExtraFiles + export.BinaryFormat = config.BinaryFormat + export.FormatDetail = config.FormatDetail() + + // Build environment map for template variable expansion + envs := buildEnvMap(env.LLGoROOT()) // Convert LLVMTarget, CPU, Features to CCFLAGS/LDFLAGS var ccflags []string var ldflags []string - target := config.LLVMTarget - if target == "" { - target = llvm.GetTargetTriple(config.GOOS, config.GOARCH) + cflags := []string{"-Wno-override-module", "-Qunused-arguments", "-Wno-unused-command-line-argument"} + if config.LLVMTarget != "" { + cflags = append(cflags, "--target="+config.LLVMTarget) + ccflags = append(ccflags, "--target="+config.LLVMTarget) } + // Expand template variables in cflags + expandedCFlags := expandEnvSlice(config.CFlags, envs) + cflags = append(cflags, expandedCFlags...) - ccflags = append(ccflags, "-Wno-override-module", "--target="+config.LLVMTarget) - - // Inspired by tinygo - cpu := config.CPU + // The following parameters are inspired by tinygo/builder/library.go + // Handle CPU configuration if cpu != "" { + // X86 has deprecated the -mcpu flag, so we need to use -march instead. + // However, ARM has not done this. if strings.HasPrefix(target, "i386") || strings.HasPrefix(target, "x86_64") { ccflags = append(ccflags, "-march="+cpu) } else if strings.HasPrefix(target, "avr") { @@ -242,12 +497,50 @@ func useTarget(targetName string) (export Export, err error) { } else { ccflags = append(ccflags, "-mcpu="+cpu) } - // Only add -mllvm flags for non-WebAssembly linkers + + // For ld.lld linker, also add CPU info to linker flags if config.Linker == "ld.lld" { ldflags = append(ldflags, "-mllvm", "-mcpu="+cpu) } } + // Handle architecture-specific flags + canonicalArch := getCanonicalArchName(target) + switch canonicalArch { + case "arm": + if strings.Split(target, "-")[2] == "linux" { + ccflags = append(ccflags, "-fno-unwind-tables", "-fno-asynchronous-unwind-tables") + } else { + ccflags = append(ccflags, "-fshort-enums", "-fomit-frame-pointer", "-mfloat-abi=soft", "-fno-unwind-tables", "-fno-asynchronous-unwind-tables") + } + case "avr": + // AVR defaults to C float and double both being 32-bit. This deviates + // from what most code (and certainly compiler-rt) expects. So we need + // to force the compiler to use 64-bit floating point numbers for + // double. + ccflags = append(ccflags, "-mdouble=64") + case "riscv32": + ccflags = append(ccflags, "-march=rv32imac", "-fforce-enable-int128") + case "riscv64": + ccflags = append(ccflags, "-march=rv64gc") + case "mips": + ccflags = append(ccflags, "-fno-pic") + } + + // Handle soft float + if strings.Contains(config.Features, "soft-float") || strings.Contains(strings.Join(config.CFlags, " "), "soft-float") { + // Use softfloat instead of floating point instructions. This is + // supported on many architectures. + ccflags = append(ccflags, "-msoft-float") + } else { + if strings.HasPrefix(target, "armv5") { + // On ARMv5 we need to explicitly enable hardware floating point + // instructions: Clang appears to assume the hardware doesn't have a + // FPU otherwise. + ccflags = append(ccflags, "-mfpu=vfpv2") + } + } + // Handle Features if config.Features != "" { // Only add -mllvm flags for non-WebAssembly linkers @@ -256,64 +549,45 @@ func useTarget(targetName string) (export Export, err error) { } } - // Handle Linker - keep it for external usage - export.Linker = config.Linker + // Handle code generation configuration + if config.CodeModel != "" { + ccflags = append(ccflags, "-mcmodel="+config.CodeModel) + } + if config.TargetABI != "" { + ccflags = append(ccflags, "-mabi="+config.TargetABI) + } + if config.RelocationModel != "" { + switch config.RelocationModel { + case "pic": + ccflags = append(ccflags, "-fPIC") + case "static": + ccflags = append(ccflags, "-fno-pic") + } + } - // Combine with config flags - export.CFLAGS = config.CFlags + // Handle Linker - keep it for external usage + if config.Linker != "" { + export.Linker = filepath.Join(clangRoot, "bin", config.Linker) + } + if config.LinkerScript != "" { + ldflags = append(ldflags, "-T", config.LinkerScript) + } + ldflags = append(ldflags, "-L", env.LLGoROOT()) // search targets/*.ld + + // Combine with config flags and expand template variables + export.CFLAGS = cflags export.CCFLAGS = ccflags - export.LDFLAGS = append(ldflags, filterCompatibleLDFlags(config.LDFlags)...) - export.EXTRAFLAGS = []string{} + expandedLDFlags := expandEnvSlice(config.LDFlags, envs) + export.LDFLAGS = append(ldflags, expandedLDFlags...) return export, nil } -// UseWithTarget extends the original Use function to support target-based configuration +// Use extends the original Use function to support target-based configuration // If targetName is provided, it takes precedence over goos/goarch -func UseWithTarget(goos, goarch string, wasiThreads bool, targetName string) (export Export, err error) { +func Use(goos, goarch string, wasiThreads bool, targetName string) (export Export, err error) { if targetName != "" { return useTarget(targetName) } - return Use(goos, goarch, wasiThreads) -} - -// filterCompatibleLDFlags filters out linker flags that are incompatible with clang/lld -func filterCompatibleLDFlags(ldflags []string) []string { - if len(ldflags) == 0 { - return ldflags - } - - var filtered []string - - incompatiblePrefixes := []string{ - "--defsym=", // Use -Wl,--defsym= instead - "-T", // Linker script, needs special handling - } - - i := 0 - for i < len(ldflags) { - flag := ldflags[i] - - // Check incompatible prefixes - skip := false - for _, prefix := range incompatiblePrefixes { - if strings.HasPrefix(flag, prefix) { - skip = true - break - } - } - if skip { - // Skip -T and its argument if separate - if flag == "-T" && i+1 < len(ldflags) { - i += 2 // Skip both -T and the script path - } else { - i++ - } - continue - } - filtered = append(filtered, flag) - i++ - } - - return filtered + return use(goos, goarch, wasiThreads) } diff --git a/internal/crosscompile/crosscompile_test.go b/internal/crosscompile/crosscompile_test.go index 53161cd6..ded63e0e 100644 --- a/internal/crosscompile/crosscompile_test.go +++ b/internal/crosscompile/crosscompile_test.go @@ -37,10 +37,10 @@ func TestUseCrossCompileSDK(t *testing.T) { name: "Same Platform", goos: runtime.GOOS, goarch: runtime.GOARCH, - expectSDK: false, - expectCCFlags: false, - expectCFlags: false, - expectLDFlags: false, + expectSDK: true, // Changed: now we expect flags even for same platform + expectCCFlags: true, // Changed: CCFLAGS will contain sysroot + expectCFlags: true, // Changed: CFLAGS will contain include paths + expectLDFlags: true, // Changed: LDFLAGS will contain library paths }, { name: "WASM Target", @@ -55,10 +55,10 @@ func TestUseCrossCompileSDK(t *testing.T) { name: "Unsupported Target", goos: "windows", goarch: "amd64", - expectSDK: false, - expectCCFlags: false, - expectCFlags: false, - expectLDFlags: false, + expectSDK: false, // Still false as it won't set up specific SDK + expectCCFlags: false, // No cross-compile specific flags + expectCFlags: false, // No cross-compile specific flags + expectLDFlags: false, // No cross-compile specific flags }, } @@ -76,7 +76,7 @@ func TestUseCrossCompileSDK(t *testing.T) { for _, tc := range testCases { t.Run(tc.name, func(t *testing.T) { - export, err := Use(tc.goos, tc.goarch, false) + export, err := use(tc.goos, tc.goarch, false) if err != nil { t.Fatalf("Unexpected error: %v", err) @@ -111,11 +111,20 @@ func TestUseCrossCompileSDK(t *testing.T) { } } - if !hasSysroot { - t.Error("Missing --sysroot flag in CCFLAGS") - } - if !hasResourceDir { - t.Error("Missing -resource-dir flag in CCFLAGS") + // For WASM target, both sysroot and resource-dir are expected + if tc.name == "WASM Target" { + if !hasSysroot { + t.Error("Missing --sysroot flag in CCFLAGS") + } + if !hasResourceDir { + t.Error("Missing -resource-dir flag in CCFLAGS") + } + } else if tc.name == "Same Platform" { + // For same platform, we expect sysroot only on macOS + if runtime.GOOS == "darwin" && !hasSysroot { + t.Error("Missing --sysroot flag in CCFLAGS on macOS") + } + // On Linux and other platforms, sysroot is not necessarily required } } @@ -147,9 +156,11 @@ func TestUseCrossCompileSDK(t *testing.T) { } } } else { - if /*len(export.CCFLAGS) != 0 ||*/ len(export.CFLAGS) != 0 { - t.Errorf("Expected empty export, got CCFLAGS=%v, CFLAGS=%v, LDFLAGS=%v", - export.CCFLAGS, export.CFLAGS, export.LDFLAGS) + // For unsupported targets, we still expect some basic flags to be set + // since the implementation now always sets up ESP Clang environment + // Only check that we don't have specific SDK-related flags for unsupported targets + if tc.name == "Unsupported Target" && len(export.CFLAGS) != 0 { + t.Errorf("Expected empty CFLAGS for unsupported target, got CFLAGS=%v", export.CFLAGS) } } }) @@ -182,7 +193,7 @@ func TestUseTarget(t *testing.T) { { name: "Cortex-M Target", targetName: "cortex-m", - expectError: false, + expectError: true, expectLLVM: "", expectCPU: "", }, @@ -230,20 +241,33 @@ func TestUseTarget(t *testing.T) { } } - // Check if CPU is in CCFLAGS + // Check if CPU is in LDFLAGS (for ld.lld linker) or CCFLAGS (for other cases) if tc.expectCPU != "" { found := false - expectedFlags := []string{"-mmcu=" + tc.expectCPU, "-mcpu=" + tc.expectCPU} - for _, flag := range export.CCFLAGS { - for _, expectedFlag := range expectedFlags { - if flag == expectedFlag { + // First check LDFLAGS for -mllvm -mcpu= pattern + for i, flag := range export.LDFLAGS { + if flag == "-mllvm" && i+1 < len(export.LDFLAGS) { + nextFlag := export.LDFLAGS[i+1] + if nextFlag == "-mcpu="+tc.expectCPU { found = true break } } } + // If not found in LDFLAGS, check CCFLAGS for direct CPU flags if !found { - t.Errorf("Expected CPU %s in CCFLAGS, got %v", tc.expectCPU, export.CCFLAGS) + expectedFlags := []string{"-mmcu=" + tc.expectCPU, "-mcpu=" + tc.expectCPU} + for _, flag := range export.CCFLAGS { + for _, expectedFlag := range expectedFlags { + if flag == expectedFlag { + found = true + break + } + } + } + } + if !found { + t.Errorf("Expected CPU %s in LDFLAGS or CCFLAGS, got LDFLAGS=%v, CCFLAGS=%v", tc.expectCPU, export.LDFLAGS, export.CCFLAGS) } } @@ -255,7 +279,7 @@ func TestUseTarget(t *testing.T) { func TestUseWithTarget(t *testing.T) { // Test target-based configuration takes precedence - export, err := UseWithTarget("linux", "amd64", false, "wasi") + export, err := Use("linux", "amd64", false, "wasi") if err != nil { t.Fatalf("Unexpected error: %v", err) } @@ -267,7 +291,7 @@ func TestUseWithTarget(t *testing.T) { } // Test fallback to goos/goarch when no target specified - export, err = UseWithTarget(runtime.GOOS, runtime.GOARCH, false, "") + export, err = Use(runtime.GOOS, runtime.GOARCH, false, "") if err != nil { t.Fatalf("Unexpected error: %v", err) } @@ -278,58 +302,125 @@ func TestUseWithTarget(t *testing.T) { } } -func TestFilterCompatibleLDFlags(t *testing.T) { - testCases := []struct { - name string - input []string - expected []string +func TestExpandEnv(t *testing.T) { + envs := map[string]string{ + "port": "/dev/ttyUSB0", + "hex": "firmware.hex", + "bin": "firmware.bin", + "root": "/usr/local/llgo", + } + + tests := []struct { + template string + expected string }{ { - name: "Empty flags", - input: []string{}, - expected: []string{}, + "avrdude -c arduino -p atmega328p -P {port} -U flash:w:{hex}:i", + "avrdude -c arduino -p atmega328p -P /dev/ttyUSB0 -U flash:w:firmware.hex:i", }, { - name: "Compatible flags only", - input: []string{"-lm", "-lpthread"}, - expected: []string{"-lm", "-lpthread"}, + "simavr -m atmega328p -f 16000000 {}", + "simavr -m atmega328p -f 16000000 firmware.hex", // {} expands to hex (first priority) }, { - name: "Incompatible flags filtered", - input: []string{"--gc-sections", "-lm", "--emit-relocs", "-lpthread"}, - expected: []string{"--gc-sections", "-lm", "--emit-relocs", "-lpthread"}, + "-I{root}/lib/CMSIS/CMSIS/Include", + "-I/usr/local/llgo/lib/CMSIS/CMSIS/Include", }, { - name: "Defsym flags filtered", - input: []string{"--defsym=_stack_size=512", "-lm", "--defsym=_bootloader_size=512"}, - expected: []string{"-lm"}, + "no variables here", + "no variables here", }, { - name: "Linker script flags filtered", - input: []string{"-T", "script.ld", "-lm"}, - expected: []string{"-lm"}, - }, - { - name: "Mixed compatible and incompatible", - input: []string{"-lm", "--gc-sections", "--defsym=test=1", "-lpthread", "--no-demangle"}, - expected: []string{"-lm", "--gc-sections", "-lpthread", "--no-demangle"}, + "", + "", }, } - for _, tc := range testCases { - t.Run(tc.name, func(t *testing.T) { - result := filterCompatibleLDFlags(tc.input) - - if len(result) != len(tc.expected) { - t.Errorf("Expected %d flags, got %d: %v", len(tc.expected), len(result), result) - return - } - - for i, expected := range tc.expected { - if result[i] != expected { - t.Errorf("Expected flag[%d] = %s, got %s", i, expected, result[i]) - } - } - }) + for _, test := range tests { + result := expandEnv(test.template, envs) + if result != test.expected { + t.Errorf("expandEnv(%q) = %q, want %q", test.template, result, test.expected) + } + } +} + +func TestExpandEnvSlice(t *testing.T) { + envs := map[string]string{ + "root": "/usr/local/llgo", + "port": "/dev/ttyUSB0", + } + + input := []string{ + "-I{root}/include", + "-DPORT={port}", + "static-flag", + } + + expected := []string{ + "-I/usr/local/llgo/include", + "-DPORT=/dev/ttyUSB0", + "static-flag", + } + + result := expandEnvSlice(input, envs) + + if len(result) != len(expected) { + t.Fatalf("expandEnvSlice length mismatch: got %d, want %d", len(result), len(expected)) + } + + for i, exp := range expected { + if result[i] != exp { + t.Errorf("expandEnvSlice[%d] = %q, want %q", i, result[i], exp) + } + } +} + +func TestExpandEnvWithDefault(t *testing.T) { + envs := map[string]string{ + "port": "/dev/ttyUSB0", + "hex": "firmware.hex", + "bin": "firmware.bin", + "img": "image.img", + } + + tests := []struct { + template string + defaultValue string + expected string + }{ + { + "simavr {}", + "", // No default - should use hex (priority) + "simavr firmware.hex", + }, + { + "simavr {}", + "custom.elf", // Explicit default + "simavr custom.elf", + }, + { + "qemu -kernel {}", + "vmlinux", // Custom kernel + "qemu -kernel vmlinux", + }, + { + "no braces here", + "ignored", + "no braces here", + }, + } + + for i, test := range tests { + var result string + if test.defaultValue == "" { + result = expandEnvWithDefault(test.template, envs) + } else { + result = expandEnvWithDefault(test.template, envs, test.defaultValue) + } + + if result != test.expected { + t.Errorf("Test %d: expandEnvWithDefault(%q, envs, %q) = %q, want %q", + i, test.template, test.defaultValue, result, test.expected) + } } } diff --git a/internal/crosscompile/fetch.go b/internal/crosscompile/fetch.go index edd556a7..3584b38f 100644 --- a/internal/crosscompile/fetch.go +++ b/internal/crosscompile/fetch.go @@ -7,39 +7,149 @@ import ( "io" "net/http" "os" + "os/exec" "path/filepath" "strings" + "syscall" ) -func downloadAndExtract(url, dir string) (err error) { - if _, err = os.Stat(dir); err == nil { - os.RemoveAll(dir) - } - tempDir := dir + ".temp" - os.RemoveAll(tempDir) - if err = os.MkdirAll(tempDir, 0755); err != nil { - return fmt.Errorf("failed to create temporary directory: %w", err) +// checkDownloadAndExtractWasiSDK downloads and extracts WASI SDK +func checkDownloadAndExtractWasiSDK(dir string) (wasiSdkRoot string, err error) { + wasiSdkRoot = filepath.Join(dir, wasiMacosSubdir) + + // Check if already exists + if _, err := os.Stat(wasiSdkRoot); err == nil { + return wasiSdkRoot, nil } + // Create lock file path for the parent directory (dir) since that's what we're operating on + lockPath := dir + ".lock" + lockFile, err := acquireLock(lockPath) + if err != nil { + return "", fmt.Errorf("failed to acquire lock: %w", err) + } + defer releaseLock(lockFile) + + // Double-check after acquiring lock + if _, err := os.Stat(wasiSdkRoot); err == nil { + return wasiSdkRoot, nil + } + + err = downloadAndExtractArchive(wasiSdkUrl, dir, "WASI SDK") + return wasiSdkRoot, err +} + +// checkDownloadAndExtractESPClang downloads and extracts ESP Clang binaries and libraries +func checkDownloadAndExtractESPClang(platformSuffix, dir string) error { + // Check if already exists + if _, err := os.Stat(dir); err == nil { + return nil + } + + // Create lock file path for the final destination + lockPath := dir + ".lock" + lockFile, err := acquireLock(lockPath) + if err != nil { + return fmt.Errorf("failed to acquire lock: %w", err) + } + defer releaseLock(lockFile) + + // Double-check after acquiring lock + if _, err := os.Stat(dir); err == nil { + return nil + } + + clangUrl := fmt.Sprintf("%s/clang-esp-%s-%s.tar.xz", espClangBaseUrl, espClangVersion, platformSuffix) + description := fmt.Sprintf("ESP Clang %s-%s", espClangVersion, platformSuffix) + + // Use temporary extraction directory for ESP Clang special handling + tempExtractDir := dir + ".extract" + if err := downloadAndExtractArchive(clangUrl, tempExtractDir, description); err != nil { + return err + } + defer os.RemoveAll(tempExtractDir) + + // ESP Clang needs special handling: move esp-clang subdirectory to final destination + espClangDir := filepath.Join(tempExtractDir, "esp-clang") + if err := os.Rename(espClangDir, dir); err != nil { + return fmt.Errorf("failed to rename esp-clang directory: %w", err) + } + + return nil +} + +// acquireLock creates and locks a file to prevent concurrent operations +func acquireLock(lockPath string) (*os.File, error) { + // Ensure the parent directory exists + if err := os.MkdirAll(filepath.Dir(lockPath), 0755); err != nil { + return nil, fmt.Errorf("failed to create lock directory: %w", err) + } + + lockFile, err := os.OpenFile(lockPath, os.O_CREATE|os.O_WRONLY, 0644) + if err != nil { + return nil, fmt.Errorf("failed to create lock file: %w", err) + } + if err := syscall.Flock(int(lockFile.Fd()), syscall.LOCK_EX); err != nil { + lockFile.Close() + return nil, fmt.Errorf("failed to acquire lock: %w", err) + } + return lockFile, nil +} + +// releaseLock unlocks and removes the lock file +func releaseLock(lockFile *os.File) error { + if lockFile == nil { + return nil + } + lockPath := lockFile.Name() + syscall.Flock(int(lockFile.Fd()), syscall.LOCK_UN) + lockFile.Close() + os.Remove(lockPath) + return nil +} + +// downloadAndExtractArchive downloads and extracts an archive to the destination directory (without locking) +func downloadAndExtractArchive(url, destDir, description string) error { + fmt.Fprintf(os.Stderr, "Downloading %s...\n", description) + + // Use temporary extraction directory + tempDir := destDir + ".temp" + os.RemoveAll(tempDir) + if err := os.MkdirAll(tempDir, 0755); err != nil { + return fmt.Errorf("failed to create temporary directory: %w", err) + } + defer os.RemoveAll(tempDir) + + // Download the archive urlPath := strings.Split(url, "/") filename := urlPath[len(urlPath)-1] localFile := filepath.Join(tempDir, filename) - if err = downloadFile(url, localFile); err != nil { - return fmt.Errorf("failed to download file: %w", err) + if err := downloadFile(url, localFile); err != nil { + return fmt.Errorf("failed to download %s from %s: %w", description, url, err) } - defer os.Remove(localFile) + // Extract the archive + fmt.Fprintf(os.Stderr, "Extracting %s...\n", description) if strings.HasSuffix(filename, ".tar.gz") || strings.HasSuffix(filename, ".tgz") { - err = extractTarGz(localFile, tempDir) + err := extractTarGz(localFile, tempDir) + if err != nil { + return fmt.Errorf("failed to extract %s archive: %w", description, err) + } + } else if strings.HasSuffix(filename, ".tar.xz") { + err := extractTarXz(localFile, tempDir) + if err != nil { + return fmt.Errorf("failed to extract %s archive: %w", description, err) + } } else { return fmt.Errorf("unsupported archive format: %s", filename) } - if err != nil { - return fmt.Errorf("failed to extract archive: %w", err) - } - if err = os.Rename(tempDir, dir); err != nil { + + // Rename temp directory to target directory + if err := os.Rename(tempDir, destDir); err != nil { return fmt.Errorf("failed to rename directory: %w", err) } + + fmt.Fprintf(os.Stderr, "%s downloaded and extracted successfully.\n", description) return nil } @@ -107,3 +217,9 @@ func extractTarGz(tarGzFile, dest string) error { } return nil } + +func extractTarXz(tarXzFile, dest string) error { + // Use external tar command to extract .tar.xz files + cmd := exec.Command("tar", "-xf", tarXzFile, "-C", dest) + return cmd.Run() +} diff --git a/internal/crosscompile/fetch_test.go b/internal/crosscompile/fetch_test.go new file mode 100644 index 00000000..9bd2c496 --- /dev/null +++ b/internal/crosscompile/fetch_test.go @@ -0,0 +1,492 @@ +//go:build !llgo +// +build !llgo + +package crosscompile + +import ( + "archive/tar" + "compress/gzip" + "net/http" + "net/http/httptest" + "os" + "path/filepath" + "strings" + "sync" + "testing" + "time" +) + +// Helper function to create a test tar.gz archive +func createTestTarGz(t *testing.T, files map[string]string) string { + tempFile, err := os.CreateTemp("", "test*.tar.gz") + if err != nil { + t.Fatalf("Failed to create temp file: %v", err) + } + defer tempFile.Close() + + gzw := gzip.NewWriter(tempFile) + defer gzw.Close() + + tw := tar.NewWriter(gzw) + defer tw.Close() + + for name, content := range files { + hdr := &tar.Header{ + Name: name, + Mode: 0644, + Size: int64(len(content)), + } + if err := tw.WriteHeader(hdr); err != nil { + t.Fatalf("Failed to write tar header: %v", err) + } + if _, err := tw.Write([]byte(content)); err != nil { + t.Fatalf("Failed to write tar content: %v", err) + } + } + + return tempFile.Name() +} + +// Helper function to create a test HTTP server +func createTestServer(t *testing.T, files map[string]string) *httptest.Server { + return httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + path := strings.TrimPrefix(r.URL.Path, "/") + if content, exists := files[path]; exists { + w.Header().Set("Content-Type", "application/octet-stream") + w.Write([]byte(content)) + } else { + w.WriteHeader(http.StatusNotFound) + } + })) +} + +func TestAcquireAndReleaseLock(t *testing.T) { + tempDir := t.TempDir() + lockPath := filepath.Join(tempDir, "test.lock") + + // Test acquiring lock + lockFile, err := acquireLock(lockPath) + if err != nil { + t.Fatalf("Failed to acquire lock: %v", err) + } + + // Check lock file exists + if _, err := os.Stat(lockPath); os.IsNotExist(err) { + t.Error("Lock file should exist") + } + + // Test releasing lock + if err := releaseLock(lockFile); err != nil { + t.Errorf("Failed to release lock: %v", err) + } + + // Check lock file is removed + if _, err := os.Stat(lockPath); !os.IsNotExist(err) { + t.Error("Lock file should be removed after release") + } +} + +func TestAcquireLockConcurrency(t *testing.T) { + tempDir := t.TempDir() + lockPath := filepath.Join(tempDir, "concurrent.lock") + + var wg sync.WaitGroup + var results []int + var resultsMu sync.Mutex + + // Start multiple goroutines trying to acquire the same lock + for i := 0; i < 5; i++ { + wg.Add(1) + go func(id int) { + defer wg.Done() + + lockFile, err := acquireLock(lockPath) + if err != nil { + t.Errorf("Goroutine %d failed to acquire lock: %v", id, err) + return + } + + // Hold the lock for a short time + resultsMu.Lock() + results = append(results, id) + resultsMu.Unlock() + + time.Sleep(10 * time.Millisecond) + + if err := releaseLock(lockFile); err != nil { + t.Errorf("Goroutine %d failed to release lock: %v", id, err) + } + }(i) + } + + wg.Wait() + + // All goroutines should have successfully acquired and released the lock + if len(results) != 5 { + t.Errorf("Expected 5 successful lock acquisitions, got %d", len(results)) + } +} + +func TestDownloadFile(t *testing.T) { + // Create test server + testContent := "test file content" + server := createTestServer(t, map[string]string{ + "test.txt": testContent, + }) + defer server.Close() + + tempDir := t.TempDir() + targetFile := filepath.Join(tempDir, "downloaded.txt") + + // Test successful download + err := downloadFile(server.URL+"/test.txt", targetFile) + if err != nil { + t.Fatalf("Failed to download file: %v", err) + } + + // Check file content + content, err := os.ReadFile(targetFile) + if err != nil { + t.Fatalf("Failed to read downloaded file: %v", err) + } + + if string(content) != testContent { + t.Errorf("Expected content %q, got %q", testContent, string(content)) + } + + // Test download failure (404) + err = downloadFile(server.URL+"/nonexistent.txt", targetFile) + if err == nil { + t.Error("Expected error for non-existent file, got nil") + } +} + +func TestExtractTarGz(t *testing.T) { + // Create test archive + files := map[string]string{ + "test-dir/file1.txt": "content of file1", + "test-dir/file2.txt": "content of file2", + "file3.txt": "content of file3", + } + + archivePath := createTestTarGz(t, files) + defer os.Remove(archivePath) + + // Extract to temp directory + tempDir := t.TempDir() + err := extractTarGz(archivePath, tempDir) + if err != nil { + t.Fatalf("Failed to extract tar.gz: %v", err) + } + + // Check extracted files + for name, expectedContent := range files { + filePath := filepath.Join(tempDir, name) + content, err := os.ReadFile(filePath) + if err != nil { + t.Errorf("Failed to read extracted file %s: %v", name, err) + continue + } + if string(content) != expectedContent { + t.Errorf("File %s: expected content %q, got %q", name, expectedContent, string(content)) + } + } +} + +func TestExtractTarGzPathTraversal(t *testing.T) { + // Create a malicious archive with path traversal + tempFile, err := os.CreateTemp("", "malicious*.tar.gz") + if err != nil { + t.Fatalf("Failed to create temp file: %v", err) + } + defer tempFile.Close() + defer os.Remove(tempFile.Name()) + + gzw := gzip.NewWriter(tempFile) + tw := tar.NewWriter(gzw) + + // Add a file with path traversal attack + hdr := &tar.Header{ + Name: "../../../etc/passwd", + Mode: 0644, + Size: 5, + Typeflag: tar.TypeReg, + } + if err := tw.WriteHeader(hdr); err != nil { + t.Fatalf("Failed to write tar header: %v", err) + } + if _, err := tw.Write([]byte("pwned")); err != nil { + t.Fatalf("Failed to write tar content: %v", err) + } + + // Close writers to flush all data + if err := tw.Close(); err != nil { + t.Fatalf("Failed to close tar writer: %v", err) + } + if err := gzw.Close(); err != nil { + t.Fatalf("Failed to close gzip writer: %v", err) + } + if err := tempFile.Close(); err != nil { + t.Fatalf("Failed to close temp file: %v", err) + } + + tempDir := t.TempDir() + err = extractTarGz(tempFile.Name(), tempDir) + if err == nil { + t.Error("Expected error for path traversal attack, got nil") + } + if !strings.Contains(err.Error(), "illegal file path") { + t.Errorf("Expected 'illegal file path' error, got: %v", err) + } +} + +func TestDownloadAndExtractArchive(t *testing.T) { + // Create test archive + files := map[string]string{ + "test-app/bin/app": "#!/bin/bash\necho hello", + "test-app/lib/lib.so": "fake library content", + "test-app/README": "This is a test application", + } + + archivePath := createTestTarGz(t, files) + defer os.Remove(archivePath) + + // Create test server to serve the archive + archiveContent, err := os.ReadFile(archivePath) + if err != nil { + t.Fatalf("Failed to read test archive: %v", err) + } + + server := createTestServer(t, map[string]string{ + "test-app.tar.gz": string(archiveContent), + }) + defer server.Close() + + // Test download and extract + tempDir := t.TempDir() + destDir := filepath.Join(tempDir, "extracted") + + err = downloadAndExtractArchive(server.URL+"/test-app.tar.gz", destDir, "Test App") + if err != nil { + t.Fatalf("Failed to download and extract: %v", err) + } + + // Check extracted files + for name, expectedContent := range files { + filePath := filepath.Join(destDir, name) + content, err := os.ReadFile(filePath) + if err != nil { + t.Errorf("Failed to read extracted file %s: %v", name, err) + continue + } + if string(content) != expectedContent { + t.Errorf("File %s: expected content %q, got %q", name, expectedContent, string(content)) + } + } +} + +func TestDownloadAndExtractArchiveUnsupportedFormat(t *testing.T) { + server := createTestServer(t, map[string]string{ + "test.zip": "fake zip content", + }) + defer server.Close() + + tempDir := t.TempDir() + destDir := filepath.Join(tempDir, "extracted") + + err := downloadAndExtractArchive(server.URL+"/test.zip", destDir, "Test Archive") + if err == nil { + t.Error("Expected error for unsupported format, got nil") + } + if !strings.Contains(err.Error(), "unsupported archive format") { + t.Errorf("Expected 'unsupported archive format' error, got: %v", err) + } +} + +// Mock test for WASI SDK (without actual download) +func TestWasiSDKExtractionLogic(t *testing.T) { + tempDir := t.TempDir() + + // Create fake WASI SDK directory structure + wasiSdkDir := filepath.Join(tempDir, wasiMacosSubdir) + binDir := filepath.Join(wasiSdkDir, "bin") + err := os.MkdirAll(binDir, 0755) + if err != nil { + t.Fatalf("Failed to create fake WASI SDK structure: %v", err) + } + + // Create fake clang binary + clangPath := filepath.Join(binDir, "clang") + err = os.WriteFile(clangPath, []byte("fake clang"), 0755) + if err != nil { + t.Fatalf("Failed to create fake clang: %v", err) + } + + // Test that function returns correct path for existing SDK + sdkRoot, err := checkDownloadAndExtractWasiSDK(tempDir) + if err != nil { + t.Fatalf("checkDownloadAndExtractWasiSDK failed: %v", err) + } + + expectedRoot := filepath.Join(tempDir, wasiMacosSubdir) + if sdkRoot != expectedRoot { + t.Errorf("Expected SDK root %q, got %q", expectedRoot, sdkRoot) + } +} + +// Test ESP Clang extraction logic with existing directory +func TestESPClangExtractionLogic(t *testing.T) { + tempDir := t.TempDir() + espClangDir := filepath.Join(tempDir, "esp-clang") + + // Create fake ESP Clang directory structure + binDir := filepath.Join(espClangDir, "bin") + err := os.MkdirAll(binDir, 0755) + if err != nil { + t.Fatalf("Failed to create fake ESP Clang structure: %v", err) + } + + // Create fake clang binary + clangPath := filepath.Join(binDir, "clang") + err = os.WriteFile(clangPath, []byte("fake esp clang"), 0755) + if err != nil { + t.Fatalf("Failed to create fake esp clang: %v", err) + } + + // Test that function skips download for existing directory + err = checkDownloadAndExtractESPClang("linux", espClangDir) + if err != nil { + t.Fatalf("checkDownloadAndExtractESPClang failed: %v", err) + } + + // Check that the directory still exists and has the right content + if _, err := os.Stat(clangPath); os.IsNotExist(err) { + t.Error("ESP Clang binary should exist") + } +} + +// Test WASI SDK download and extraction when directory doesn't exist +func TestWasiSDKDownloadWhenNotExists(t *testing.T) { + // Create fake WASI SDK archive with proper structure + files := map[string]string{ + "wasi-sdk-25.0-x86_64-macos/bin/clang": "fake wasi clang binary", + "wasi-sdk-25.0-x86_64-macos/lib/libm.a": "fake math library", + "wasi-sdk-25.0-x86_64-macos/include/stdio.h": "#include ", + } + + archivePath := createTestTarGz(t, files) + defer os.Remove(archivePath) + + // Create test server to serve the archive + archiveContent, err := os.ReadFile(archivePath) + if err != nil { + t.Fatalf("Failed to read test archive: %v", err) + } + + server := createTestServer(t, map[string]string{ + "wasi-sdk-25.0-x86_64-macos.tar.gz": string(archiveContent), + }) + defer server.Close() + + // Override cacheRoot to use a temporary directory + tempCacheRoot := t.TempDir() + originalCacheRoot := cacheRoot + cacheRoot = func() string { return tempCacheRoot } + defer func() { cacheRoot = originalCacheRoot }() + + // Override wasiSdkUrl to use our test server + originalWasiSdkUrl := wasiSdkUrl + wasiSdkUrl = server.URL + "/wasi-sdk-25.0-x86_64-macos.tar.gz" + defer func() { wasiSdkUrl = originalWasiSdkUrl }() + + // Use the cache directory structure + extractDir := filepath.Join(tempCacheRoot, "crosscompile", "wasi") + + // Test download and extract when directory doesn't exist + sdkRoot, err := checkDownloadAndExtractWasiSDK(extractDir) + if err != nil { + t.Fatalf("checkDownloadAndExtractWasiSDK failed: %v", err) + } + + expectedRoot := filepath.Join(extractDir, wasiMacosSubdir) + if sdkRoot != expectedRoot { + t.Errorf("Expected SDK root %q, got %q", expectedRoot, sdkRoot) + } + + // Check that files were extracted correctly + for name, expectedContent := range files { + filePath := filepath.Join(extractDir, name) + content, err := os.ReadFile(filePath) + if err != nil { + t.Errorf("Failed to read extracted file %s: %v", name, err) + continue + } + if string(content) != expectedContent { + t.Errorf("File %s: expected content %q, got %q", name, expectedContent, string(content)) + } + } +} + +// Test ESP Clang download and extraction when directory doesn't exist +func TestESPClangDownloadWhenNotExists(t *testing.T) { + // Create fake ESP Clang archive with proper structure + files := map[string]string{ + "esp-clang/bin/clang": "fake esp clang binary", + "esp-clang/lib/libc.a": "fake c library", + "esp-clang/include/esp32.h": "#define ESP32 1", + } + + archivePath := createTestTarGz(t, files) + defer os.Remove(archivePath) + + // Read the archive content + archiveContent, err := os.ReadFile(archivePath) + if err != nil { + t.Fatalf("Failed to read test archive: %v", err) + } + + server := createTestServer(t, map[string]string{ + "clang-esp-19.1.2_20250820-linux.tar.xz": string(archiveContent), + }) + defer server.Close() + + // Override cacheRoot to use a temporary directory + tempCacheRoot := t.TempDir() + originalCacheRoot := cacheRoot + cacheRoot = func() string { return tempCacheRoot } + defer func() { cacheRoot = originalCacheRoot }() + + // Override espClangBaseUrl to use our test server + originalEspClangBaseUrl := espClangBaseUrl + espClangBaseUrl = server.URL + defer func() { espClangBaseUrl = originalEspClangBaseUrl }() + + // Use a fresh temp directory that doesn't have ESP Clang + espClangDir := filepath.Join(tempCacheRoot, "esp-clang-test") + + // Test download and extract when directory doesn't exist + err = checkDownloadAndExtractESPClang("linux", espClangDir) + if err != nil { + t.Fatalf("checkDownloadAndExtractESPClang failed: %v", err) + } + + // Check that the target directory exists + if _, err := os.Stat(espClangDir); os.IsNotExist(err) { + t.Error("ESP Clang directory should exist after extraction") + } + + // Check that files were extracted correctly to the final destination + for name, expectedContent := range files { + // Remove "esp-clang/" prefix since it gets moved to the final destination + relativePath := strings.TrimPrefix(name, "esp-clang/") + filePath := filepath.Join(espClangDir, relativePath) + content, err := os.ReadFile(filePath) + if err != nil { + t.Errorf("Failed to read extracted file %s: %v", relativePath, err) + continue + } + if string(content) != expectedContent { + t.Errorf("File %s: expected content %q, got %q", relativePath, expectedContent, string(content)) + } + } +} diff --git a/internal/firmware/esp.go b/internal/firmware/esp.go new file mode 100644 index 00000000..c678413c --- /dev/null +++ b/internal/firmware/esp.go @@ -0,0 +1,188 @@ +// From tinygo/builder/esp.go + +package firmware + +import ( + "bytes" + "crypto/sha256" + "debug/elf" + "encoding/binary" + "fmt" + "os" + "sort" + "strings" +) + +type espImageSegment struct { + addr uint32 + data []byte +} + +// makeESPFirmareImage converts an input ELF file to an image file for an ESP32 or +// ESP8266 chip. This is a special purpose image format just for the ESP chip +// family, and is parsed by the on-chip mask ROM bootloader. +// +// The following documentation has been used: +// https://github.com/espressif/esptool/wiki/Firmware-Image-Format +// https://github.com/espressif/esp-idf/blob/8fbb63c2a701c22ccf4ce249f43aded73e134a34/components/bootloader_support/include/esp_image_format.h#L58 +// https://github.com/espressif/esptool/blob/master/esptool.py +func makeESPFirmareImage(infile, outfile, format string) error { + inf, err := elf.Open(infile) + if err != nil { + return err + } + defer inf.Close() + + // Load all segments to be written to the image. These are actually ELF + // sections, not true ELF segments (similar to how esptool does it). + var segments []*espImageSegment + for _, section := range inf.Sections { + if section.Type != elf.SHT_PROGBITS || section.Size == 0 || section.Flags&elf.SHF_ALLOC == 0 { + continue + } + data, err := section.Data() + if err != nil { + return fmt.Errorf("failed to read section data: %w", err) + } + for len(data)%4 != 0 { + // Align segment to 4 bytes. + data = append(data, 0) + } + if uint64(uint32(section.Addr)) != section.Addr { + return fmt.Errorf("section address too big: 0x%x", section.Addr) + } + segments = append(segments, &espImageSegment{ + addr: uint32(section.Addr), + data: data, + }) + } + + // Sort the segments by address. This is what esptool does too. + sort.SliceStable(segments, func(i, j int) bool { return segments[i].addr < segments[j].addr }) + + // Calculate checksum over the segment data. This is used in the image + // footer. + checksum := uint8(0xef) + for _, segment := range segments { + for _, b := range segment.data { + checksum ^= b + } + } + + // Write first to an in-memory buffer, primarily so that we can easily + // calculate a hash over the entire image. + // An added benefit is that we don't need to check for errors all the time. + outf := &bytes.Buffer{} + + // Separate esp32 and esp32-img. The -img suffix indicates we should make an + // image, not just a binary to be flashed at 0x1000 for example. + chip := format + makeImage := false + if strings.HasSuffix(format, "-img") { + makeImage = true + chip = format[:len(format)-len("-img")] + } + + if makeImage { + // The bootloader starts at 0x1000, or 4096. + // TinyGo doesn't use a separate bootloader and runs the entire + // application in the bootloader location. + outf.Write(make([]byte, 4096)) + } + + // Chip IDs. Source: + // https://github.com/espressif/esp-idf/blob/v4.3/components/bootloader_support/include/esp_app_format.h#L22 + chip_id := map[string]uint16{ + "esp32": 0x0000, + "esp32c3": 0x0005, + }[chip] + + // Image header. + switch chip { + case "esp32", "esp32c3": + // Header format: + // https://github.com/espressif/esp-idf/blob/v4.3/components/bootloader_support/include/esp_app_format.h#L71 + // Note: not adding a SHA256 hash as the binary is modified by + // esptool.py while flashing and therefore the hash won't be valid + // anymore. + binary.Write(outf, binary.LittleEndian, struct { + magic uint8 + segment_count uint8 + spi_mode uint8 + spi_speed_size uint8 + entry_addr uint32 + wp_pin uint8 + spi_pin_drv [3]uint8 + chip_id uint16 + min_chip_rev uint8 + reserved [8]uint8 + hash_appended bool + }{ + magic: 0xE9, + segment_count: byte(len(segments)), + spi_mode: 2, // ESP_IMAGE_SPI_MODE_DIO + spi_speed_size: 0x1f, // ESP_IMAGE_SPI_SPEED_80M, ESP_IMAGE_FLASH_SIZE_2MB + entry_addr: uint32(inf.Entry), + wp_pin: 0xEE, // disable WP pin + chip_id: chip_id, + hash_appended: true, // add a SHA256 hash + }) + case "esp8266": + // Header format: + // https://github.com/espressif/esptool/wiki/Firmware-Image-Format + // Basically a truncated version of the ESP32 header. + binary.Write(outf, binary.LittleEndian, struct { + magic uint8 + segment_count uint8 + spi_mode uint8 + spi_speed_size uint8 + entry_addr uint32 + }{ + magic: 0xE9, + segment_count: byte(len(segments)), + spi_mode: 0, // irrelevant, replaced by esptool when flashing + spi_speed_size: 0x20, // spi_speed, spi_size: replaced by esptool when flashing + entry_addr: uint32(inf.Entry), + }) + default: + return fmt.Errorf("builder: unknown binary format %#v, expected esp32 or esp8266", format) + } + + // Write all segments to the image. + // https://github.com/espressif/esptool/wiki/Firmware-Image-Format#segment + for _, segment := range segments { + binary.Write(outf, binary.LittleEndian, struct { + addr uint32 + length uint32 + }{ + addr: segment.addr, + length: uint32(len(segment.data)), + }) + outf.Write(segment.data) + } + + // Footer, including checksum. + // The entire image size must be a multiple of 16, so pad the image to one + // byte less than that before writing the checksum. + outf.Write(make([]byte, 15-outf.Len()%16)) + outf.WriteByte(checksum) + + if chip != "esp8266" { + // SHA256 hash (to protect against image corruption, not for security). + hash := sha256.Sum256(outf.Bytes()) + outf.Write(hash[:]) + } + + // QEMU (or more precisely, qemu-system-xtensa from Espressif) expects the + // image to be a certain size. + if makeImage { + // Use a default image size of 4MB. + grow := 4096*1024 - outf.Len() + if grow > 0 { + outf.Write(make([]byte, grow)) + } + } + + // Write the image to the output file. + return os.WriteFile(outfile, outf.Bytes(), 0666) +} diff --git a/internal/firmware/ext.go b/internal/firmware/ext.go new file mode 100644 index 00000000..3a90ca97 --- /dev/null +++ b/internal/firmware/ext.go @@ -0,0 +1,16 @@ +package firmware + +import "strings" + +// BinaryExt returns the binary file extension based on the binary format +// Returns ".bin" for ESP-based formats, "" for others +func BinaryExt(binaryFormat string) string { + if strings.HasPrefix(binaryFormat, "esp") { + return ".bin" + } else if strings.HasPrefix(binaryFormat, "uf2") { + return ".uf2" + } else if strings.HasPrefix(binaryFormat, "nrf-dfu") { + return ".zip" + } + return "" +} diff --git a/internal/firmware/ext_test.go b/internal/firmware/ext_test.go new file mode 100644 index 00000000..cfbe1f13 --- /dev/null +++ b/internal/firmware/ext_test.go @@ -0,0 +1,31 @@ +//go:build !llgo +// +build !llgo + +package firmware + +import "testing" + +func TestBinaryExt(t *testing.T) { + tests := []struct { + name string + binaryFormat string + expected string + }{ + {"ESP32", "esp32", ".bin"}, + {"ESP8266", "esp8266", ".bin"}, + {"ESP32C3", "esp32c3", ".bin"}, + {"UF2", "uf2", ".uf2"}, + {"ELF", "elf", ""}, + {"Empty", "", ""}, + {"NRF-DFU", "nrf-dfu", ".zip"}, + } + + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + result := BinaryExt(tt.binaryFormat) + if result != tt.expected { + t.Errorf("BinaryExt() = %q, want %q", result, tt.expected) + } + }) + } +} diff --git a/internal/firmware/firmware.go b/internal/firmware/firmware.go new file mode 100644 index 00000000..bbe42e4e --- /dev/null +++ b/internal/firmware/firmware.go @@ -0,0 +1,19 @@ +package firmware + +import ( + "fmt" + "strings" +) + +// MakeFirmwareImage creates a firmware image from the given input file. +func MakeFirmwareImage(infile, outfile, format, fmtDetail string) error { + if strings.HasPrefix(format, "esp") { + return makeESPFirmareImage(infile, outfile, format) + } else if format == "uf2" { + uf2Family := fmtDetail + return convertELFFileToUF2File(infile, outfile, uf2Family) + } else if format == "nrf-dfu" { + return makeDFUFirmwareImage(infile, outfile) + } + return fmt.Errorf("unsupported firmware format: %s", format) +} diff --git a/internal/firmware/nrfutil.go b/internal/firmware/nrfutil.go new file mode 100644 index 00000000..f0937c71 --- /dev/null +++ b/internal/firmware/nrfutil.go @@ -0,0 +1,118 @@ +// From tinygo/builder/nrfutil.go + +package firmware + +import ( + "archive/zip" + "bytes" + "encoding/binary" + "encoding/json" + "os" + + "github.com/sigurn/crc16" +) + +// Structure of the manifest.json file. +type jsonManifest struct { + Manifest struct { + Application struct { + BinaryFile string `json:"bin_file"` + DataFile string `json:"dat_file"` + InitPacketData nrfInitPacket `json:"init_packet_data"` + } `json:"application"` + DFUVersion float64 `json:"dfu_version"` // yes, this is a JSON number, not a string + } `json:"manifest"` +} + +// Structure of the init packet. +// Source: +// https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/lib/sdk11/components/libraries/bootloader_dfu/dfu_init.h#L47-L57 +type nrfInitPacket struct { + ApplicationVersion uint32 `json:"application_version"` + DeviceRevision uint16 `json:"device_revision"` + DeviceType uint16 `json:"device_type"` + FirmwareCRC16 uint16 `json:"firmware_crc16"` + SoftDeviceRequired []uint16 `json:"softdevice_req"` // this is actually a variable length array +} + +// Create the init packet (the contents of application.dat). +func (p nrfInitPacket) createInitPacket() []byte { + buf := &bytes.Buffer{} + binary.Write(buf, binary.LittleEndian, p.DeviceType) // uint16_t device_type; + binary.Write(buf, binary.LittleEndian, p.DeviceRevision) // uint16_t device_rev; + binary.Write(buf, binary.LittleEndian, p.ApplicationVersion) // uint32_t app_version; + binary.Write(buf, binary.LittleEndian, uint16(len(p.SoftDeviceRequired))) // uint16_t softdevice_len; + binary.Write(buf, binary.LittleEndian, p.SoftDeviceRequired) // uint16_t softdevice[1]; + binary.Write(buf, binary.LittleEndian, p.FirmwareCRC16) + return buf.Bytes() +} + +// Make a Nordic DFU firmware image from an ELF file. +func makeDFUFirmwareImage(infile, outfile string) error { + // Read ELF file as input and convert it to a binary image file. + _, data, err := extractROM(infile) + if err != nil { + return err + } + + // Create the zip file in memory. + // It won't be very large anyway. + buf := &bytes.Buffer{} + w := zip.NewWriter(buf) + + // Write the application binary to the zip file. + binw, err := w.Create("application.bin") + if err != nil { + return err + } + _, err = binw.Write(data) + if err != nil { + return err + } + + // Create the init packet. + initPacket := nrfInitPacket{ + ApplicationVersion: 0xffff_ffff, // appears to be unused by the Adafruit bootloader + DeviceRevision: 0xffff, // DFU_DEVICE_REVISION_EMPTY + DeviceType: 0x0052, // ADAFRUIT_DEVICE_TYPE + FirmwareCRC16: crc16.Checksum(data, crc16.MakeTable(crc16.CRC16_CCITT_FALSE)), + SoftDeviceRequired: []uint16{0xfffe}, // DFU_SOFTDEVICE_ANY + } + + // Write the init packet to the zip file. + datw, err := w.Create("application.dat") + if err != nil { + return err + } + _, err = datw.Write(initPacket.createInitPacket()) + if err != nil { + return err + } + + // Create the JSON manifest. + manifest := &jsonManifest{} + manifest.Manifest.Application.BinaryFile = "application.bin" + manifest.Manifest.Application.DataFile = "application.dat" + manifest.Manifest.Application.InitPacketData = initPacket + manifest.Manifest.DFUVersion = 0.5 + + // Write the JSON manifest to the file. + jsonw, err := w.Create("manifest.json") + if err != nil { + return err + } + enc := json.NewEncoder(jsonw) + enc.SetIndent("", " ") + err = enc.Encode(manifest) + if err != nil { + return err + } + + // Finish the zip file. + err = w.Close() + if err != nil { + return err + } + + return os.WriteFile(outfile, buf.Bytes(), 0o666) +} diff --git a/internal/firmware/objcopy.go b/internal/firmware/objcopy.go new file mode 100644 index 00000000..e163f41f --- /dev/null +++ b/internal/firmware/objcopy.go @@ -0,0 +1,133 @@ +// From tinygo/builder/objcopy.go + +package firmware + +import ( + "debug/elf" + "io" + "os" + "sort" +) + +// maxPadBytes is the maximum allowed bytes to be padded in a rom extraction +// this value is currently defined by Nintendo Switch Page Alignment (4096 bytes) +const maxPadBytes = 4095 + +// objcopyError is an error returned by functions that act like objcopy. +type objcopyError struct { + Op string + Err error +} + +func (e objcopyError) Error() string { + if e.Err == nil { + return e.Op + } + return e.Op + ": " + e.Err.Error() +} + +type progSlice []*elf.Prog + +func (s progSlice) Len() int { return len(s) } +func (s progSlice) Less(i, j int) bool { return s[i].Paddr < s[j].Paddr } +func (s progSlice) Swap(i, j int) { s[i], s[j] = s[j], s[i] } + +// extractROM extracts a firmware image and the first load address from the +// given ELF file. It tries to emulate the behavior of objcopy. +func extractROM(path string) (uint64, []byte, error) { + f, err := elf.Open(path) + if err != nil { + return 0, nil, objcopyError{"failed to open ELF file to extract text segment", err} + } + defer f.Close() + + // The GNU objcopy command does the following for firmware extraction (from + // the man page): + // > When objcopy generates a raw binary file, it will essentially produce a + // > memory dump of the contents of the input object file. All symbols and + // > relocation information will be discarded. The memory dump will start at + // > the load address of the lowest section copied into the output file. + + // Find the lowest section address. + startAddr := ^uint64(0) + for _, section := range f.Sections { + if section.Type != elf.SHT_PROGBITS || section.Flags&elf.SHF_ALLOC == 0 { + continue + } + if section.Addr < startAddr { + startAddr = section.Addr + } + } + + progs := make(progSlice, 0, 2) + for _, prog := range f.Progs { + if prog.Type != elf.PT_LOAD || prog.Filesz == 0 || prog.Off == 0 { + continue + } + progs = append(progs, prog) + } + if len(progs) == 0 { + return 0, nil, objcopyError{"file does not contain ROM segments: " + path, nil} + } + sort.Sort(progs) + + var rom []byte + for _, prog := range progs { + romEnd := progs[0].Paddr + uint64(len(rom)) + if prog.Paddr > romEnd && prog.Paddr < romEnd+16 { + // Sometimes, the linker seems to insert a bit of padding between + // segments. Simply zero-fill these parts. + rom = append(rom, make([]byte, prog.Paddr-romEnd)...) + } + if prog.Paddr != progs[0].Paddr+uint64(len(rom)) { + diff := prog.Paddr - (progs[0].Paddr + uint64(len(rom))) + if diff > maxPadBytes { + return 0, nil, objcopyError{"ROM segments are non-contiguous: " + path, nil} + } + // Pad the difference + rom = append(rom, make([]byte, diff)...) + } + data, err := io.ReadAll(prog.Open()) + if err != nil { + return 0, nil, objcopyError{"failed to extract segment from ELF file: " + path, err} + } + rom = append(rom, data...) + } + if progs[0].Paddr < startAddr { + // The lowest memory address is before the first section. This means + // that there is some extra data loaded at the start of the image that + // should be discarded. + // Example: ELF files where .text doesn't start at address 0 because + // there is a bootloader at the start. + return startAddr, rom[startAddr-progs[0].Paddr:], nil + } else { + return progs[0].Paddr, rom, nil + } +} + +// objcopy converts an ELF file to a different (simpler) output file format: +// .bin or .hex. It extracts only the .text section. +func objcopy(infile, outfile, binaryFormat string) error { + f, err := os.OpenFile(outfile, os.O_RDWR|os.O_CREATE|os.O_TRUNC, 0666) + if err != nil { + return err + } + defer f.Close() + + // Read the .text segment. + _, data, err := extractROM(infile) + if err != nil { + return err + } + + // Write to the file, in the correct format. + switch binaryFormat { + case "bin": + // The start address is not stored in raw firmware files (therefore you + // should use .hex files in most cases). + _, err := f.Write(data) + return err + default: + panic("unreachable") + } +} diff --git a/internal/firmware/uf2.go b/internal/firmware/uf2.go new file mode 100644 index 00000000..bfc99b3c --- /dev/null +++ b/internal/firmware/uf2.go @@ -0,0 +1,155 @@ +// From tinygo/builder/uf2.go + +package firmware + +// This file converts firmware files from BIN to UF2 format before flashing. +// +// For more information about the UF2 firmware file format, please see: +// https://github.com/Microsoft/uf2 +// +// + +import ( + "bytes" + "encoding/binary" + "os" + "strconv" +) + +// convertELFFileToUF2File converts an ELF file to a UF2 file. +func convertELFFileToUF2File(infile, outfile string, uf2FamilyID string) error { + // Read the .text segment. + targetAddress, data, err := extractROM(infile) + if err != nil { + return err + } + + output, _, err := convertBinToUF2(data, uint32(targetAddress), uf2FamilyID) + if err != nil { + return err + } + return os.WriteFile(outfile, output, 0644) +} + +// convertBinToUF2 converts the binary bytes in input to UF2 formatted data. +func convertBinToUF2(input []byte, targetAddr uint32, uf2FamilyID string) ([]byte, int, error) { + blocks := split(input, 256) + output := make([]byte, 0) + + bl, err := newUF2Block(targetAddr, uf2FamilyID) + if err != nil { + return nil, 0, err + } + bl.SetNumBlocks(len(blocks)) + + for i := 0; i < len(blocks); i++ { + bl.SetBlockNo(i) + bl.SetData(blocks[i]) + + output = append(output, bl.Bytes()...) + bl.IncrementAddress(bl.payloadSize) + } + + return output, len(blocks), nil +} + +const ( + uf2MagicStart0 = 0x0A324655 // "UF2\n" + uf2MagicStart1 = 0x9E5D5157 // Randomly selected + uf2MagicEnd = 0x0AB16F30 // Ditto +) + +// uf2Block is the structure used for each UF2 code block sent to device. +type uf2Block struct { + magicStart0 uint32 + magicStart1 uint32 + flags uint32 + targetAddr uint32 + payloadSize uint32 + blockNo uint32 + numBlocks uint32 + familyID uint32 + data []uint8 + magicEnd uint32 +} + +// newUF2Block returns a new uf2Block struct that has been correctly populated +func newUF2Block(targetAddr uint32, uf2FamilyID string) (*uf2Block, error) { + var flags uint32 + var familyID uint32 + if uf2FamilyID != "" { + flags |= flagFamilyIDPresent + v, err := strconv.ParseUint(uf2FamilyID, 0, 32) + if err != nil { + return nil, err + } + familyID = uint32(v) + } + return &uf2Block{magicStart0: uf2MagicStart0, + magicStart1: uf2MagicStart1, + magicEnd: uf2MagicEnd, + targetAddr: targetAddr, + flags: flags, + familyID: familyID, + payloadSize: 256, + data: make([]byte, 476), + }, nil +} + +const ( + flagFamilyIDPresent = 0x00002000 +) + +// Bytes converts the uf2Block to a slice of bytes that can be written to file. +func (b *uf2Block) Bytes() []byte { + buf := bytes.NewBuffer(make([]byte, 0, 512)) + binary.Write(buf, binary.LittleEndian, b.magicStart0) + binary.Write(buf, binary.LittleEndian, b.magicStart1) + binary.Write(buf, binary.LittleEndian, b.flags) + binary.Write(buf, binary.LittleEndian, b.targetAddr) + binary.Write(buf, binary.LittleEndian, b.payloadSize) + binary.Write(buf, binary.LittleEndian, b.blockNo) + binary.Write(buf, binary.LittleEndian, b.numBlocks) + binary.Write(buf, binary.LittleEndian, b.familyID) + binary.Write(buf, binary.LittleEndian, b.data) + binary.Write(buf, binary.LittleEndian, b.magicEnd) + + return buf.Bytes() +} + +// IncrementAddress moves the target address pointer forward by count bytes. +func (b *uf2Block) IncrementAddress(count uint32) { + b.targetAddr += b.payloadSize +} + +// SetData sets the data to be used for the current block. +func (b *uf2Block) SetData(d []byte) { + b.data = make([]byte, 476) + copy(b.data[:], d) +} + +// SetBlockNo sets the current block number to be used. +func (b *uf2Block) SetBlockNo(bn int) { + b.blockNo = uint32(bn) +} + +// SetNumBlocks sets the total number of blocks for this UF2 file. +func (b *uf2Block) SetNumBlocks(total int) { + b.numBlocks = uint32(total) +} + +// split splits a slice of bytes into a slice of byte slices of a specific size limit. +func split(input []byte, limit int) [][]byte { + var block []byte + output := make([][]byte, 0, len(input)/limit+1) + for len(input) >= limit { + // add all blocks + block, input = input[:limit], input[limit:] + output = append(output, block) + } + if len(input) > 0 { + // add remaining block (that isn't full sized) + output = append(output, input) + } + return output +} diff --git a/internal/targets/config.go b/internal/targets/config.go index 66874434..99938e74 100644 --- a/internal/targets/config.go +++ b/internal/targets/config.go @@ -16,9 +16,42 @@ type Config struct { GOARCH string `json:"goarch"` // Compiler and linker configuration - Linker string `json:"linker"` - CFlags []string `json:"cflags"` - LDFlags []string `json:"ldflags"` + Linker string `json:"linker"` + LinkerScript string `json:"linkerscript"` + CFlags []string `json:"cflags"` + LDFlags []string `json:"ldflags"` + ExtraFiles []string `json:"extra-files"` + + // Code generation configuration + CodeModel string `json:"code-model"` + TargetABI string `json:"target-abi"` + RelocationModel string `json:"relocation-model"` + + // Binary and firmware configuration + BinaryFormat string `json:"binary-format"` + // UF2 configuration + UF2FamilyID string `json:"uf2-family-id"` + + // Flash and deployment configuration + FlashCommand string `json:"flash-command"` + FlashMethod string `json:"flash-method"` + Flash1200BpsReset string `json:"flash-1200-bps-reset"` + + // Mass storage device configuration + MSDVolumeName []string `json:"msd-volume-name"` + MSDFirmwareName string `json:"msd-firmware-name"` + + // Device-specific configuration + RP2040BootPatch bool `json:"rp2040-boot-patch"` + + // Debug and emulation configuration + Emulator string `json:"emulator"` + GDB []string `json:"gdb"` + + // OpenOCD configuration + OpenOCDInterface string `json:"openocd-interface"` + OpenOCDTransport string `json:"openocd-transport"` + OpenOCDTarget string `json:"openocd-target"` } // RawConfig represents the raw JSON configuration before inheritance resolution @@ -32,6 +65,13 @@ func (c *Config) IsEmpty() bool { return c.Name == "" && c.LLVMTarget == "" && c.GOOS == "" && c.GOARCH == "" } +func (c *Config) FormatDetail() string { + if c.BinaryFormat == "uf2" { + return c.UF2FamilyID + } + return "" +} + // HasInheritance returns true if this config inherits from other configs func (rc *RawConfig) HasInheritance() bool { return len(rc.Inherits) > 0 diff --git a/internal/targets/loader.go b/internal/targets/loader.go index cea4ee6d..ebcd0c07 100644 --- a/internal/targets/loader.go +++ b/internal/targets/loader.go @@ -137,6 +137,51 @@ func (l *Loader) mergeConfig(dst, src *Config) { if src.Linker != "" { dst.Linker = src.Linker } + if src.LinkerScript != "" { + dst.LinkerScript = src.LinkerScript + } + if src.CodeModel != "" { + dst.CodeModel = src.CodeModel + } + if src.TargetABI != "" { + dst.TargetABI = src.TargetABI + } + if src.RelocationModel != "" { + dst.RelocationModel = src.RelocationModel + } + if src.BinaryFormat != "" { + dst.BinaryFormat = src.BinaryFormat + } + if src.FlashCommand != "" { + dst.FlashCommand = src.FlashCommand + } + if src.FlashMethod != "" { + dst.FlashMethod = src.FlashMethod + } + if src.Flash1200BpsReset != "" { + dst.Flash1200BpsReset = src.Flash1200BpsReset + } + if src.MSDFirmwareName != "" { + dst.MSDFirmwareName = src.MSDFirmwareName + } + if src.UF2FamilyID != "" { + dst.UF2FamilyID = src.UF2FamilyID + } + if src.RP2040BootPatch { + dst.RP2040BootPatch = src.RP2040BootPatch + } + if src.Emulator != "" { + dst.Emulator = src.Emulator + } + if src.OpenOCDInterface != "" { + dst.OpenOCDInterface = src.OpenOCDInterface + } + if src.OpenOCDTransport != "" { + dst.OpenOCDTransport = src.OpenOCDTransport + } + if src.OpenOCDTarget != "" { + dst.OpenOCDTarget = src.OpenOCDTarget + } // Merge slices (append, don't replace) if len(src.BuildTags) > 0 { @@ -148,6 +193,15 @@ func (l *Loader) mergeConfig(dst, src *Config) { if len(src.LDFlags) > 0 { dst.LDFlags = append(dst.LDFlags, src.LDFlags...) } + if len(src.ExtraFiles) > 0 { + dst.ExtraFiles = append(dst.ExtraFiles, src.ExtraFiles...) + } + if len(src.MSDVolumeName) > 0 { + dst.MSDVolumeName = append(dst.MSDVolumeName, src.MSDVolumeName...) + } + if len(src.GDB) > 0 { + dst.GDB = append(dst.GDB, src.GDB...) + } } // GetTargetsDir returns the targets directory path diff --git a/internal/targets/targets_test.go b/internal/targets/targets_test.go index bfe5c677..bf2407e0 100644 --- a/internal/targets/targets_test.go +++ b/internal/targets/targets_test.go @@ -61,7 +61,8 @@ func TestLoaderLoadRaw(t *testing.T) { "goarch": "arm", "build-tags": ["test", "embedded"], "cflags": ["-Os", "-g"], - "ldflags": ["--gc-sections"] + "ldflags": ["--gc-sections"], + "binary-format": "uf2" }` configPath := filepath.Join(tempDir, "test-target.json") @@ -87,6 +88,9 @@ func TestLoaderLoadRaw(t *testing.T) { if len(config.BuildTags) != 2 || config.BuildTags[0] != "test" || config.BuildTags[1] != "embedded" { t.Errorf("Expected build-tags [test, embedded], got %v", config.BuildTags) } + if config.BinaryFormat != "uf2" { + t.Errorf("Expected binary-format 'uf2', got '%s'", config.BinaryFormat) + } } func TestLoaderInheritance(t *testing.T) { @@ -99,7 +103,8 @@ func TestLoaderInheritance(t *testing.T) { "goos": "linux", "goarch": "arm", "cflags": ["-Os"], - "ldflags": ["--gc-sections"] + "ldflags": ["--gc-sections"], + "binary-format": "elf" }` // Create child config that inherits from parent @@ -108,7 +113,8 @@ func TestLoaderInheritance(t *testing.T) { "cpu": "cortex-m4", "build-tags": ["child"], "cflags": ["-O2"], - "ldflags": ["-g"] + "ldflags": ["-g"], + "binary-format": "uf2" }` parentPath := filepath.Join(tempDir, "parent.json") @@ -143,6 +149,11 @@ func TestLoaderInheritance(t *testing.T) { t.Errorf("Expected overridden cpu 'cortex-m4', got '%s'", config.CPU) } + // Check binary-format override + if config.BinaryFormat != "uf2" { + t.Errorf("Expected overridden binary-format 'uf2', got '%s'", config.BinaryFormat) + } + // Check merged arrays expectedCFlags := []string{"-Os", "-O2"} if len(config.CFlags) != 2 || config.CFlags[0] != "-Os" || config.CFlags[1] != "-O2" { diff --git a/targets/atmega1280.json b/targets/atmega1280.json index 34e78f41..3c0aac51 100644 --- a/targets/atmega1280.json +++ b/targets/atmega1280.json @@ -6,9 +6,9 @@ "ldflags": [ "--defsym=_stack_size=512" ], - "linkerscript": "src/device/avr/atmega1280.ld", + "linkerscript": "targets/device/avr/atmega1280.ld", "extra-files": [ "targets/avr.S", - "src/device/avr/atmega1280.s" + "targets/device/avr/atmega1280.s" ] } diff --git a/targets/atmega1284p.json b/targets/atmega1284p.json index 501fb58d..4747ed21 100644 --- a/targets/atmega1284p.json +++ b/targets/atmega1284p.json @@ -7,10 +7,10 @@ "--defsym=_bootloader_size=0", "--defsym=_stack_size=512" ], - "linkerscript": "src/device/avr/atmega1284p.ld", + "linkerscript": "targets/device/avr/atmega1284p.ld", "extra-files": [ "targets/avr.S", - "src/device/avr/atmega1284p.s" + "targets/device/avr/atmega1284p.s" ], "emulator": "simavr -m atmega1284p -f 20000000 {}" } diff --git a/targets/atmega2560.json b/targets/atmega2560.json index a00179ef..46a32b96 100644 --- a/targets/atmega2560.json +++ b/targets/atmega2560.json @@ -6,9 +6,9 @@ "ldflags": [ "--defsym=_stack_size=512" ], - "linkerscript": "src/device/avr/atmega2560.ld", + "linkerscript": "targets/device/avr/atmega2560.ld", "extra-files": [ "targets/avr.S", - "src/device/avr/atmega2560.s" + "targets/device/avr/atmega2560.s" ] } diff --git a/targets/atmega328p.json b/targets/atmega328p.json index d4098d4b..4431eb9d 100644 --- a/targets/atmega328p.json +++ b/targets/atmega328p.json @@ -3,9 +3,9 @@ "cpu": "atmega328p", "build-tags": ["atmega328p", "atmega", "avr5"], "serial": "uart", - "linkerscript": "src/device/avr/atmega328p.ld", + "linkerscript": "targets/device/avr/atmega328p.ld", "extra-files": [ "targets/avr.S", - "src/device/avr/atmega328p.s" + "targets/device/avr/atmega328p.s" ] } diff --git a/targets/atmega328pb.json b/targets/atmega328pb.json index c4e1b447..1fdd22dc 100644 --- a/targets/atmega328pb.json +++ b/targets/atmega328pb.json @@ -7,9 +7,9 @@ "--defsym=_stack_size=512" ], "serial": "uart", - "linkerscript": "src/device/avr/atmega328pb.ld", + "linkerscript": "targets/device/avr/atmega328pb.ld", "extra-files": [ "targets/avr.S", - "src/device/avr/atmega328pb.s" + "targets/device/avr/atmega328pb.s" ] } diff --git a/targets/atmega32u4.json b/targets/atmega32u4.json index 7aa2c08b..48b65498 100644 --- a/targets/atmega32u4.json +++ b/targets/atmega32u4.json @@ -3,9 +3,9 @@ "cpu": "atmega32u4", "build-tags": ["atmega32u4", "avr5"], "serial": "none", - "linkerscript": "src/device/avr/atmega32u4.ld", + "linkerscript": "targets/device/avr/atmega32u4.ld", "extra-files": [ "targets/avr.S", - "src/device/avr/atmega32u4.s" + "targets/device/avr/atmega32u4.s" ] } diff --git a/targets/atsamd21e18a.json b/targets/atsamd21e18a.json index 92b671c9..96d8de47 100644 --- a/targets/atsamd21e18a.json +++ b/targets/atsamd21e18a.json @@ -4,7 +4,7 @@ "serial": "usb", "linkerscript": "targets/atsamd21.ld", "extra-files": [ - "src/device/sam/atsamd21e18a.s" + "targets/device/sam/atsamd21e18a.s" ], "openocd-transport": "swd", "openocd-target": "at91samdXX" diff --git a/targets/atsamd21g18a.json b/targets/atsamd21g18a.json index db46c962..689ab3c2 100644 --- a/targets/atsamd21g18a.json +++ b/targets/atsamd21g18a.json @@ -4,7 +4,7 @@ "serial": "usb", "linkerscript": "targets/atsamd21.ld", "extra-files": [ - "src/device/sam/atsamd21g18a.s" + "targets/device/sam/atsamd21g18a.s" ], "openocd-transport": "swd", "openocd-target": "at91samdXX" diff --git a/targets/atsamd51g19a.json b/targets/atsamd51g19a.json index 4534d1c1..81cfa1c4 100644 --- a/targets/atsamd51g19a.json +++ b/targets/atsamd51g19a.json @@ -3,7 +3,7 @@ "build-tags": ["atsamd51g19a", "atsamd51g19", "atsamd51", "sam"], "linkerscript": "targets/atsamd51.ld", "extra-files": [ - "src/device/sam/atsamd51g19a.s" + "targets/device/sam/atsamd51g19a.s" ], "openocd-transport": "swd", "openocd-target": "atsame5x" diff --git a/targets/atsamd51j19a.json b/targets/atsamd51j19a.json index 2493ca4d..99ed65a5 100644 --- a/targets/atsamd51j19a.json +++ b/targets/atsamd51j19a.json @@ -3,7 +3,7 @@ "build-tags": ["atsamd51j19a", "atsamd51j19", "atsamd51", "sam"], "linkerscript": "targets/atsamd51.ld", "extra-files": [ - "src/device/sam/atsamd51j19a.s" + "targets/device/sam/atsamd51j19a.s" ], "openocd-transport": "swd", "openocd-target": "atsame5x" diff --git a/targets/atsamd51j20a.json b/targets/atsamd51j20a.json index 9f59e32d..79e0a19d 100644 --- a/targets/atsamd51j20a.json +++ b/targets/atsamd51j20a.json @@ -3,7 +3,7 @@ "build-tags": ["sam", "atsamd51", "atsamd51j20", "atsamd51j20a"], "linkerscript": "targets/atsamd51j20a.ld", "extra-files": [ - "src/device/sam/atsamd51j20a.s" + "targets/device/sam/atsamd51j20a.s" ], "openocd-transport": "swd", "openocd-target": "atsame5x" diff --git a/targets/atsamd51p19a.json b/targets/atsamd51p19a.json index 6b2f6b5b..c1114d3d 100644 --- a/targets/atsamd51p19a.json +++ b/targets/atsamd51p19a.json @@ -3,7 +3,7 @@ "build-tags": ["atsamd51p19a", "atsamd51p19", "atsamd51", "sam"], "linkerscript": "targets/atsamd51.ld", "extra-files": [ - "src/device/sam/atsamd51p19a.s" + "targets/device/sam/atsamd51p19a.s" ], "openocd-transport": "swd", "openocd-target": "atsame5x" diff --git a/targets/atsamd51p20a.json b/targets/atsamd51p20a.json index bc66ca03..3929818f 100644 --- a/targets/atsamd51p20a.json +++ b/targets/atsamd51p20a.json @@ -3,7 +3,7 @@ "build-tags": ["sam", "atsamd51", "atsamd51p20", "atsamd51p20a"], "linkerscript": "targets/atsamd51p20a.ld", "extra-files": [ - "src/device/sam/atsamd51p20a.s" + "targets/device/sam/atsamd51p20a.s" ], "openocd-transport": "swd", "openocd-target": "atsame5x" diff --git a/targets/atsame51j19a.json b/targets/atsame51j19a.json index 98136769..447da461 100644 --- a/targets/atsame51j19a.json +++ b/targets/atsame51j19a.json @@ -3,7 +3,7 @@ "build-tags": ["atsame51j19a", "atsame51j19", "atsame51", "atsame5x", "sam"], "linkerscript": "targets/atsame5xx19.ld", "extra-files": [ - "src/device/sam/atsame51j19a.s" + "targets/device/sam/atsame51j19a.s" ], "openocd-transport": "swd", "openocd-target": "atsame5x" diff --git a/targets/atsame54p20a.json b/targets/atsame54p20a.json index f2450fb4..62ad734b 100644 --- a/targets/atsame54p20a.json +++ b/targets/atsame54p20a.json @@ -3,7 +3,7 @@ "build-tags": ["sam", "atsame5x", "atsame54", "atsame54p20", "atsame54p20a"], "linkerscript": "targets/atsame5xx20-no-bootloader.ld", "extra-files": [ - "src/device/sam/atsame54p20a.s" + "targets/device/sam/atsame54p20a.s" ], "openocd-transport": "swd", "openocd-target": "atsame5x" diff --git a/targets/attiny1616.json b/targets/attiny1616.json index 38e645ae..f64f4b5a 100644 --- a/targets/attiny1616.json +++ b/targets/attiny1616.json @@ -6,9 +6,9 @@ "cflags": [ "-D__AVR_ARCH__=103" ], - "linkerscript": "src/device/avr/attiny1616.ld", + "linkerscript": "targets/device/avr/attiny1616.ld", "extra-files": [ - "src/device/avr/attiny1616.s" + "targets/device/avr/attiny1616.s" ], "flash-command": "pymcuprog write -f {hex} --erase --verify -d attiny1616 -t uart -u {port}" } diff --git a/targets/attiny85.json b/targets/attiny85.json index 3fb11114..8068ef56 100644 --- a/targets/attiny85.json +++ b/targets/attiny85.json @@ -5,9 +5,9 @@ "cflags": [ "-D__AVR_ARCH__=25" ], - "linkerscript": "src/device/avr/attiny85.ld", + "linkerscript": "targets/device/avr/attiny85.ld", "extra-files": [ "targets/avr.S", - "src/device/avr/attiny85.s" + "targets/device/avr/attiny85.s" ] } diff --git a/targets/avr.json b/targets/avr.json index 587a3e56..d4f52e54 100644 --- a/targets/avr.json +++ b/targets/avr.json @@ -16,9 +16,5 @@ "-T", "targets/avr.ld", "--gc-sections" ], - "extra-files": [ - "src/internal/task/task_stack_avr.S", - "src/runtime/asm_avr.S" - ], "gdb": ["avr-gdb"] } diff --git a/targets/avrtiny.json b/targets/avrtiny.json index 7cb1581f..6e7dde95 100644 --- a/targets/avrtiny.json +++ b/targets/avrtiny.json @@ -17,8 +17,6 @@ "--gc-sections" ], "extra-files": [ - "src/internal/task/task_stack_avr.S", - "src/runtime/asm_avr.S", "targets/avrtiny.S" ], "gdb": ["avr-gdb"] diff --git a/targets/bluepill.json b/targets/bluepill.json index 752261f4..ab03fc96 100644 --- a/targets/bluepill.json +++ b/targets/bluepill.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32.ld", "extra-files": [ - "src/device/stm32/stm32f103.s" + "targets/device/stm32/stm32f103.s" ], "flash-method": "openocd", "openocd-interface": "stlink-v2", diff --git a/targets/cortex-m.json b/targets/cortex-m.json index cf21969f..f38badd9 100644 --- a/targets/cortex-m.json +++ b/targets/cortex-m.json @@ -22,9 +22,7 @@ "--gc-sections" ], "extra-files": [ - "src/device/arm/cortexm.S", - "src/internal/task/task_stack_cortexm.S", - "src/runtime/asm_arm.S" + "targets/device/arm/cortexm.S" ], "gdb": ["gdb-multiarch", "arm-none-eabi-gdb", "gdb"] } diff --git a/targets/device/arm/cortexm.S b/targets/device/arm/cortexm.S new file mode 100644 index 00000000..e9b15aaf --- /dev/null +++ b/targets/device/arm/cortexm.S @@ -0,0 +1,37 @@ +.syntax unified +.cfi_sections .debug_frame + +.section .text.HardFault_Handler +.global HardFault_Handler +.type HardFault_Handler, %function +HardFault_Handler: + .cfi_startproc + // Put the old stack pointer in the first argument, for easy debugging. This + // is especially useful on Cortex-M0, which supports far fewer debug + // facilities. + mov r0, sp + + // Load the default stack pointer from address 0 so that we can call normal + // functions again that expect a working stack. However, it will corrupt the + // old stack so the function below must not attempt to recover from this + // fault. + movs r3, #0 + ldr r3, [r3] + mov sp, r3 + + // Continue handling this error in Go. + bl handleHardFault + .cfi_endproc +.size HardFault_Handler, .-HardFault_Handler + +// This is a convenience function for semihosting support. +// At some point, this should be replaced by inline assembly. +.section .text.SemihostingCall +.global SemihostingCall +.type SemihostingCall, %function +SemihostingCall: + .cfi_startproc + bkpt 0xab + bx lr + .cfi_endproc +.size SemihostingCall, .-SemihostingCall diff --git a/targets/device/arm/interrupts.c b/targets/device/arm/interrupts.c new file mode 100644 index 00000000..d94a3134 --- /dev/null +++ b/targets/device/arm/interrupts.c @@ -0,0 +1,22 @@ +#include + +void EnableInterrupts(uintptr_t mask) { + asm volatile( + "msr PRIMASK, %0" + : + : "r"(mask) + : "memory" + ); +} + +uintptr_t DisableInterrupts() { + uintptr_t mask; + asm volatile( + "mrs %0, PRIMASK\n\t" + "cpsid i" + : "=r"(mask) + : + : "memory" + ); + return mask; +} \ No newline at end of file diff --git a/targets/device/avr/at90can128.ld b/targets/device/avr/at90can128.ld new file mode 100644 index 00000000..af9c5f8e --- /dev/null +++ b/targets/device/avr/at90can128.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90CAN128.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 37; diff --git a/targets/device/avr/at90can128.s b/targets/device/avr/at90can128.s new file mode 100644 index 00000000..d6adf639 --- /dev/null +++ b/targets/device/avr/at90can128.s @@ -0,0 +1,98 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90CAN128.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_CANIT + jmp __vector_OVRIT + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_CANIT + IRQ __vector_OVRIT + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90can32.ld b/targets/device/avr/at90can32.ld new file mode 100644 index 00000000..416e7d75 --- /dev/null +++ b/targets/device/avr/at90can32.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90CAN32.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 37; diff --git a/targets/device/avr/at90can32.s b/targets/device/avr/at90can32.s new file mode 100644 index 00000000..c4b74f37 --- /dev/null +++ b/targets/device/avr/at90can32.s @@ -0,0 +1,98 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90CAN32.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_CANIT + jmp __vector_OVRIT + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_CANIT + IRQ __vector_OVRIT + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90can64.ld b/targets/device/avr/at90can64.ld new file mode 100644 index 00000000..02df5bcd --- /dev/null +++ b/targets/device/avr/at90can64.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90CAN64.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 37; diff --git a/targets/device/avr/at90can64.s b/targets/device/avr/at90can64.s new file mode 100644 index 00000000..df136777 --- /dev/null +++ b/targets/device/avr/at90can64.s @@ -0,0 +1,98 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90CAN64.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_CANIT + jmp __vector_OVRIT + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_CANIT + IRQ __vector_OVRIT + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90pwm1.ld b/targets/device/avr/at90pwm1.ld new file mode 100644 index 00000000..ff8681d0 --- /dev/null +++ b/targets/device/avr/at90pwm1.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90PWM1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 32; diff --git a/targets/device/avr/at90pwm1.s b/targets/device/avr/at90pwm1.s new file mode 100644 index 00000000..b6465ca3 --- /dev/null +++ b/targets/device/avr/at90pwm1.s @@ -0,0 +1,88 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90PWM1.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_PSC2_CAPT + rjmp __vector_PSC2_EC + rjmp __vector_PSC1_CAPT + rjmp __vector_PSC1_EC + rjmp __vector_PSC0_CAPT + rjmp __vector_PSC0_EC + rjmp __vector_ANALOG_COMP_0 + rjmp __vector_ANALOG_COMP_1 + rjmp __vector_ANALOG_COMP_2 + rjmp __vector_INT0 + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_RESERVED15 + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMP_A + rjmp __vector_TIMER0_OVF + rjmp __vector_ADC + rjmp __vector_INT1 + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_INT2 + rjmp __vector_WDT + rjmp __vector_EE_READY + rjmp __vector_TIMER0_COMPB + rjmp __vector_INT3 + rjmp __vector_RESERVED30 + rjmp __vector_RESERVED31 + rjmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_PSC2_CAPT + IRQ __vector_PSC2_EC + IRQ __vector_PSC1_CAPT + IRQ __vector_PSC1_EC + IRQ __vector_PSC0_CAPT + IRQ __vector_PSC0_EC + IRQ __vector_ANALOG_COMP_0 + IRQ __vector_ANALOG_COMP_1 + IRQ __vector_ANALOG_COMP_2 + IRQ __vector_INT0 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_RESERVED15 + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP_A + IRQ __vector_TIMER0_OVF + IRQ __vector_ADC + IRQ __vector_INT1 + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_TIMER0_COMPB + IRQ __vector_INT3 + IRQ __vector_RESERVED30 + IRQ __vector_RESERVED31 + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90pwm161.ld b/targets/device/avr/at90pwm161.ld new file mode 100644 index 00000000..0e5850f0 --- /dev/null +++ b/targets/device/avr/at90pwm161.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90PWM161.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 20; diff --git a/targets/device/avr/at90pwm161.s b/targets/device/avr/at90pwm161.s new file mode 100644 index 00000000..9a8ef757 --- /dev/null +++ b/targets/device/avr/at90pwm161.s @@ -0,0 +1,64 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90PWM161.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_PSC2_CAPT + jmp __vector_PSC2_EC + jmp __vector_PSC2_EEC + jmp __vector_PSC0_CAPT + jmp __vector_PSC0_EC + jmp __vector_PSC0_EEC + jmp __vector_ANALOG_COMP_1 + jmp __vector_ANALOG_COMP_2 + jmp __vector_ANALOG_COMP_3 + jmp __vector_INT0 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_OVF + jmp __vector_ADC + jmp __vector_INT1 + jmp __vector_SPI_STC + jmp __vector_INT2 + jmp __vector_WDT + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_PSC2_CAPT + IRQ __vector_PSC2_EC + IRQ __vector_PSC2_EEC + IRQ __vector_PSC0_CAPT + IRQ __vector_PSC0_EC + IRQ __vector_PSC0_EEC + IRQ __vector_ANALOG_COMP_1 + IRQ __vector_ANALOG_COMP_2 + IRQ __vector_ANALOG_COMP_3 + IRQ __vector_INT0 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_OVF + IRQ __vector_ADC + IRQ __vector_INT1 + IRQ __vector_SPI_STC + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90pwm216.ld b/targets/device/avr/at90pwm216.ld new file mode 100644 index 00000000..cd9e96c4 --- /dev/null +++ b/targets/device/avr/at90pwm216.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90PWM216.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 32; diff --git a/targets/device/avr/at90pwm216.s b/targets/device/avr/at90pwm216.s new file mode 100644 index 00000000..3c0b6a50 --- /dev/null +++ b/targets/device/avr/at90pwm216.s @@ -0,0 +1,88 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90PWM216.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_PSC2_CAPT + jmp __vector_PSC2_EC + jmp __vector_PSC1_CAPT + jmp __vector_PSC1_EC + jmp __vector_PSC0_CAPT + jmp __vector_PSC0_EC + jmp __vector_ANALOG_COMP_0 + jmp __vector_ANALOG_COMP_1 + jmp __vector_ANALOG_COMP_2 + jmp __vector_INT0 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_RESERVED15 + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP_A + jmp __vector_TIMER0_OVF + jmp __vector_ADC + jmp __vector_INT1 + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_INT2 + jmp __vector_WDT + jmp __vector_EE_READY + jmp __vector_TIMER0_COMPB + jmp __vector_INT3 + jmp __vector_RESERVED30 + jmp __vector_RESERVED31 + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_PSC2_CAPT + IRQ __vector_PSC2_EC + IRQ __vector_PSC1_CAPT + IRQ __vector_PSC1_EC + IRQ __vector_PSC0_CAPT + IRQ __vector_PSC0_EC + IRQ __vector_ANALOG_COMP_0 + IRQ __vector_ANALOG_COMP_1 + IRQ __vector_ANALOG_COMP_2 + IRQ __vector_INT0 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_RESERVED15 + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP_A + IRQ __vector_TIMER0_OVF + IRQ __vector_ADC + IRQ __vector_INT1 + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_TIMER0_COMPB + IRQ __vector_INT3 + IRQ __vector_RESERVED30 + IRQ __vector_RESERVED31 + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90pwm2b.ld b/targets/device/avr/at90pwm2b.ld new file mode 100644 index 00000000..25ab4c9a --- /dev/null +++ b/targets/device/avr/at90pwm2b.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90PWM2B.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 32; diff --git a/targets/device/avr/at90pwm2b.s b/targets/device/avr/at90pwm2b.s new file mode 100644 index 00000000..81913ecc --- /dev/null +++ b/targets/device/avr/at90pwm2b.s @@ -0,0 +1,88 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90PWM2B.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_PSC2_CAPT + rjmp __vector_PSC2_EC + rjmp __vector_PSC1_CAPT + rjmp __vector_PSC1_EC + rjmp __vector_PSC0_CAPT + rjmp __vector_PSC0_EC + rjmp __vector_ANALOG_COMP_0 + rjmp __vector_ANALOG_COMP_1 + rjmp __vector_ANALOG_COMP_2 + rjmp __vector_INT0 + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_RESERVED15 + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_OVF + rjmp __vector_ADC + rjmp __vector_INT1 + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_INT2 + rjmp __vector_WDT + rjmp __vector_EE_READY + rjmp __vector_TIMER0_COMPB + rjmp __vector_INT3 + rjmp __vector_RESERVED30 + rjmp __vector_RESERVED31 + rjmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_PSC2_CAPT + IRQ __vector_PSC2_EC + IRQ __vector_PSC1_CAPT + IRQ __vector_PSC1_EC + IRQ __vector_PSC0_CAPT + IRQ __vector_PSC0_EC + IRQ __vector_ANALOG_COMP_0 + IRQ __vector_ANALOG_COMP_1 + IRQ __vector_ANALOG_COMP_2 + IRQ __vector_INT0 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_RESERVED15 + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_OVF + IRQ __vector_ADC + IRQ __vector_INT1 + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_TIMER0_COMPB + IRQ __vector_INT3 + IRQ __vector_RESERVED30 + IRQ __vector_RESERVED31 + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90pwm316.ld b/targets/device/avr/at90pwm316.ld new file mode 100644 index 00000000..05043dee --- /dev/null +++ b/targets/device/avr/at90pwm316.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90PWM316.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 32; diff --git a/targets/device/avr/at90pwm316.s b/targets/device/avr/at90pwm316.s new file mode 100644 index 00000000..aba1a20c --- /dev/null +++ b/targets/device/avr/at90pwm316.s @@ -0,0 +1,88 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90PWM316.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_PSC2_CAPT + jmp __vector_PSC2_EC + jmp __vector_PSC1_CAPT + jmp __vector_PSC1_EC + jmp __vector_PSC0_CAPT + jmp __vector_PSC0_EC + jmp __vector_ANALOG_COMP_0 + jmp __vector_ANALOG_COMP_1 + jmp __vector_ANALOG_COMP_2 + jmp __vector_INT0 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_RESERVED15 + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP_A + jmp __vector_TIMER0_OVF + jmp __vector_ADC + jmp __vector_INT1 + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_INT2 + jmp __vector_WDT + jmp __vector_EE_READY + jmp __vector_TIMER0_COMPB + jmp __vector_INT3 + jmp __vector_RESERVED30 + jmp __vector_RESERVED31 + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_PSC2_CAPT + IRQ __vector_PSC2_EC + IRQ __vector_PSC1_CAPT + IRQ __vector_PSC1_EC + IRQ __vector_PSC0_CAPT + IRQ __vector_PSC0_EC + IRQ __vector_ANALOG_COMP_0 + IRQ __vector_ANALOG_COMP_1 + IRQ __vector_ANALOG_COMP_2 + IRQ __vector_INT0 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_RESERVED15 + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP_A + IRQ __vector_TIMER0_OVF + IRQ __vector_ADC + IRQ __vector_INT1 + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_TIMER0_COMPB + IRQ __vector_INT3 + IRQ __vector_RESERVED30 + IRQ __vector_RESERVED31 + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90pwm3b.ld b/targets/device/avr/at90pwm3b.ld new file mode 100644 index 00000000..bc25ceba --- /dev/null +++ b/targets/device/avr/at90pwm3b.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90PWM3B.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 32; diff --git a/targets/device/avr/at90pwm3b.s b/targets/device/avr/at90pwm3b.s new file mode 100644 index 00000000..8316688c --- /dev/null +++ b/targets/device/avr/at90pwm3b.s @@ -0,0 +1,88 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90PWM3B.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_PSC2_CAPT + rjmp __vector_PSC2_EC + rjmp __vector_PSC1_CAPT + rjmp __vector_PSC1_EC + rjmp __vector_PSC0_CAPT + rjmp __vector_PSC0_EC + rjmp __vector_ANALOG_COMP_0 + rjmp __vector_ANALOG_COMP_1 + rjmp __vector_ANALOG_COMP_2 + rjmp __vector_INT0 + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_RESERVED15 + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_OVF + rjmp __vector_ADC + rjmp __vector_INT1 + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_INT2 + rjmp __vector_WDT + rjmp __vector_EE_READY + rjmp __vector_TIMER0_COMPB + rjmp __vector_INT3 + rjmp __vector_RESERVED30 + rjmp __vector_RESERVED31 + rjmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_PSC2_CAPT + IRQ __vector_PSC2_EC + IRQ __vector_PSC1_CAPT + IRQ __vector_PSC1_EC + IRQ __vector_PSC0_CAPT + IRQ __vector_PSC0_EC + IRQ __vector_ANALOG_COMP_0 + IRQ __vector_ANALOG_COMP_1 + IRQ __vector_ANALOG_COMP_2 + IRQ __vector_INT0 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_RESERVED15 + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_OVF + IRQ __vector_ADC + IRQ __vector_INT1 + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_TIMER0_COMPB + IRQ __vector_INT3 + IRQ __vector_RESERVED30 + IRQ __vector_RESERVED31 + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90pwm81.ld b/targets/device/avr/at90pwm81.ld new file mode 100644 index 00000000..cc7f17ed --- /dev/null +++ b/targets/device/avr/at90pwm81.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90PWM81.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x100; +__num_isrs = 20; diff --git a/targets/device/avr/at90pwm81.s b/targets/device/avr/at90pwm81.s new file mode 100644 index 00000000..bb661e42 --- /dev/null +++ b/targets/device/avr/at90pwm81.s @@ -0,0 +1,64 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90PWM81.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_PSC2_CAPT + rjmp __vector_PSC2_EC + rjmp __vector_PSC2_EEC + rjmp __vector_PSC0_CAPT + rjmp __vector_PSC0_EC + rjmp __vector_PSC0_EEC + rjmp __vector_ANALOG_COMP_1 + rjmp __vector_ANALOG_COMP_2 + rjmp __vector_ANALOG_COMP_3 + rjmp __vector_INT0 + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_OVF + rjmp __vector_ADC + rjmp __vector_INT1 + rjmp __vector_SPI_STC + rjmp __vector_INT2 + rjmp __vector_WDT + rjmp __vector_EE_READY + rjmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_PSC2_CAPT + IRQ __vector_PSC2_EC + IRQ __vector_PSC2_EEC + IRQ __vector_PSC0_CAPT + IRQ __vector_PSC0_EC + IRQ __vector_PSC0_EEC + IRQ __vector_ANALOG_COMP_1 + IRQ __vector_ANALOG_COMP_2 + IRQ __vector_ANALOG_COMP_3 + IRQ __vector_INT0 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_OVF + IRQ __vector_ADC + IRQ __vector_INT1 + IRQ __vector_SPI_STC + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90usb1286.ld b/targets/device/avr/at90usb1286.ld new file mode 100644 index 00000000..73a6860e --- /dev/null +++ b/targets/device/avr/at90usb1286.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90USB1286.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x100; +__ram_size = 0x2000; +__num_isrs = 38; diff --git a/targets/device/avr/at90usb1286.s b/targets/device/avr/at90usb1286.s new file mode 100644 index 00000000..b45d629d --- /dev/null +++ b/targets/device/avr/at90usb1286.s @@ -0,0 +1,100 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90USB1286.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90usb1287.ld b/targets/device/avr/at90usb1287.ld new file mode 100644 index 00000000..3a5a30fd --- /dev/null +++ b/targets/device/avr/at90usb1287.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90USB1287.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x100; +__ram_size = 0x2000; +__num_isrs = 38; diff --git a/targets/device/avr/at90usb1287.s b/targets/device/avr/at90usb1287.s new file mode 100644 index 00000000..84421b8e --- /dev/null +++ b/targets/device/avr/at90usb1287.s @@ -0,0 +1,100 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90USB1287.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90usb162.ld b/targets/device/avr/at90usb162.ld new file mode 100644 index 00000000..d38ba1ec --- /dev/null +++ b/targets/device/avr/at90usb162.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90USB162.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/targets/device/avr/at90usb162.s b/targets/device/avr/at90usb162.s new file mode 100644 index 00000000..d97976b0 --- /dev/null +++ b/targets/device/avr/at90usb162.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90USB162.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90usb646.ld b/targets/device/avr/at90usb646.ld new file mode 100644 index 00000000..62a2bbb9 --- /dev/null +++ b/targets/device/avr/at90usb646.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90USB646.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 38; diff --git a/targets/device/avr/at90usb646.s b/targets/device/avr/at90usb646.s new file mode 100644 index 00000000..6a88ec20 --- /dev/null +++ b/targets/device/avr/at90usb646.s @@ -0,0 +1,100 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90USB646.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90usb647.ld b/targets/device/avr/at90usb647.ld new file mode 100644 index 00000000..3b61b230 --- /dev/null +++ b/targets/device/avr/at90usb647.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90USB647.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 38; diff --git a/targets/device/avr/at90usb647.s b/targets/device/avr/at90usb647.s new file mode 100644 index 00000000..849299a1 --- /dev/null +++ b/targets/device/avr/at90usb647.s @@ -0,0 +1,100 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90USB647.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/at90usb82.ld b/targets/device/avr/at90usb82.ld new file mode 100644 index 00000000..7ceb5d33 --- /dev/null +++ b/targets/device/avr/at90usb82.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from AT90USB82.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/targets/device/avr/at90usb82.s b/targets/device/avr/at90usb82.s new file mode 100644 index 00000000..43830856 --- /dev/null +++ b/targets/device/avr/at90usb82.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from AT90USB82.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_INT2 + rjmp __vector_INT3 + rjmp __vector_INT4 + rjmp __vector_INT5 + rjmp __vector_INT6 + rjmp __vector_INT7 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_USB_GEN + rjmp __vector_USB_COM + rjmp __vector_WDT + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_COMPC + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART1_RX + rjmp __vector_USART1_UDRE + rjmp __vector_USART1_TX + rjmp __vector_ANALOG_COMP + rjmp __vector_EE_READY + rjmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega128.ld b/targets/device/avr/atmega128.ld new file mode 100644 index 00000000..e9321079 --- /dev/null +++ b/targets/device/avr/atmega128.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega128.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 35; diff --git a/targets/device/avr/atmega128.s b/targets/device/avr/atmega128.s new file mode 100644 index 00000000..2b106918 --- /dev/null +++ b/targets/device/avr/atmega128.s @@ -0,0 +1,94 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega128.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega1280.ld b/targets/device/avr/atmega1280.ld new file mode 100644 index 00000000..afaab3c8 --- /dev/null +++ b/targets/device/avr/atmega1280.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega1280.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x200; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/targets/device/avr/atmega1280.s b/targets/device/avr/atmega1280.s new file mode 100644 index 00000000..e0fa7c5f --- /dev/null +++ b/targets/device/avr/atmega1280.s @@ -0,0 +1,138 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega1280.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_USART2_RX + jmp __vector_USART2_UDRE + jmp __vector_USART2_TX + jmp __vector_USART3_RX + jmp __vector_USART3_UDRE + jmp __vector_USART3_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_USART2_RX + IRQ __vector_USART2_UDRE + IRQ __vector_USART2_TX + IRQ __vector_USART3_RX + IRQ __vector_USART3_UDRE + IRQ __vector_USART3_TX diff --git a/targets/device/avr/atmega1281.ld b/targets/device/avr/atmega1281.ld new file mode 100644 index 00000000..5bc8ca3d --- /dev/null +++ b/targets/device/avr/atmega1281.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega1281.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x200; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/targets/device/avr/atmega1281.s b/targets/device/avr/atmega1281.s new file mode 100644 index 00000000..03ba121e --- /dev/null +++ b/targets/device/avr/atmega1281.s @@ -0,0 +1,138 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega1281.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_USART2_RX + jmp __vector_USART2_UDRE + jmp __vector_USART2_TX + jmp __vector_USART3_RX + jmp __vector_USART3_UDRE + jmp __vector_USART3_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_USART2_RX + IRQ __vector_USART2_UDRE + IRQ __vector_USART2_TX + IRQ __vector_USART3_RX + IRQ __vector_USART3_UDRE + IRQ __vector_USART3_TX diff --git a/targets/device/avr/atmega1284.ld b/targets/device/avr/atmega1284.ld new file mode 100644 index 00000000..b1bdee59 --- /dev/null +++ b/targets/device/avr/atmega1284.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega1284.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x100; +__ram_size = 0x4000; +__num_isrs = 35; diff --git a/targets/device/avr/atmega1284.s b/targets/device/avr/atmega1284.s new file mode 100644 index 00000000..2f6d7466 --- /dev/null +++ b/targets/device/avr/atmega1284.s @@ -0,0 +1,94 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega1284.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_OVF diff --git a/targets/device/avr/atmega1284p.ld b/targets/device/avr/atmega1284p.ld new file mode 100644 index 00000000..8fae3fe1 --- /dev/null +++ b/targets/device/avr/atmega1284p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega1284P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x100; +__ram_size = 0x4000; +__num_isrs = 35; diff --git a/targets/device/avr/atmega1284p.s b/targets/device/avr/atmega1284p.s new file mode 100644 index 00000000..435a153e --- /dev/null +++ b/targets/device/avr/atmega1284p.s @@ -0,0 +1,94 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega1284P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_OVF diff --git a/targets/device/avr/atmega1284rfr2.ld b/targets/device/avr/atmega1284rfr2.ld new file mode 100644 index 00000000..6570c062 --- /dev/null +++ b/targets/device/avr/atmega1284rfr2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega1284RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x200; +__ram_size = 0x4000; +__num_isrs = 71; diff --git a/targets/device/avr/atmega1284rfr2.s b/targets/device/avr/atmega1284rfr2.s new file mode 100644 index 00000000..fbadaa2a --- /dev/null +++ b/targets/device/avr/atmega1284rfr2.s @@ -0,0 +1,172 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega1284RFR2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_TRX24_PLL_LOCK + jmp __vector_TRX24_PLL_UNLOCK + jmp __vector_TRX24_RX_START + jmp __vector_TRX24_RX_END + jmp __vector_TRX24_CCA_ED_DONE + jmp __vector_TRX24_XAH_AMI + jmp __vector_TRX24_TX_END + jmp __vector_TRX24_AWAKE + jmp __vector_SCNT_CMP1 + jmp __vector_SCNT_CMP2 + jmp __vector_SCNT_CMP3 + jmp __vector_SCNT_OVFL + jmp __vector_SCNT_BACKOFF + jmp __vector_AES_READY + jmp __vector_BAT_LOW + jmp __vector_TRX24_TX_START + jmp __vector_TRX24_AMI0 + jmp __vector_TRX24_AMI1 + jmp __vector_TRX24_AMI2 + jmp __vector_TRX24_AMI3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_TRX24_PLL_LOCK + IRQ __vector_TRX24_PLL_UNLOCK + IRQ __vector_TRX24_RX_START + IRQ __vector_TRX24_RX_END + IRQ __vector_TRX24_CCA_ED_DONE + IRQ __vector_TRX24_XAH_AMI + IRQ __vector_TRX24_TX_END + IRQ __vector_TRX24_AWAKE + IRQ __vector_SCNT_CMP1 + IRQ __vector_SCNT_CMP2 + IRQ __vector_SCNT_CMP3 + IRQ __vector_SCNT_OVFL + IRQ __vector_SCNT_BACKOFF + IRQ __vector_AES_READY + IRQ __vector_BAT_LOW + IRQ __vector_TRX24_TX_START + IRQ __vector_TRX24_AMI0 + IRQ __vector_TRX24_AMI1 + IRQ __vector_TRX24_AMI2 + IRQ __vector_TRX24_AMI3 diff --git a/targets/device/avr/atmega128a.ld b/targets/device/avr/atmega128a.ld new file mode 100644 index 00000000..019cdd82 --- /dev/null +++ b/targets/device/avr/atmega128a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega128A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 35; diff --git a/targets/device/avr/atmega128a.s b/targets/device/avr/atmega128a.s new file mode 100644 index 00000000..41aea722 --- /dev/null +++ b/targets/device/avr/atmega128a.s @@ -0,0 +1,94 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega128A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega128rfa1.ld b/targets/device/avr/atmega128rfa1.ld new file mode 100644 index 00000000..1cca0954 --- /dev/null +++ b/targets/device/avr/atmega128rfa1.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega128RFA1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x200; +__ram_size = 0x4000; +__num_isrs = 72; diff --git a/targets/device/avr/atmega128rfa1.s b/targets/device/avr/atmega128rfa1.s new file mode 100644 index 00000000..26f5762c --- /dev/null +++ b/targets/device/avr/atmega128rfa1.s @@ -0,0 +1,168 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega128RFA1.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_USART2_RX + jmp __vector_USART2_UDRE + jmp __vector_USART2_TX + jmp __vector_USART3_RX + jmp __vector_USART3_UDRE + jmp __vector_USART3_TX + jmp __vector_TRX24_PLL_LOCK + jmp __vector_TRX24_PLL_UNLOCK + jmp __vector_TRX24_RX_START + jmp __vector_TRX24_RX_END + jmp __vector_TRX24_CCA_ED_DONE + jmp __vector_TRX24_XAH_AMI + jmp __vector_TRX24_TX_END + jmp __vector_TRX24_AWAKE + jmp __vector_SCNT_CMP1 + jmp __vector_SCNT_CMP2 + jmp __vector_SCNT_CMP3 + jmp __vector_SCNT_OVFL + jmp __vector_SCNT_BACKOFF + jmp __vector_AES_READY + jmp __vector_BAT_LOW + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_USART2_RX + IRQ __vector_USART2_UDRE + IRQ __vector_USART2_TX + IRQ __vector_USART3_RX + IRQ __vector_USART3_UDRE + IRQ __vector_USART3_TX + IRQ __vector_TRX24_PLL_LOCK + IRQ __vector_TRX24_PLL_UNLOCK + IRQ __vector_TRX24_RX_START + IRQ __vector_TRX24_RX_END + IRQ __vector_TRX24_CCA_ED_DONE + IRQ __vector_TRX24_XAH_AMI + IRQ __vector_TRX24_TX_END + IRQ __vector_TRX24_AWAKE + IRQ __vector_SCNT_CMP1 + IRQ __vector_SCNT_CMP2 + IRQ __vector_SCNT_CMP3 + IRQ __vector_SCNT_OVFL + IRQ __vector_SCNT_BACKOFF + IRQ __vector_AES_READY + IRQ __vector_BAT_LOW diff --git a/targets/device/avr/atmega128rfr2.ld b/targets/device/avr/atmega128rfr2.ld new file mode 100644 index 00000000..5812f3e6 --- /dev/null +++ b/targets/device/avr/atmega128rfr2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega128RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_start = 0x200; +__ram_size = 0x4000; +__num_isrs = 71; diff --git a/targets/device/avr/atmega128rfr2.s b/targets/device/avr/atmega128rfr2.s new file mode 100644 index 00000000..f67bcd2c --- /dev/null +++ b/targets/device/avr/atmega128rfr2.s @@ -0,0 +1,172 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega128RFR2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_TRX24_PLL_LOCK + jmp __vector_TRX24_PLL_UNLOCK + jmp __vector_TRX24_RX_START + jmp __vector_TRX24_RX_END + jmp __vector_TRX24_CCA_ED_DONE + jmp __vector_TRX24_XAH_AMI + jmp __vector_TRX24_TX_END + jmp __vector_TRX24_AWAKE + jmp __vector_SCNT_CMP1 + jmp __vector_SCNT_CMP2 + jmp __vector_SCNT_CMP3 + jmp __vector_SCNT_OVFL + jmp __vector_SCNT_BACKOFF + jmp __vector_AES_READY + jmp __vector_BAT_LOW + jmp __vector_TRX24_TX_START + jmp __vector_TRX24_AMI0 + jmp __vector_TRX24_AMI1 + jmp __vector_TRX24_AMI2 + jmp __vector_TRX24_AMI3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_TRX24_PLL_LOCK + IRQ __vector_TRX24_PLL_UNLOCK + IRQ __vector_TRX24_RX_START + IRQ __vector_TRX24_RX_END + IRQ __vector_TRX24_CCA_ED_DONE + IRQ __vector_TRX24_XAH_AMI + IRQ __vector_TRX24_TX_END + IRQ __vector_TRX24_AWAKE + IRQ __vector_SCNT_CMP1 + IRQ __vector_SCNT_CMP2 + IRQ __vector_SCNT_CMP3 + IRQ __vector_SCNT_OVFL + IRQ __vector_SCNT_BACKOFF + IRQ __vector_AES_READY + IRQ __vector_BAT_LOW + IRQ __vector_TRX24_TX_START + IRQ __vector_TRX24_AMI0 + IRQ __vector_TRX24_AMI1 + IRQ __vector_TRX24_AMI2 + IRQ __vector_TRX24_AMI3 diff --git a/targets/device/avr/atmega16.ld b/targets/device/avr/atmega16.ld new file mode 100644 index 00000000..4f8bf356 --- /dev/null +++ b/targets/device/avr/atmega16.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega16.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x60; +__ram_size = 0x400; +__num_isrs = 21; diff --git a/targets/device/avr/atmega16.s b/targets/device/avr/atmega16.s new file mode 100644 index 00000000..eff12c2e --- /dev/null +++ b/targets/device/avr/atmega16.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega16.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RXC + jmp __vector_USART_UDRE + jmp __vector_USART_TXC + jmp __vector_ADC + jmp __vector_EE_RDY + jmp __vector_ANA_COMP + jmp __vector_TWI + jmp __vector_INT2 + jmp __vector_TIMER0_COMP + jmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RXC + IRQ __vector_USART_UDRE + IRQ __vector_USART_TXC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TWI + IRQ __vector_INT2 + IRQ __vector_TIMER0_COMP + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega162.ld b/targets/device/avr/atmega162.ld new file mode 100644 index 00000000..fe3ec3c0 --- /dev/null +++ b/targets/device/avr/atmega162.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega162.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 28; diff --git a/targets/device/avr/atmega162.s b/targets/device/avr/atmega162.s new file mode 100644 index 00000000..a2c99b14 --- /dev/null +++ b/targets/device/avr/atmega162.s @@ -0,0 +1,80 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega162.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_OVF + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RXC + jmp __vector_USART1_RXC + jmp __vector_USART0_UDRE + jmp __vector_USART1_UDRE + jmp __vector_USART0_TXC + jmp __vector_USART1_TXC + jmp __vector_EE_RDY + jmp __vector_ANA_COMP + jmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_OVF + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RXC + IRQ __vector_USART1_RXC + IRQ __vector_USART0_UDRE + IRQ __vector_USART1_UDRE + IRQ __vector_USART0_TXC + IRQ __vector_USART1_TXC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega164a.ld b/targets/device/avr/atmega164a.ld new file mode 100644 index 00000000..a503d39c --- /dev/null +++ b/targets/device/avr/atmega164a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega164A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/targets/device/avr/atmega164a.s b/targets/device/avr/atmega164a.s new file mode 100644 index 00000000..db920049 --- /dev/null +++ b/targets/device/avr/atmega164a.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega164A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega164p.ld b/targets/device/avr/atmega164p.ld new file mode 100644 index 00000000..a1c74cce --- /dev/null +++ b/targets/device/avr/atmega164p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega164P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/targets/device/avr/atmega164p.s b/targets/device/avr/atmega164p.s new file mode 100644 index 00000000..938c7db2 --- /dev/null +++ b/targets/device/avr/atmega164p.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega164P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega164pa.ld b/targets/device/avr/atmega164pa.ld new file mode 100644 index 00000000..25d31a8b --- /dev/null +++ b/targets/device/avr/atmega164pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega164PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/targets/device/avr/atmega164pa.s b/targets/device/avr/atmega164pa.s new file mode 100644 index 00000000..b5812562 --- /dev/null +++ b/targets/device/avr/atmega164pa.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega164PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega165a.ld b/targets/device/avr/atmega165a.ld new file mode 100644 index 00000000..39c8d6a7 --- /dev/null +++ b/targets/device/avr/atmega165a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega165A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 22; diff --git a/targets/device/avr/atmega165a.s b/targets/device/avr/atmega165a.s new file mode 100644 index 00000000..c8919ea8 --- /dev/null +++ b/targets/device/avr/atmega165a.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega165A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega165p.ld b/targets/device/avr/atmega165p.ld new file mode 100644 index 00000000..0520535c --- /dev/null +++ b/targets/device/avr/atmega165p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega165P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 22; diff --git a/targets/device/avr/atmega165p.s b/targets/device/avr/atmega165p.s new file mode 100644 index 00000000..f16c572f --- /dev/null +++ b/targets/device/avr/atmega165p.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega165P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega165pa.ld b/targets/device/avr/atmega165pa.ld new file mode 100644 index 00000000..13fa87bb --- /dev/null +++ b/targets/device/avr/atmega165pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega165PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 22; diff --git a/targets/device/avr/atmega165pa.s b/targets/device/avr/atmega165pa.s new file mode 100644 index 00000000..8e7d0ddb --- /dev/null +++ b/targets/device/avr/atmega165pa.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega165PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega168.ld b/targets/device/avr/atmega168.ld new file mode 100644 index 00000000..c585cef1 --- /dev/null +++ b/targets/device/avr/atmega168.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega168.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/targets/device/avr/atmega168.s b/targets/device/avr/atmega168.s new file mode 100644 index 00000000..423ecc18 --- /dev/null +++ b/targets/device/avr/atmega168.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega168.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega168a.ld b/targets/device/avr/atmega168a.ld new file mode 100644 index 00000000..b3c9383b --- /dev/null +++ b/targets/device/avr/atmega168a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega168A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/targets/device/avr/atmega168a.s b/targets/device/avr/atmega168a.s new file mode 100644 index 00000000..23a43bc8 --- /dev/null +++ b/targets/device/avr/atmega168a.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega168A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TWI + jmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega168p.ld b/targets/device/avr/atmega168p.ld new file mode 100644 index 00000000..9c4501a4 --- /dev/null +++ b/targets/device/avr/atmega168p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega168P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/targets/device/avr/atmega168p.s b/targets/device/avr/atmega168p.s new file mode 100644 index 00000000..06c332c3 --- /dev/null +++ b/targets/device/avr/atmega168p.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega168P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TWI + jmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega168pa.ld b/targets/device/avr/atmega168pa.ld new file mode 100644 index 00000000..23eb5b52 --- /dev/null +++ b/targets/device/avr/atmega168pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega168PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/targets/device/avr/atmega168pa.s b/targets/device/avr/atmega168pa.s new file mode 100644 index 00000000..d59f2092 --- /dev/null +++ b/targets/device/avr/atmega168pa.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega168PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TWI + jmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega168pb.ld b/targets/device/avr/atmega168pb.ld new file mode 100644 index 00000000..a94f8fce --- /dev/null +++ b/targets/device/avr/atmega168pb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega168PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 27; diff --git a/targets/device/avr/atmega168pb.s b/targets/device/avr/atmega168pb.s new file mode 100644 index 00000000..f34b015c --- /dev/null +++ b/targets/device/avr/atmega168pb.s @@ -0,0 +1,78 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega168PB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TWI + jmp __vector_SPM_Ready + jmp __vector_USART_START + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready + IRQ __vector_USART_START diff --git a/targets/device/avr/atmega169a.ld b/targets/device/avr/atmega169a.ld new file mode 100644 index 00000000..d2ed0506 --- /dev/null +++ b/targets/device/avr/atmega169a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega169A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 23; diff --git a/targets/device/avr/atmega169a.s b/targets/device/avr/atmega169a.s new file mode 100644 index 00000000..65bdfac5 --- /dev/null +++ b/targets/device/avr/atmega169a.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega169A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega169p.ld b/targets/device/avr/atmega169p.ld new file mode 100644 index 00000000..de4b8d74 --- /dev/null +++ b/targets/device/avr/atmega169p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega169P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 23; diff --git a/targets/device/avr/atmega169p.s b/targets/device/avr/atmega169p.s new file mode 100644 index 00000000..52ca3b96 --- /dev/null +++ b/targets/device/avr/atmega169p.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega169P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega169pa.ld b/targets/device/avr/atmega169pa.ld new file mode 100644 index 00000000..01da35b8 --- /dev/null +++ b/targets/device/avr/atmega169pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega169PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 23; diff --git a/targets/device/avr/atmega169pa.s b/targets/device/avr/atmega169pa.s new file mode 100644 index 00000000..2a7dc95d --- /dev/null +++ b/targets/device/avr/atmega169pa.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega169PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega16a.ld b/targets/device/avr/atmega16a.ld new file mode 100644 index 00000000..e66cc7d7 --- /dev/null +++ b/targets/device/avr/atmega16a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega16A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x60; +__ram_size = 0x400; +__num_isrs = 21; diff --git a/targets/device/avr/atmega16a.s b/targets/device/avr/atmega16a.s new file mode 100644 index 00000000..affc7d93 --- /dev/null +++ b/targets/device/avr/atmega16a.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega16A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RXC + jmp __vector_USART_UDRE + jmp __vector_USART_TXC + jmp __vector_ADC + jmp __vector_EE_RDY + jmp __vector_ANA_COMP + jmp __vector_TWI + jmp __vector_INT2 + jmp __vector_TIMER0_COMP + jmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RXC + IRQ __vector_USART_UDRE + IRQ __vector_USART_TXC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TWI + IRQ __vector_INT2 + IRQ __vector_TIMER0_COMP + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega16hva.ld b/targets/device/avr/atmega16hva.ld new file mode 100644 index 00000000..fee9e990 --- /dev/null +++ b/targets/device/avr/atmega16hva.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega16HVA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 21; diff --git a/targets/device/avr/atmega16hva.s b/targets/device/avr/atmega16hva.s new file mode 100644 index 00000000..49154398 --- /dev/null +++ b/targets/device/avr/atmega16hva.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega16HVA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_BPINT + jmp __vector_VREGMON + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_WDT + jmp __vector_TIMER1_IC + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_IC + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_VADC + jmp __vector_CCADC_CONV + jmp __vector_CCADC_REG_CUR + jmp __vector_CCADC_ACC + jmp __vector_EE_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_BPINT + IRQ __vector_VREGMON + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_TIMER1_IC + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_IC + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_VADC + IRQ __vector_CCADC_CONV + IRQ __vector_CCADC_REG_CUR + IRQ __vector_CCADC_ACC + IRQ __vector_EE_READY diff --git a/targets/device/avr/atmega16hvb.ld b/targets/device/avr/atmega16hvb.ld new file mode 100644 index 00000000..9239f478 --- /dev/null +++ b/targets/device/avr/atmega16hvb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega16HVB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 29; diff --git a/targets/device/avr/atmega16hvb.s b/targets/device/avr/atmega16hvb.s new file mode 100644 index 00000000..da713196 --- /dev/null +++ b/targets/device/avr/atmega16hvb.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega16HVB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_BPINT + jmp __vector_VREGMON + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_WDT + jmp __vector_BGSCD + jmp __vector_CHDET + jmp __vector_TIMER1_IC + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_IC + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_TWIBUSCD + jmp __vector_TWI + jmp __vector_SPI_STC + jmp __vector_VADC + jmp __vector_CCADC_CONV + jmp __vector_CCADC_REG_CUR + jmp __vector_CCADC_ACC + jmp __vector_EE_READY + jmp __vector_SPM + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_BPINT + IRQ __vector_VREGMON + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_BGSCD + IRQ __vector_CHDET + IRQ __vector_TIMER1_IC + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_IC + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_TWIBUSCD + IRQ __vector_TWI + IRQ __vector_SPI_STC + IRQ __vector_VADC + IRQ __vector_CCADC_CONV + IRQ __vector_CCADC_REG_CUR + IRQ __vector_CCADC_ACC + IRQ __vector_EE_READY + IRQ __vector_SPM diff --git a/targets/device/avr/atmega16hvbrevb.ld b/targets/device/avr/atmega16hvbrevb.ld new file mode 100644 index 00000000..963f2a10 --- /dev/null +++ b/targets/device/avr/atmega16hvbrevb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega16HVBrevB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 29; diff --git a/targets/device/avr/atmega16hvbrevb.s b/targets/device/avr/atmega16hvbrevb.s new file mode 100644 index 00000000..f4c72267 --- /dev/null +++ b/targets/device/avr/atmega16hvbrevb.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega16HVBrevB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_BPINT + jmp __vector_VREGMON + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_WDT + jmp __vector_BGSCD + jmp __vector_CHDET + jmp __vector_TIMER1_IC + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_IC + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_TWIBUSCD + jmp __vector_TWI + jmp __vector_SPI_STC + jmp __vector_VADC + jmp __vector_CCADC_CONV + jmp __vector_CCADC_REG_CUR + jmp __vector_CCADC_ACC + jmp __vector_EE_READY + jmp __vector_SPM + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_BPINT + IRQ __vector_VREGMON + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_BGSCD + IRQ __vector_CHDET + IRQ __vector_TIMER1_IC + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_IC + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_TWIBUSCD + IRQ __vector_TWI + IRQ __vector_SPI_STC + IRQ __vector_VADC + IRQ __vector_CCADC_CONV + IRQ __vector_CCADC_REG_CUR + IRQ __vector_CCADC_ACC + IRQ __vector_EE_READY + IRQ __vector_SPM diff --git a/targets/device/avr/atmega16m1.ld b/targets/device/avr/atmega16m1.ld new file mode 100644 index 00000000..057ba4d7 --- /dev/null +++ b/targets/device/avr/atmega16m1.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega16M1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/targets/device/avr/atmega16m1.s b/targets/device/avr/atmega16m1.s new file mode 100644 index 00000000..3d71a442 --- /dev/null +++ b/targets/device/avr/atmega16m1.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega16M1.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_ANACOMP0 + jmp __vector_ANACOMP1 + jmp __vector_ANACOMP2 + jmp __vector_ANACOMP3 + jmp __vector_PSC_FAULT + jmp __vector_PSC_EC + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_CAN_INT + jmp __vector_CAN_TOVF + jmp __vector_LIN_TC + jmp __vector_LIN_ERR + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_SPI_STC + jmp __vector_ADC + jmp __vector_WDT + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_ANACOMP0 + IRQ __vector_ANACOMP1 + IRQ __vector_ANACOMP2 + IRQ __vector_ANACOMP3 + IRQ __vector_PSC_FAULT + IRQ __vector_PSC_EC + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_CAN_INT + IRQ __vector_CAN_TOVF + IRQ __vector_LIN_TC + IRQ __vector_LIN_ERR + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega16u2.ld b/targets/device/avr/atmega16u2.ld new file mode 100644 index 00000000..89db6f84 --- /dev/null +++ b/targets/device/avr/atmega16u2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega16U2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/targets/device/avr/atmega16u2.s b/targets/device/avr/atmega16u2.s new file mode 100644 index 00000000..5a3870c9 --- /dev/null +++ b/targets/device/avr/atmega16u2.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega16U2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega16u4.ld b/targets/device/avr/atmega16u4.ld new file mode 100644 index 00000000..fcf340ee --- /dev/null +++ b/targets/device/avr/atmega16u4.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega16U4.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x500; +__num_isrs = 43; diff --git a/targets/device/avr/atmega16u4.s b/targets/device/avr/atmega16u4.s new file mode 100644 index 00000000..97ef1951 --- /dev/null +++ b/targets/device/avr/atmega16u4.s @@ -0,0 +1,110 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega16U4.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_Reserved1 + jmp __vector_Reserved2 + jmp __vector_INT6 + jmp __vector_Reserved3 + jmp __vector_PCINT0 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_Reserved4 + jmp __vector_Reserved5 + jmp __vector_Reserved6 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPD + jmp __vector_TIMER4_OVF + jmp __vector_TIMER4_FPF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_Reserved1 + IRQ __vector_Reserved2 + IRQ __vector_INT6 + IRQ __vector_Reserved3 + IRQ __vector_PCINT0 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_Reserved4 + IRQ __vector_Reserved5 + IRQ __vector_Reserved6 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPD + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER4_FPF diff --git a/targets/device/avr/atmega2560.ld b/targets/device/avr/atmega2560.ld new file mode 100644 index 00000000..3c596ac9 --- /dev/null +++ b/targets/device/avr/atmega2560.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega2560.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x40000; +__ram_start = 0x200; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/targets/device/avr/atmega2560.s b/targets/device/avr/atmega2560.s new file mode 100644 index 00000000..ff7e4357 --- /dev/null +++ b/targets/device/avr/atmega2560.s @@ -0,0 +1,138 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega2560.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_USART2_RX + jmp __vector_USART2_UDRE + jmp __vector_USART2_TX + jmp __vector_USART3_RX + jmp __vector_USART3_UDRE + jmp __vector_USART3_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_USART2_RX + IRQ __vector_USART2_UDRE + IRQ __vector_USART2_TX + IRQ __vector_USART3_RX + IRQ __vector_USART3_UDRE + IRQ __vector_USART3_TX diff --git a/targets/device/avr/atmega2561.ld b/targets/device/avr/atmega2561.ld new file mode 100644 index 00000000..e8c87dc5 --- /dev/null +++ b/targets/device/avr/atmega2561.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega2561.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x40000; +__ram_start = 0x200; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/targets/device/avr/atmega2561.s b/targets/device/avr/atmega2561.s new file mode 100644 index 00000000..1c576492 --- /dev/null +++ b/targets/device/avr/atmega2561.s @@ -0,0 +1,138 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega2561.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_USART2_RX + jmp __vector_USART2_UDRE + jmp __vector_USART2_TX + jmp __vector_USART3_RX + jmp __vector_USART3_UDRE + jmp __vector_USART3_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_USART2_RX + IRQ __vector_USART2_UDRE + IRQ __vector_USART2_TX + IRQ __vector_USART3_RX + IRQ __vector_USART3_UDRE + IRQ __vector_USART3_TX diff --git a/targets/device/avr/atmega2564rfr2.ld b/targets/device/avr/atmega2564rfr2.ld new file mode 100644 index 00000000..b12672ef --- /dev/null +++ b/targets/device/avr/atmega2564rfr2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega2564RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x40000; +__ram_start = 0x200; +__ram_size = 0x8000; +__num_isrs = 71; diff --git a/targets/device/avr/atmega2564rfr2.s b/targets/device/avr/atmega2564rfr2.s new file mode 100644 index 00000000..166fbc45 --- /dev/null +++ b/targets/device/avr/atmega2564rfr2.s @@ -0,0 +1,172 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega2564RFR2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_TRX24_PLL_LOCK + jmp __vector_TRX24_PLL_UNLOCK + jmp __vector_TRX24_RX_START + jmp __vector_TRX24_RX_END + jmp __vector_TRX24_CCA_ED_DONE + jmp __vector_TRX24_XAH_AMI + jmp __vector_TRX24_TX_END + jmp __vector_TRX24_AWAKE + jmp __vector_SCNT_CMP1 + jmp __vector_SCNT_CMP2 + jmp __vector_SCNT_CMP3 + jmp __vector_SCNT_OVFL + jmp __vector_SCNT_BACKOFF + jmp __vector_AES_READY + jmp __vector_BAT_LOW + jmp __vector_TRX24_TX_START + jmp __vector_TRX24_AMI0 + jmp __vector_TRX24_AMI1 + jmp __vector_TRX24_AMI2 + jmp __vector_TRX24_AMI3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_TRX24_PLL_LOCK + IRQ __vector_TRX24_PLL_UNLOCK + IRQ __vector_TRX24_RX_START + IRQ __vector_TRX24_RX_END + IRQ __vector_TRX24_CCA_ED_DONE + IRQ __vector_TRX24_XAH_AMI + IRQ __vector_TRX24_TX_END + IRQ __vector_TRX24_AWAKE + IRQ __vector_SCNT_CMP1 + IRQ __vector_SCNT_CMP2 + IRQ __vector_SCNT_CMP3 + IRQ __vector_SCNT_OVFL + IRQ __vector_SCNT_BACKOFF + IRQ __vector_AES_READY + IRQ __vector_BAT_LOW + IRQ __vector_TRX24_TX_START + IRQ __vector_TRX24_AMI0 + IRQ __vector_TRX24_AMI1 + IRQ __vector_TRX24_AMI2 + IRQ __vector_TRX24_AMI3 diff --git a/targets/device/avr/atmega256rfr2.ld b/targets/device/avr/atmega256rfr2.ld new file mode 100644 index 00000000..9e15d6ef --- /dev/null +++ b/targets/device/avr/atmega256rfr2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega256RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x40000; +__ram_start = 0x200; +__ram_size = 0x8000; +__num_isrs = 71; diff --git a/targets/device/avr/atmega256rfr2.s b/targets/device/avr/atmega256rfr2.s new file mode 100644 index 00000000..6d9a0db8 --- /dev/null +++ b/targets/device/avr/atmega256rfr2.s @@ -0,0 +1,172 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega256RFR2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_TRX24_PLL_LOCK + jmp __vector_TRX24_PLL_UNLOCK + jmp __vector_TRX24_RX_START + jmp __vector_TRX24_RX_END + jmp __vector_TRX24_CCA_ED_DONE + jmp __vector_TRX24_XAH_AMI + jmp __vector_TRX24_TX_END + jmp __vector_TRX24_AWAKE + jmp __vector_SCNT_CMP1 + jmp __vector_SCNT_CMP2 + jmp __vector_SCNT_CMP3 + jmp __vector_SCNT_OVFL + jmp __vector_SCNT_BACKOFF + jmp __vector_AES_READY + jmp __vector_BAT_LOW + jmp __vector_TRX24_TX_START + jmp __vector_TRX24_AMI0 + jmp __vector_TRX24_AMI1 + jmp __vector_TRX24_AMI2 + jmp __vector_TRX24_AMI3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_TRX24_PLL_LOCK + IRQ __vector_TRX24_PLL_UNLOCK + IRQ __vector_TRX24_RX_START + IRQ __vector_TRX24_RX_END + IRQ __vector_TRX24_CCA_ED_DONE + IRQ __vector_TRX24_XAH_AMI + IRQ __vector_TRX24_TX_END + IRQ __vector_TRX24_AWAKE + IRQ __vector_SCNT_CMP1 + IRQ __vector_SCNT_CMP2 + IRQ __vector_SCNT_CMP3 + IRQ __vector_SCNT_OVFL + IRQ __vector_SCNT_BACKOFF + IRQ __vector_AES_READY + IRQ __vector_BAT_LOW + IRQ __vector_TRX24_TX_START + IRQ __vector_TRX24_AMI0 + IRQ __vector_TRX24_AMI1 + IRQ __vector_TRX24_AMI2 + IRQ __vector_TRX24_AMI3 diff --git a/targets/device/avr/atmega32.ld b/targets/device/avr/atmega32.ld new file mode 100644 index 00000000..6c3e9050 --- /dev/null +++ b/targets/device/avr/atmega32.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega32.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x60; +__ram_size = 0x800; +__num_isrs = 21; diff --git a/targets/device/avr/atmega32.s b/targets/device/avr/atmega32.s new file mode 100644 index 00000000..c6cfe165 --- /dev/null +++ b/targets/device/avr/atmega32.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega32.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RXC + jmp __vector_USART_UDRE + jmp __vector_USART_TXC + jmp __vector_ADC + jmp __vector_EE_RDY + jmp __vector_ANA_COMP + jmp __vector_TWI + jmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RXC + IRQ __vector_USART_UDRE + IRQ __vector_USART_TXC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TWI + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega324a.ld b/targets/device/avr/atmega324a.ld new file mode 100644 index 00000000..4abf8570 --- /dev/null +++ b/targets/device/avr/atmega324a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega324A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/targets/device/avr/atmega324a.s b/targets/device/avr/atmega324a.s new file mode 100644 index 00000000..b08c7761 --- /dev/null +++ b/targets/device/avr/atmega324a.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega324A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega324p.ld b/targets/device/avr/atmega324p.ld new file mode 100644 index 00000000..400f7566 --- /dev/null +++ b/targets/device/avr/atmega324p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega324P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/targets/device/avr/atmega324p.s b/targets/device/avr/atmega324p.s new file mode 100644 index 00000000..4cc9146b --- /dev/null +++ b/targets/device/avr/atmega324p.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega324P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega324pa.ld b/targets/device/avr/atmega324pa.ld new file mode 100644 index 00000000..01f86d18 --- /dev/null +++ b/targets/device/avr/atmega324pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega324PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/targets/device/avr/atmega324pa.s b/targets/device/avr/atmega324pa.s new file mode 100644 index 00000000..81066344 --- /dev/null +++ b/targets/device/avr/atmega324pa.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega324PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega324pb.ld b/targets/device/avr/atmega324pb.ld new file mode 100644 index 00000000..515f9119 --- /dev/null +++ b/targets/device/avr/atmega324pb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega324PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 54; diff --git a/targets/device/avr/atmega324pb.s b/targets/device/avr/atmega324pb.s new file mode 100644 index 00000000..7c569cf2 --- /dev/null +++ b/targets/device/avr/atmega324pb.s @@ -0,0 +1,129 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega324PB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI0_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI0 + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_OVF + jmp __vector_USART0_RXS + jmp __vector_USART1_RXS + jmp __vector_PCINT4 + jmp __vector_XOSCFD + jmp __vector_PTC_EOC + jmp __vector_PTC_WCOMP + jmp __vector_SPI1_STC + jmp __vector_TWI1 + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_OVF + jmp __vector_USART2_RX + jmp __vector_USART2_UDRE + jmp __vector_USART2_TX + jmp __vector_USART2_RXS + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI0_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI0 + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_OVF + IRQ __vector_USART0_RXS + IRQ __vector_USART0_START + IRQ __vector_USART1_RXS + IRQ __vector_USART1_START + IRQ __vector_PCINT4 + IRQ __vector_XOSCFD + IRQ __vector_PTC_EOC + IRQ __vector_PTC_WCOMP + IRQ __vector_SPI1_STC + IRQ __vector_TWI1 + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_OVF + IRQ __vector_USART2_RX + IRQ __vector_USART2_UDRE + IRQ __vector_USART2_TX + IRQ __vector_USART2_RXS + IRQ __vector_USART2_START diff --git a/targets/device/avr/atmega325.ld b/targets/device/avr/atmega325.ld new file mode 100644 index 00000000..1a8fc62d --- /dev/null +++ b/targets/device/avr/atmega325.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega325.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 22; diff --git a/targets/device/avr/atmega325.s b/targets/device/avr/atmega325.s new file mode 100644 index 00000000..e03a0cc7 --- /dev/null +++ b/targets/device/avr/atmega325.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega325.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega3250.ld b/targets/device/avr/atmega3250.ld new file mode 100644 index 00000000..07b234a8 --- /dev/null +++ b/targets/device/avr/atmega3250.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega3250.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/targets/device/avr/atmega3250.s b/targets/device/avr/atmega3250.s new file mode 100644 index 00000000..8df525b5 --- /dev/null +++ b/targets/device/avr/atmega3250.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega3250.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_NOT_USED + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_NOT_USED + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega3250a.ld b/targets/device/avr/atmega3250a.ld new file mode 100644 index 00000000..fedc2392 --- /dev/null +++ b/targets/device/avr/atmega3250a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega3250A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/targets/device/avr/atmega3250a.s b/targets/device/avr/atmega3250a.s new file mode 100644 index 00000000..0a3b0cba --- /dev/null +++ b/targets/device/avr/atmega3250a.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega3250A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_NOT_USED + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_NOT_USED + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega3250p.ld b/targets/device/avr/atmega3250p.ld new file mode 100644 index 00000000..2c08b8df --- /dev/null +++ b/targets/device/avr/atmega3250p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega3250P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/targets/device/avr/atmega3250p.s b/targets/device/avr/atmega3250p.s new file mode 100644 index 00000000..0ca1f9b9 --- /dev/null +++ b/targets/device/avr/atmega3250p.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega3250P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_NOT_USED + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_NOT_USED + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega3250pa.ld b/targets/device/avr/atmega3250pa.ld new file mode 100644 index 00000000..93652911 --- /dev/null +++ b/targets/device/avr/atmega3250pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega3250PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/targets/device/avr/atmega3250pa.s b/targets/device/avr/atmega3250pa.s new file mode 100644 index 00000000..898cdcdc --- /dev/null +++ b/targets/device/avr/atmega3250pa.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega3250PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_NOT_USED + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_NOT_USED + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega325a.ld b/targets/device/avr/atmega325a.ld new file mode 100644 index 00000000..f82c0fc4 --- /dev/null +++ b/targets/device/avr/atmega325a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega325A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 22; diff --git a/targets/device/avr/atmega325a.s b/targets/device/avr/atmega325a.s new file mode 100644 index 00000000..6974df4c --- /dev/null +++ b/targets/device/avr/atmega325a.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega325A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega325p.ld b/targets/device/avr/atmega325p.ld new file mode 100644 index 00000000..6f63f64a --- /dev/null +++ b/targets/device/avr/atmega325p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega325P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 22; diff --git a/targets/device/avr/atmega325p.s b/targets/device/avr/atmega325p.s new file mode 100644 index 00000000..5884588f --- /dev/null +++ b/targets/device/avr/atmega325p.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega325P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega325pa.ld b/targets/device/avr/atmega325pa.ld new file mode 100644 index 00000000..bfc4ee3e --- /dev/null +++ b/targets/device/avr/atmega325pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega325PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 22; diff --git a/targets/device/avr/atmega325pa.s b/targets/device/avr/atmega325pa.s new file mode 100644 index 00000000..1b84fd7f --- /dev/null +++ b/targets/device/avr/atmega325pa.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega325PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega328.ld b/targets/device/avr/atmega328.ld new file mode 100644 index 00000000..081e47a0 --- /dev/null +++ b/targets/device/avr/atmega328.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega328.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 26; diff --git a/targets/device/avr/atmega328.s b/targets/device/avr/atmega328.s new file mode 100644 index 00000000..4478a06a --- /dev/null +++ b/targets/device/avr/atmega328.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega328.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega328p.ld b/targets/device/avr/atmega328p.ld new file mode 100644 index 00000000..220e0a91 --- /dev/null +++ b/targets/device/avr/atmega328p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega328P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 26; diff --git a/targets/device/avr/atmega328p.s b/targets/device/avr/atmega328p.s new file mode 100644 index 00000000..6faa7beb --- /dev/null +++ b/targets/device/avr/atmega328p.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega328P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TWI + jmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega328pb.ld b/targets/device/avr/atmega328pb.ld new file mode 100644 index 00000000..e185b1ba --- /dev/null +++ b/targets/device/avr/atmega328pb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega328PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 45; diff --git a/targets/device/avr/atmega328pb.s b/targets/device/avr/atmega328pb.s new file mode 100644 index 00000000..a7b0acd5 --- /dev/null +++ b/targets/device/avr/atmega328pb.s @@ -0,0 +1,114 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega328PB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI0_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TWI0 + jmp __vector_SPM_Ready + jmp __vector_USART0_START + jmp __vector_PCINT3 + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_USART1_START + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_OVF + jmp __vector_CFD + jmp __vector_PTC_EOC + jmp __vector_PTC_WCOMP + jmp __vector_SPI1_STC + jmp __vector_TWI1 + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI0_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI0 + IRQ __vector_SPM_Ready + IRQ __vector_USART0_START + IRQ __vector_PCINT3 + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_USART1_START + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_OVF + IRQ __vector_CFD + IRQ __vector_PTC_EOC + IRQ __vector_PTC_WCOMP + IRQ __vector_SPI1_STC + IRQ __vector_TWI1 + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_OVF diff --git a/targets/device/avr/atmega329.ld b/targets/device/avr/atmega329.ld new file mode 100644 index 00000000..9e5af152 --- /dev/null +++ b/targets/device/avr/atmega329.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega329.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/targets/device/avr/atmega329.s b/targets/device/avr/atmega329.s new file mode 100644 index 00000000..9b3d5514 --- /dev/null +++ b/targets/device/avr/atmega329.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega329.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega3290.ld b/targets/device/avr/atmega3290.ld new file mode 100644 index 00000000..22f361dc --- /dev/null +++ b/targets/device/avr/atmega3290.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega3290.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/targets/device/avr/atmega3290.s b/targets/device/avr/atmega3290.s new file mode 100644 index 00000000..9ff619a4 --- /dev/null +++ b/targets/device/avr/atmega3290.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega3290.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega3290a.ld b/targets/device/avr/atmega3290a.ld new file mode 100644 index 00000000..5941228e --- /dev/null +++ b/targets/device/avr/atmega3290a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega3290A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/targets/device/avr/atmega3290a.s b/targets/device/avr/atmega3290a.s new file mode 100644 index 00000000..45a9a6c4 --- /dev/null +++ b/targets/device/avr/atmega3290a.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega3290A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega3290p.ld b/targets/device/avr/atmega3290p.ld new file mode 100644 index 00000000..10be822d --- /dev/null +++ b/targets/device/avr/atmega3290p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega3290P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/targets/device/avr/atmega3290p.s b/targets/device/avr/atmega3290p.s new file mode 100644 index 00000000..b8edcb4c --- /dev/null +++ b/targets/device/avr/atmega3290p.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega3290P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega3290pa.ld b/targets/device/avr/atmega3290pa.ld new file mode 100644 index 00000000..7a324bb8 --- /dev/null +++ b/targets/device/avr/atmega3290pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega3290PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/targets/device/avr/atmega3290pa.s b/targets/device/avr/atmega3290pa.s new file mode 100644 index 00000000..d6e6311d --- /dev/null +++ b/targets/device/avr/atmega3290pa.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega3290PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega329a.ld b/targets/device/avr/atmega329a.ld new file mode 100644 index 00000000..ba61325e --- /dev/null +++ b/targets/device/avr/atmega329a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega329A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/targets/device/avr/atmega329a.s b/targets/device/avr/atmega329a.s new file mode 100644 index 00000000..e07d80a6 --- /dev/null +++ b/targets/device/avr/atmega329a.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega329A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega329p.ld b/targets/device/avr/atmega329p.ld new file mode 100644 index 00000000..fd94bce6 --- /dev/null +++ b/targets/device/avr/atmega329p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega329P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/targets/device/avr/atmega329p.s b/targets/device/avr/atmega329p.s new file mode 100644 index 00000000..faafeb86 --- /dev/null +++ b/targets/device/avr/atmega329p.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega329P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega329pa.ld b/targets/device/avr/atmega329pa.ld new file mode 100644 index 00000000..2741fe1b --- /dev/null +++ b/targets/device/avr/atmega329pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega329PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/targets/device/avr/atmega329pa.s b/targets/device/avr/atmega329pa.s new file mode 100644 index 00000000..f77042ad --- /dev/null +++ b/targets/device/avr/atmega329pa.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega329PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega32a.ld b/targets/device/avr/atmega32a.ld new file mode 100644 index 00000000..97263864 --- /dev/null +++ b/targets/device/avr/atmega32a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega32A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x60; +__ram_size = 0x800; +__num_isrs = 21; diff --git a/targets/device/avr/atmega32a.s b/targets/device/avr/atmega32a.s new file mode 100644 index 00000000..1bb5548d --- /dev/null +++ b/targets/device/avr/atmega32a.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega32A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RXC + jmp __vector_USART_UDRE + jmp __vector_USART_TXC + jmp __vector_ADC + jmp __vector_EE_RDY + jmp __vector_ANA_COMP + jmp __vector_TWI + jmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RXC + IRQ __vector_USART_UDRE + IRQ __vector_USART_TXC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TWI + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega32c1.ld b/targets/device/avr/atmega32c1.ld new file mode 100644 index 00000000..ef7079e2 --- /dev/null +++ b/targets/device/avr/atmega32c1.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega32C1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/targets/device/avr/atmega32c1.s b/targets/device/avr/atmega32c1.s new file mode 100644 index 00000000..9a6cacbe --- /dev/null +++ b/targets/device/avr/atmega32c1.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega32C1.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_ANACOMP0 + jmp __vector_ANACOMP1 + jmp __vector_ANACOMP2 + jmp __vector_ANACOMP3 + jmp __vector_PSC_FAULT + jmp __vector_PSC_EC + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_CAN_INT + jmp __vector_CAN_TOVF + jmp __vector_LIN_TC + jmp __vector_LIN_ERR + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_SPI_STC + jmp __vector_ADC + jmp __vector_WDT + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_ANACOMP0 + IRQ __vector_ANACOMP1 + IRQ __vector_ANACOMP2 + IRQ __vector_ANACOMP3 + IRQ __vector_PSC_FAULT + IRQ __vector_PSC_EC + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_CAN_INT + IRQ __vector_CAN_TOVF + IRQ __vector_LIN_TC + IRQ __vector_LIN_ERR + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega32hvb.ld b/targets/device/avr/atmega32hvb.ld new file mode 100644 index 00000000..5de9aca7 --- /dev/null +++ b/targets/device/avr/atmega32hvb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega32HVB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 29; diff --git a/targets/device/avr/atmega32hvb.s b/targets/device/avr/atmega32hvb.s new file mode 100644 index 00000000..c529c26e --- /dev/null +++ b/targets/device/avr/atmega32hvb.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega32HVB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_BPINT + jmp __vector_VREGMON + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_WDT + jmp __vector_BGSCD + jmp __vector_CHDET + jmp __vector_TIMER1_IC + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_IC + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_TWIBUSCD + jmp __vector_TWI + jmp __vector_SPI_STC + jmp __vector_VADC + jmp __vector_CCADC_CONV + jmp __vector_CCADC_REG_CUR + jmp __vector_CCADC_ACC + jmp __vector_EE_READY + jmp __vector_SPM + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_BPINT + IRQ __vector_VREGMON + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_BGSCD + IRQ __vector_CHDET + IRQ __vector_TIMER1_IC + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_IC + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_TWIBUSCD + IRQ __vector_TWI + IRQ __vector_SPI_STC + IRQ __vector_VADC + IRQ __vector_CCADC_CONV + IRQ __vector_CCADC_REG_CUR + IRQ __vector_CCADC_ACC + IRQ __vector_EE_READY + IRQ __vector_SPM diff --git a/targets/device/avr/atmega32hvbrevb.ld b/targets/device/avr/atmega32hvbrevb.ld new file mode 100644 index 00000000..a859c3b2 --- /dev/null +++ b/targets/device/avr/atmega32hvbrevb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega32HVBrevB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 29; diff --git a/targets/device/avr/atmega32hvbrevb.s b/targets/device/avr/atmega32hvbrevb.s new file mode 100644 index 00000000..19572025 --- /dev/null +++ b/targets/device/avr/atmega32hvbrevb.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega32HVBrevB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_BPINT + jmp __vector_VREGMON + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_WDT + jmp __vector_BGSCD + jmp __vector_CHDET + jmp __vector_TIMER1_IC + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_IC + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_TWIBUSCD + jmp __vector_TWI + jmp __vector_SPI_STC + jmp __vector_VADC + jmp __vector_CCADC_CONV + jmp __vector_CCADC_REG_CUR + jmp __vector_CCADC_ACC + jmp __vector_EE_READY + jmp __vector_SPM + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_BPINT + IRQ __vector_VREGMON + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_BGSCD + IRQ __vector_CHDET + IRQ __vector_TIMER1_IC + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_IC + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_TWIBUSCD + IRQ __vector_TWI + IRQ __vector_SPI_STC + IRQ __vector_VADC + IRQ __vector_CCADC_CONV + IRQ __vector_CCADC_REG_CUR + IRQ __vector_CCADC_ACC + IRQ __vector_EE_READY + IRQ __vector_SPM diff --git a/targets/device/avr/atmega32m1.ld b/targets/device/avr/atmega32m1.ld new file mode 100644 index 00000000..6f966115 --- /dev/null +++ b/targets/device/avr/atmega32m1.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega32M1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/targets/device/avr/atmega32m1.s b/targets/device/avr/atmega32m1.s new file mode 100644 index 00000000..33565bd2 --- /dev/null +++ b/targets/device/avr/atmega32m1.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega32M1.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_ANACOMP0 + jmp __vector_ANACOMP1 + jmp __vector_ANACOMP2 + jmp __vector_ANACOMP3 + jmp __vector_PSC_FAULT + jmp __vector_PSC_EC + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_CAN_INT + jmp __vector_CAN_TOVF + jmp __vector_LIN_TC + jmp __vector_LIN_ERR + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_SPI_STC + jmp __vector_ADC + jmp __vector_WDT + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_ANACOMP0 + IRQ __vector_ANACOMP1 + IRQ __vector_ANACOMP2 + IRQ __vector_ANACOMP3 + IRQ __vector_PSC_FAULT + IRQ __vector_PSC_EC + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_CAN_INT + IRQ __vector_CAN_TOVF + IRQ __vector_LIN_TC + IRQ __vector_LIN_ERR + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega32u2.ld b/targets/device/avr/atmega32u2.ld new file mode 100644 index 00000000..0d9544b2 --- /dev/null +++ b/targets/device/avr/atmega32u2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega32U2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 29; diff --git a/targets/device/avr/atmega32u2.s b/targets/device/avr/atmega32u2.s new file mode 100644 index 00000000..ec1e6e37 --- /dev/null +++ b/targets/device/avr/atmega32u2.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega32U2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega32u4.ld b/targets/device/avr/atmega32u4.ld new file mode 100644 index 00000000..41bd8942 --- /dev/null +++ b/targets/device/avr/atmega32u4.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega32U4.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_start = 0x100; +__ram_size = 0xa00; +__num_isrs = 43; diff --git a/targets/device/avr/atmega32u4.s b/targets/device/avr/atmega32u4.s new file mode 100644 index 00000000..2711974b --- /dev/null +++ b/targets/device/avr/atmega32u4.s @@ -0,0 +1,110 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega32U4.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_Reserved1 + jmp __vector_Reserved2 + jmp __vector_INT6 + jmp __vector_Reserved3 + jmp __vector_PCINT0 + jmp __vector_USB_GEN + jmp __vector_USB_COM + jmp __vector_WDT + jmp __vector_Reserved4 + jmp __vector_Reserved5 + jmp __vector_Reserved6 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPD + jmp __vector_TIMER4_OVF + jmp __vector_TIMER4_FPF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_Reserved1 + IRQ __vector_Reserved2 + IRQ __vector_INT6 + IRQ __vector_Reserved3 + IRQ __vector_PCINT0 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_Reserved4 + IRQ __vector_Reserved5 + IRQ __vector_Reserved6 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPD + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER4_FPF diff --git a/targets/device/avr/atmega406.ld b/targets/device/avr/atmega406.ld new file mode 100644 index 00000000..3c7d70a0 --- /dev/null +++ b/targets/device/avr/atmega406.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega406.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0xa000; +__ram_start = 0x100; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/targets/device/avr/atmega406.s b/targets/device/avr/atmega406.s new file mode 100644 index 00000000..8b454a84 --- /dev/null +++ b/targets/device/avr/atmega406.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega406.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_BPINT + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_WDT + jmp __vector_WAKE_UP + jmp __vector_TIM1_COMP + jmp __vector_TIM1_OVF + jmp __vector_TIM0_COMPA + jmp __vector_TIM0_COMPB + jmp __vector_TIM0_OVF + jmp __vector_TWI_BUS_CD + jmp __vector_TWI + jmp __vector_VADC + jmp __vector_CCADC_CONV + jmp __vector_CCADC_REG_CUR + jmp __vector_CCADC_ACC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_BPINT + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_WAKE_UP + IRQ __vector_TIM1_COMP + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_TWI_BUS_CD + IRQ __vector_TWI + IRQ __vector_VADC + IRQ __vector_CCADC_CONV + IRQ __vector_CCADC_REG_CUR + IRQ __vector_CCADC_ACC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega48.ld b/targets/device/avr/atmega48.ld new file mode 100644 index 00000000..9f7d0c61 --- /dev/null +++ b/targets/device/avr/atmega48.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega48.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/targets/device/avr/atmega48.s b/targets/device/avr/atmega48.s new file mode 100644 index 00000000..a63d533d --- /dev/null +++ b/targets/device/avr/atmega48.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega48.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega48a.ld b/targets/device/avr/atmega48a.ld new file mode 100644 index 00000000..29057907 --- /dev/null +++ b/targets/device/avr/atmega48a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega48A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/targets/device/avr/atmega48a.s b/targets/device/avr/atmega48a.s new file mode 100644 index 00000000..a4abca1c --- /dev/null +++ b/targets/device/avr/atmega48a.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega48A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega48p.ld b/targets/device/avr/atmega48p.ld new file mode 100644 index 00000000..771b2f38 --- /dev/null +++ b/targets/device/avr/atmega48p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega48P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/targets/device/avr/atmega48p.s b/targets/device/avr/atmega48p.s new file mode 100644 index 00000000..a1b95893 --- /dev/null +++ b/targets/device/avr/atmega48p.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega48P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega48pa.ld b/targets/device/avr/atmega48pa.ld new file mode 100644 index 00000000..43367016 --- /dev/null +++ b/targets/device/avr/atmega48pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega48PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/targets/device/avr/atmega48pa.s b/targets/device/avr/atmega48pa.s new file mode 100644 index 00000000..267658ba --- /dev/null +++ b/targets/device/avr/atmega48pa.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega48PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega48pb.ld b/targets/device/avr/atmega48pb.ld new file mode 100644 index 00000000..bd3522b9 --- /dev/null +++ b/targets/device/avr/atmega48pb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega48PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 27; diff --git a/targets/device/avr/atmega48pb.s b/targets/device/avr/atmega48pb.s new file mode 100644 index 00000000..bbff0ba2 --- /dev/null +++ b/targets/device/avr/atmega48pb.s @@ -0,0 +1,78 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega48PB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + rjmp __vector_USART_START + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready + IRQ __vector_USART_START diff --git a/targets/device/avr/atmega64.ld b/targets/device/avr/atmega64.ld new file mode 100644 index 00000000..0a16ea0c --- /dev/null +++ b/targets/device/avr/atmega64.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega64.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 35; diff --git a/targets/device/avr/atmega64.s b/targets/device/avr/atmega64.s new file mode 100644 index 00000000..f42b554f --- /dev/null +++ b/targets/device/avr/atmega64.s @@ -0,0 +1,94 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega64.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega640.ld b/targets/device/avr/atmega640.ld new file mode 100644 index 00000000..2d2e093d --- /dev/null +++ b/targets/device/avr/atmega640.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega640.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x200; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/targets/device/avr/atmega640.s b/targets/device/avr/atmega640.s new file mode 100644 index 00000000..46b9b5bd --- /dev/null +++ b/targets/device/avr/atmega640.s @@ -0,0 +1,138 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega640.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_USART2_RX + jmp __vector_USART2_UDRE + jmp __vector_USART2_TX + jmp __vector_USART3_RX + jmp __vector_USART3_UDRE + jmp __vector_USART3_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_USART2_RX + IRQ __vector_USART2_UDRE + IRQ __vector_USART2_TX + IRQ __vector_USART3_RX + IRQ __vector_USART3_UDRE + IRQ __vector_USART3_TX diff --git a/targets/device/avr/atmega644.ld b/targets/device/avr/atmega644.ld new file mode 100644 index 00000000..3896dcc6 --- /dev/null +++ b/targets/device/avr/atmega644.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega644.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 28; diff --git a/targets/device/avr/atmega644.s b/targets/device/avr/atmega644.s new file mode 100644 index 00000000..eba50329 --- /dev/null +++ b/targets/device/avr/atmega644.s @@ -0,0 +1,80 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega644.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega644a.ld b/targets/device/avr/atmega644a.ld new file mode 100644 index 00000000..f44cc293 --- /dev/null +++ b/targets/device/avr/atmega644a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega644A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/targets/device/avr/atmega644a.s b/targets/device/avr/atmega644a.s new file mode 100644 index 00000000..aacfaebd --- /dev/null +++ b/targets/device/avr/atmega644a.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega644A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega644p.ld b/targets/device/avr/atmega644p.ld new file mode 100644 index 00000000..ae17a6f5 --- /dev/null +++ b/targets/device/avr/atmega644p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega644P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/targets/device/avr/atmega644p.s b/targets/device/avr/atmega644p.s new file mode 100644 index 00000000..a9c5756c --- /dev/null +++ b/targets/device/avr/atmega644p.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega644P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega644pa.ld b/targets/device/avr/atmega644pa.ld new file mode 100644 index 00000000..4bf97450 --- /dev/null +++ b/targets/device/avr/atmega644pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega644PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/targets/device/avr/atmega644pa.s b/targets/device/avr/atmega644pa.s new file mode 100644 index 00000000..5898ee6e --- /dev/null +++ b/targets/device/avr/atmega644pa.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega644PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX diff --git a/targets/device/avr/atmega644rfr2.ld b/targets/device/avr/atmega644rfr2.ld new file mode 100644 index 00000000..555a24d0 --- /dev/null +++ b/targets/device/avr/atmega644rfr2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega644RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x200; +__ram_size = 0x2000; +__num_isrs = 71; diff --git a/targets/device/avr/atmega644rfr2.s b/targets/device/avr/atmega644rfr2.s new file mode 100644 index 00000000..ee07aadf --- /dev/null +++ b/targets/device/avr/atmega644rfr2.s @@ -0,0 +1,172 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega644RFR2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_TRX24_PLL_LOCK + jmp __vector_TRX24_PLL_UNLOCK + jmp __vector_TRX24_RX_START + jmp __vector_TRX24_RX_END + jmp __vector_TRX24_CCA_ED_DONE + jmp __vector_TRX24_XAH_AMI + jmp __vector_TRX24_TX_END + jmp __vector_TRX24_AWAKE + jmp __vector_SCNT_CMP1 + jmp __vector_SCNT_CMP2 + jmp __vector_SCNT_CMP3 + jmp __vector_SCNT_OVFL + jmp __vector_SCNT_BACKOFF + jmp __vector_AES_READY + jmp __vector_BAT_LOW + jmp __vector_TRX24_TX_START + jmp __vector_TRX24_AMI0 + jmp __vector_TRX24_AMI1 + jmp __vector_TRX24_AMI2 + jmp __vector_TRX24_AMI3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_TRX24_PLL_LOCK + IRQ __vector_TRX24_PLL_UNLOCK + IRQ __vector_TRX24_RX_START + IRQ __vector_TRX24_RX_END + IRQ __vector_TRX24_CCA_ED_DONE + IRQ __vector_TRX24_XAH_AMI + IRQ __vector_TRX24_TX_END + IRQ __vector_TRX24_AWAKE + IRQ __vector_SCNT_CMP1 + IRQ __vector_SCNT_CMP2 + IRQ __vector_SCNT_CMP3 + IRQ __vector_SCNT_OVFL + IRQ __vector_SCNT_BACKOFF + IRQ __vector_AES_READY + IRQ __vector_BAT_LOW + IRQ __vector_TRX24_TX_START + IRQ __vector_TRX24_AMI0 + IRQ __vector_TRX24_AMI1 + IRQ __vector_TRX24_AMI2 + IRQ __vector_TRX24_AMI3 diff --git a/targets/device/avr/atmega645.ld b/targets/device/avr/atmega645.ld new file mode 100644 index 00000000..a6fe0481 --- /dev/null +++ b/targets/device/avr/atmega645.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega645.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 22; diff --git a/targets/device/avr/atmega645.s b/targets/device/avr/atmega645.s new file mode 100644 index 00000000..0a3b2d3d --- /dev/null +++ b/targets/device/avr/atmega645.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega645.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega6450.ld b/targets/device/avr/atmega6450.ld new file mode 100644 index 00000000..8197ca7c --- /dev/null +++ b/targets/device/avr/atmega6450.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega6450.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/targets/device/avr/atmega6450.s b/targets/device/avr/atmega6450.s new file mode 100644 index 00000000..5549aa96 --- /dev/null +++ b/targets/device/avr/atmega6450.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega6450.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_NOT_USED + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_NOT_USED + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega6450a.ld b/targets/device/avr/atmega6450a.ld new file mode 100644 index 00000000..a25bfa03 --- /dev/null +++ b/targets/device/avr/atmega6450a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega6450A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/targets/device/avr/atmega6450a.s b/targets/device/avr/atmega6450a.s new file mode 100644 index 00000000..7bcc6f7a --- /dev/null +++ b/targets/device/avr/atmega6450a.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega6450A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_NOT_USED + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_NOT_USED + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega6450p.ld b/targets/device/avr/atmega6450p.ld new file mode 100644 index 00000000..14724cb5 --- /dev/null +++ b/targets/device/avr/atmega6450p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega6450P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/targets/device/avr/atmega6450p.s b/targets/device/avr/atmega6450p.s new file mode 100644 index 00000000..1029eb65 --- /dev/null +++ b/targets/device/avr/atmega6450p.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega6450P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_NOT_USED + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_NOT_USED + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega645a.ld b/targets/device/avr/atmega645a.ld new file mode 100644 index 00000000..40c384f8 --- /dev/null +++ b/targets/device/avr/atmega645a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega645A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 22; diff --git a/targets/device/avr/atmega645a.s b/targets/device/avr/atmega645a.s new file mode 100644 index 00000000..ee9dee81 --- /dev/null +++ b/targets/device/avr/atmega645a.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega645A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega645p.ld b/targets/device/avr/atmega645p.ld new file mode 100644 index 00000000..06f78748 --- /dev/null +++ b/targets/device/avr/atmega645p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega645P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 22; diff --git a/targets/device/avr/atmega645p.s b/targets/device/avr/atmega645p.s new file mode 100644 index 00000000..4a4b9064 --- /dev/null +++ b/targets/device/avr/atmega645p.s @@ -0,0 +1,68 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega645P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega649.ld b/targets/device/avr/atmega649.ld new file mode 100644 index 00000000..72be6a62 --- /dev/null +++ b/targets/device/avr/atmega649.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega649.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 23; diff --git a/targets/device/avr/atmega649.s b/targets/device/avr/atmega649.s new file mode 100644 index 00000000..05c9c649 --- /dev/null +++ b/targets/device/avr/atmega649.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega649.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega6490.ld b/targets/device/avr/atmega6490.ld new file mode 100644 index 00000000..bd77e7aa --- /dev/null +++ b/targets/device/avr/atmega6490.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega6490.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/targets/device/avr/atmega6490.s b/targets/device/avr/atmega6490.s new file mode 100644 index 00000000..8a8e1278 --- /dev/null +++ b/targets/device/avr/atmega6490.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega6490.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega6490a.ld b/targets/device/avr/atmega6490a.ld new file mode 100644 index 00000000..ffe02ed3 --- /dev/null +++ b/targets/device/avr/atmega6490a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega6490A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/targets/device/avr/atmega6490a.s b/targets/device/avr/atmega6490a.s new file mode 100644 index 00000000..a9df9723 --- /dev/null +++ b/targets/device/avr/atmega6490a.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega6490A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega6490p.ld b/targets/device/avr/atmega6490p.ld new file mode 100644 index 00000000..34f9d045 --- /dev/null +++ b/targets/device/avr/atmega6490p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega6490P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/targets/device/avr/atmega6490p.s b/targets/device/avr/atmega6490p.s new file mode 100644 index 00000000..deaa3d60 --- /dev/null +++ b/targets/device/avr/atmega6490p.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega6490P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART_RX + jmp __vector_USART_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + jmp __vector_PCINT2 + jmp __vector_PCINT3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 diff --git a/targets/device/avr/atmega649a.ld b/targets/device/avr/atmega649a.ld new file mode 100644 index 00000000..eb715e42 --- /dev/null +++ b/targets/device/avr/atmega649a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega649A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 23; diff --git a/targets/device/avr/atmega649a.s b/targets/device/avr/atmega649a.s new file mode 100644 index 00000000..478b4f37 --- /dev/null +++ b/targets/device/avr/atmega649a.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega649A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega649p.ld b/targets/device/avr/atmega649p.ld new file mode 100644 index 00000000..e73604e3 --- /dev/null +++ b/targets/device/avr/atmega649p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega649P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 23; diff --git a/targets/device/avr/atmega649p.s b/targets/device/avr/atmega649p.s new file mode 100644 index 00000000..1c5cc85c --- /dev/null +++ b/targets/device/avr/atmega649p.s @@ -0,0 +1,70 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega649P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_SPM_READY + jmp __vector_LCD + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_SPM_READY + IRQ __vector_LCD diff --git a/targets/device/avr/atmega64a.ld b/targets/device/avr/atmega64a.ld new file mode 100644 index 00000000..72f78086 --- /dev/null +++ b/targets/device/avr/atmega64a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega64A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 35; diff --git a/targets/device/avr/atmega64a.s b/targets/device/avr/atmega64a.s new file mode 100644 index 00000000..214096f1 --- /dev/null +++ b/targets/device/avr/atmega64a.s @@ -0,0 +1,94 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega64A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_TIMER2_COMP + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMP + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_ANALOG_COMP + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMP + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega64c1.ld b/targets/device/avr/atmega64c1.ld new file mode 100644 index 00000000..4f7c3bb8 --- /dev/null +++ b/targets/device/avr/atmega64c1.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega64C1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/targets/device/avr/atmega64c1.s b/targets/device/avr/atmega64c1.s new file mode 100644 index 00000000..6126bec8 --- /dev/null +++ b/targets/device/avr/atmega64c1.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega64C1.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_ANACOMP0 + jmp __vector_ANACOMP1 + jmp __vector_ANACOMP2 + jmp __vector_ANACOMP3 + jmp __vector_PSC_FAULT + jmp __vector_PSC_EC + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_CAN_INT + jmp __vector_CAN_TOVF + jmp __vector_LIN_TC + jmp __vector_LIN_ERR + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_SPI_STC + jmp __vector_ADC + jmp __vector_WDT + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_ANACOMP0 + IRQ __vector_ANACOMP1 + IRQ __vector_ANACOMP2 + IRQ __vector_ANACOMP3 + IRQ __vector_PSC_FAULT + IRQ __vector_PSC_EC + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_CAN_INT + IRQ __vector_CAN_TOVF + IRQ __vector_LIN_TC + IRQ __vector_LIN_ERR + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega64hve2.ld b/targets/device/avr/atmega64hve2.ld new file mode 100644 index 00000000..b573f689 --- /dev/null +++ b/targets/device/avr/atmega64hve2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega64HVE2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/targets/device/avr/atmega64hve2.s b/targets/device/avr/atmega64hve2.s new file mode 100644 index 00000000..b59bdd0c --- /dev/null +++ b/targets/device/avr/atmega64hve2.s @@ -0,0 +1,74 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega64HVE2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_WDT + jmp __vector_WAKEUP + jmp __vector_TIMER1_IC + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_IC + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_LIN_STATUS + jmp __vector_LIN_ERROR + jmp __vector_SPI_STC + jmp __vector_VADC_CONV + jmp __vector_VADC_ACC + jmp __vector_CADC_CONV + jmp __vector_CADC_REG_CUR + jmp __vector_CADC_ACC + jmp __vector_EE_READY + jmp __vector_SPM + jmp __vector_PLL + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_WAKEUP + IRQ __vector_TIMER1_IC + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_IC + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_LIN_STATUS + IRQ __vector_LIN_ERROR + IRQ __vector_SPI_STC + IRQ __vector_VADC_CONV + IRQ __vector_VADC_ACC + IRQ __vector_CADC_CONV + IRQ __vector_CADC_REG_CUR + IRQ __vector_CADC_ACC + IRQ __vector_EE_READY + IRQ __vector_SPM + IRQ __vector_PLL diff --git a/targets/device/avr/atmega64m1.ld b/targets/device/avr/atmega64m1.ld new file mode 100644 index 00000000..c51c5ffc --- /dev/null +++ b/targets/device/avr/atmega64m1.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega64M1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x100; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/targets/device/avr/atmega64m1.s b/targets/device/avr/atmega64m1.s new file mode 100644 index 00000000..540f2088 --- /dev/null +++ b/targets/device/avr/atmega64m1.s @@ -0,0 +1,86 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega64M1.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_ANACOMP0 + jmp __vector_ANACOMP1 + jmp __vector_ANACOMP2 + jmp __vector_ANACOMP3 + jmp __vector_PSC_FAULT + jmp __vector_PSC_EC + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_CAN_INT + jmp __vector_CAN_TOVF + jmp __vector_LIN_TC + jmp __vector_LIN_ERR + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_PCINT3 + jmp __vector_SPI_STC + jmp __vector_ADC + jmp __vector_WDT + jmp __vector_EE_READY + jmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_ANACOMP0 + IRQ __vector_ANACOMP1 + IRQ __vector_ANACOMP2 + IRQ __vector_ANACOMP3 + IRQ __vector_PSC_FAULT + IRQ __vector_PSC_EC + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_CAN_INT + IRQ __vector_CAN_TOVF + IRQ __vector_LIN_TC + IRQ __vector_LIN_ERR + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/atmega64rfr2.ld b/targets/device/avr/atmega64rfr2.ld new file mode 100644 index 00000000..cccff8f1 --- /dev/null +++ b/targets/device/avr/atmega64rfr2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega64RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_start = 0x200; +__ram_size = 0x2000; +__num_isrs = 71; diff --git a/targets/device/avr/atmega64rfr2.s b/targets/device/avr/atmega64rfr2.s new file mode 100644 index 00000000..395583f6 --- /dev/null +++ b/targets/device/avr/atmega64rfr2.s @@ -0,0 +1,172 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega64RFR2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_INT2 + jmp __vector_INT3 + jmp __vector_INT4 + jmp __vector_INT5 + jmp __vector_INT6 + jmp __vector_INT7 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER2_COMPA + jmp __vector_TIMER2_COMPB + jmp __vector_TIMER2_OVF + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_COMPC + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_SPI_STC + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_ANALOG_COMP + jmp __vector_ADC + jmp __vector_EE_READY + jmp __vector_TIMER3_CAPT + jmp __vector_TIMER3_COMPA + jmp __vector_TIMER3_COMPB + jmp __vector_TIMER3_COMPC + jmp __vector_TIMER3_OVF + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_TWI + jmp __vector_SPM_READY + jmp __vector_TIMER4_CAPT + jmp __vector_TIMER4_COMPA + jmp __vector_TIMER4_COMPB + jmp __vector_TIMER4_COMPC + jmp __vector_TIMER4_OVF + jmp __vector_TIMER5_CAPT + jmp __vector_TIMER5_COMPA + jmp __vector_TIMER5_COMPB + jmp __vector_TIMER5_COMPC + jmp __vector_TIMER5_OVF + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_default + jmp __vector_TRX24_PLL_LOCK + jmp __vector_TRX24_PLL_UNLOCK + jmp __vector_TRX24_RX_START + jmp __vector_TRX24_RX_END + jmp __vector_TRX24_CCA_ED_DONE + jmp __vector_TRX24_XAH_AMI + jmp __vector_TRX24_TX_END + jmp __vector_TRX24_AWAKE + jmp __vector_SCNT_CMP1 + jmp __vector_SCNT_CMP2 + jmp __vector_SCNT_CMP3 + jmp __vector_SCNT_OVFL + jmp __vector_SCNT_BACKOFF + jmp __vector_AES_READY + jmp __vector_BAT_LOW + jmp __vector_TRX24_TX_START + jmp __vector_TRX24_AMI0 + jmp __vector_TRX24_AMI1 + jmp __vector_TRX24_AMI2 + jmp __vector_TRX24_AMI3 + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_COMPC + IRQ __vector_TIMER3_OVF + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI + IRQ __vector_SPM_READY + IRQ __vector_TIMER4_CAPT + IRQ __vector_TIMER4_COMPA + IRQ __vector_TIMER4_COMPB + IRQ __vector_TIMER4_COMPC + IRQ __vector_TIMER4_OVF + IRQ __vector_TIMER5_CAPT + IRQ __vector_TIMER5_COMPA + IRQ __vector_TIMER5_COMPB + IRQ __vector_TIMER5_COMPC + IRQ __vector_TIMER5_OVF + IRQ __vector_TRX24_PLL_LOCK + IRQ __vector_TRX24_PLL_UNLOCK + IRQ __vector_TRX24_RX_START + IRQ __vector_TRX24_RX_END + IRQ __vector_TRX24_CCA_ED_DONE + IRQ __vector_TRX24_XAH_AMI + IRQ __vector_TRX24_TX_END + IRQ __vector_TRX24_AWAKE + IRQ __vector_SCNT_CMP1 + IRQ __vector_SCNT_CMP2 + IRQ __vector_SCNT_CMP3 + IRQ __vector_SCNT_OVFL + IRQ __vector_SCNT_BACKOFF + IRQ __vector_AES_READY + IRQ __vector_BAT_LOW + IRQ __vector_TRX24_TX_START + IRQ __vector_TRX24_AMI0 + IRQ __vector_TRX24_AMI1 + IRQ __vector_TRX24_AMI2 + IRQ __vector_TRX24_AMI3 diff --git a/targets/device/avr/atmega8.ld b/targets/device/avr/atmega8.ld new file mode 100644 index 00000000..15143738 --- /dev/null +++ b/targets/device/avr/atmega8.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega8.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x400; +__num_isrs = 19; diff --git a/targets/device/avr/atmega8.s b/targets/device/avr/atmega8.s new file mode 100644 index 00000000..cfada70f --- /dev/null +++ b/targets/device/avr/atmega8.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega8.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_TIMER2_COMP + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RXC + rjmp __vector_USART_UDRE + rjmp __vector_USART_TXC + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_TWI + rjmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RXC + IRQ __vector_USART_UDRE + IRQ __vector_USART_TXC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TWI + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega8515.ld b/targets/device/avr/atmega8515.ld new file mode 100644 index 00000000..95f38469 --- /dev/null +++ b/targets/device/avr/atmega8515.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega8515.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x200; +__num_isrs = 17; diff --git a/targets/device/avr/atmega8515.s b/targets/device/avr/atmega8515.s new file mode 100644 index 00000000..b9e45656 --- /dev/null +++ b/targets/device/avr/atmega8515.s @@ -0,0 +1,58 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega8515.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ANA_COMP + rjmp __vector_INT2 + rjmp __vector_TIMER0_COMP + rjmp __vector_EE_RDY + rjmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ANA_COMP + IRQ __vector_INT2 + IRQ __vector_TIMER0_COMP + IRQ __vector_EE_RDY + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega8535.ld b/targets/device/avr/atmega8535.ld new file mode 100644 index 00000000..447e05d2 --- /dev/null +++ b/targets/device/avr/atmega8535.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega8535.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x200; +__num_isrs = 21; diff --git a/targets/device/avr/atmega8535.s b/targets/device/avr/atmega8535.s new file mode 100644 index 00000000..172f9798 --- /dev/null +++ b/targets/device/avr/atmega8535.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega8535.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_TIMER2_COMP + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_TWI + rjmp __vector_INT2 + rjmp __vector_TIMER0_COMP + rjmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TWI + IRQ __vector_INT2 + IRQ __vector_TIMER0_COMP + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega88.ld b/targets/device/avr/atmega88.ld new file mode 100644 index 00000000..2a847b6c --- /dev/null +++ b/targets/device/avr/atmega88.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega88.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/targets/device/avr/atmega88.s b/targets/device/avr/atmega88.s new file mode 100644 index 00000000..79f799b1 --- /dev/null +++ b/targets/device/avr/atmega88.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega88.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega88a.ld b/targets/device/avr/atmega88a.ld new file mode 100644 index 00000000..e1bb2f22 --- /dev/null +++ b/targets/device/avr/atmega88a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega88A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/targets/device/avr/atmega88a.s b/targets/device/avr/atmega88a.s new file mode 100644 index 00000000..8cc42a0d --- /dev/null +++ b/targets/device/avr/atmega88a.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega88A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega88p.ld b/targets/device/avr/atmega88p.ld new file mode 100644 index 00000000..c61efa3c --- /dev/null +++ b/targets/device/avr/atmega88p.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega88P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/targets/device/avr/atmega88p.s b/targets/device/avr/atmega88p.s new file mode 100644 index 00000000..1465cb47 --- /dev/null +++ b/targets/device/avr/atmega88p.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega88P.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega88pa.ld b/targets/device/avr/atmega88pa.ld new file mode 100644 index 00000000..d0df3ab8 --- /dev/null +++ b/targets/device/avr/atmega88pa.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega88PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/targets/device/avr/atmega88pa.s b/targets/device/avr/atmega88pa.s new file mode 100644 index 00000000..01e1e53a --- /dev/null +++ b/targets/device/avr/atmega88pa.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega88PA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready diff --git a/targets/device/avr/atmega88pb.ld b/targets/device/avr/atmega88pb.ld new file mode 100644 index 00000000..e69ed26a --- /dev/null +++ b/targets/device/avr/atmega88pb.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega88PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 27; diff --git a/targets/device/avr/atmega88pb.s b/targets/device/avr/atmega88pb.s new file mode 100644 index 00000000..85410643 --- /dev/null +++ b/targets/device/avr/atmega88pb.s @@ -0,0 +1,78 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega88PB.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + rjmp __vector_SPM_Ready + rjmp __vector_USART_START + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI + IRQ __vector_SPM_Ready + IRQ __vector_USART_START diff --git a/targets/device/avr/atmega8a.ld b/targets/device/avr/atmega8a.ld new file mode 100644 index 00000000..8f9249e4 --- /dev/null +++ b/targets/device/avr/atmega8a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega8A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x400; +__num_isrs = 19; diff --git a/targets/device/avr/atmega8a.s b/targets/device/avr/atmega8a.s new file mode 100644 index 00000000..3fee054c --- /dev/null +++ b/targets/device/avr/atmega8a.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega8A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_TIMER2_COMP + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_RXC + rjmp __vector_USART_UDRE + rjmp __vector_USART_TXC + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_TWI + rjmp __vector_SPM_RDY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER2_COMP + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_RXC + IRQ __vector_USART_UDRE + IRQ __vector_USART_TXC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TWI + IRQ __vector_SPM_RDY diff --git a/targets/device/avr/atmega8hva.ld b/targets/device/avr/atmega8hva.ld new file mode 100644 index 00000000..907d5984 --- /dev/null +++ b/targets/device/avr/atmega8hva.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega8HVA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 21; diff --git a/targets/device/avr/atmega8hva.s b/targets/device/avr/atmega8hva.s new file mode 100644 index 00000000..5dabeb3a --- /dev/null +++ b/targets/device/avr/atmega8hva.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega8HVA.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_BPINT + rjmp __vector_VREGMON + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_INT2 + rjmp __vector_WDT + rjmp __vector_TIMER1_IC + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_IC + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_VADC + rjmp __vector_CCADC_CONV + rjmp __vector_CCADC_REG_CUR + rjmp __vector_CCADC_ACC + rjmp __vector_EE_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_BPINT + IRQ __vector_VREGMON + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_WDT + IRQ __vector_TIMER1_IC + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_IC + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_VADC + IRQ __vector_CCADC_CONV + IRQ __vector_CCADC_REG_CUR + IRQ __vector_CCADC_ACC + IRQ __vector_EE_READY diff --git a/targets/device/avr/atmega8u2.ld b/targets/device/avr/atmega8u2.ld new file mode 100644 index 00000000..b9447a36 --- /dev/null +++ b/targets/device/avr/atmega8u2.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATmega8U2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/targets/device/avr/atmega8u2.s b/targets/device/avr/atmega8u2.s new file mode 100644 index 00000000..6d93f7ce --- /dev/null +++ b/targets/device/avr/atmega8u2.s @@ -0,0 +1,82 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATmega8U2.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_INT2 + rjmp __vector_INT3 + rjmp __vector_INT4 + rjmp __vector_INT5 + rjmp __vector_INT6 + rjmp __vector_INT7 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_USB_GEN + rjmp __vector_USB_COM + rjmp __vector_WDT + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_COMPC + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART1_RX + rjmp __vector_USART1_UDRE + rjmp __vector_USART1_TX + rjmp __vector_ANALOG_COMP + rjmp __vector_EE_READY + rjmp __vector_SPM_READY + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_INT2 + IRQ __vector_INT3 + IRQ __vector_INT4 + IRQ __vector_INT5 + IRQ __vector_INT6 + IRQ __vector_INT7 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_USB_GEN + IRQ __vector_USB_COM + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_COMPC + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_ANALOG_COMP + IRQ __vector_EE_READY + IRQ __vector_SPM_READY diff --git a/targets/device/avr/attiny10.ld b/targets/device/avr/attiny10.ld new file mode 100644 index 00000000..c0fdcc25 --- /dev/null +++ b/targets/device/avr/attiny10.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny10.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__mapped_flash_start = 0x4000; +__ram_start = 0x40; +__ram_size = 0x20; +__num_isrs = 11; diff --git a/targets/device/avr/attiny10.s b/targets/device/avr/attiny10.s new file mode 100644 index 00000000..0cc31aaa --- /dev/null +++ b/targets/device/avr/attiny10.s @@ -0,0 +1,46 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny10.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIM0_CAPT + rjmp __vector_TIM0_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_ANA_COMP + rjmp __vector_WDT + rjmp __vector_VLM + rjmp __vector_ADC + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIM0_CAPT + IRQ __vector_TIM0_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_ANA_COMP + IRQ __vector_WDT + IRQ __vector_VLM + IRQ __vector_ADC diff --git a/targets/device/avr/attiny102.ld b/targets/device/avr/attiny102.ld new file mode 100644 index 00000000..2c6c2b6b --- /dev/null +++ b/targets/device/avr/attiny102.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny102.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__mapped_flash_start = 0x4000; +__ram_start = 0x40; +__ram_size = 0x20; +__num_isrs = 16; diff --git a/targets/device/avr/attiny102.s b/targets/device/avr/attiny102.s new file mode 100644 index 00000000..b72522bd --- /dev/null +++ b/targets/device/avr/attiny102.s @@ -0,0 +1,56 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny102.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_TIM0_CAPT + rjmp __vector_TIM0_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_ANA_COMP + rjmp __vector_WDT + rjmp __vector_VLM + rjmp __vector_ADC + rjmp __vector_USART_RXS + rjmp __vector_USART_RXC + rjmp __vector_USART_DRE + rjmp __vector_USART_TXC + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIM0_CAPT + IRQ __vector_TIM0_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_ANA_COMP + IRQ __vector_WDT + IRQ __vector_VLM + IRQ __vector_ADC + IRQ __vector_USART_RXS + IRQ __vector_USART_RXC + IRQ __vector_USART_DRE + IRQ __vector_USART_TXC diff --git a/targets/device/avr/attiny104.ld b/targets/device/avr/attiny104.ld new file mode 100644 index 00000000..0842fb59 --- /dev/null +++ b/targets/device/avr/attiny104.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny104.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__mapped_flash_start = 0x4000; +__ram_start = 0x40; +__ram_size = 0x20; +__num_isrs = 16; diff --git a/targets/device/avr/attiny104.s b/targets/device/avr/attiny104.s new file mode 100644 index 00000000..298cb43e --- /dev/null +++ b/targets/device/avr/attiny104.s @@ -0,0 +1,56 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny104.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_TIM0_CAPT + rjmp __vector_TIM0_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_ANA_COMP + rjmp __vector_WDT + rjmp __vector_VLM + rjmp __vector_ADC + rjmp __vector_USART_RXS + rjmp __vector_USART_RXC + rjmp __vector_USART_DRE + rjmp __vector_USART_TXC + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_TIM0_CAPT + IRQ __vector_TIM0_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_ANA_COMP + IRQ __vector_WDT + IRQ __vector_VLM + IRQ __vector_ADC + IRQ __vector_USART_RXS + IRQ __vector_USART_RXC + IRQ __vector_USART_DRE + IRQ __vector_USART_TXC diff --git a/targets/device/avr/attiny11.ld b/targets/device/avr/attiny11.ld new file mode 100644 index 00000000..02daa695 --- /dev/null +++ b/targets/device/avr/attiny11.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny11.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__ram_start = 0x0; +__ram_size = 0x0; +__num_isrs = 5; diff --git a/targets/device/avr/attiny11.s b/targets/device/avr/attiny11.s new file mode 100644 index 00000000..cbe5eb15 --- /dev/null +++ b/targets/device/avr/attiny11.s @@ -0,0 +1,34 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny11.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_IO_PINS + rjmp __vector_TIMER0_OVF + rjmp __vector_ANA_COMP + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_IO_PINS + IRQ __vector_TIMER0_OVF + IRQ __vector_ANA_COMP diff --git a/targets/device/avr/attiny12.ld b/targets/device/avr/attiny12.ld new file mode 100644 index 00000000..8d298217 --- /dev/null +++ b/targets/device/avr/attiny12.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny12.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__ram_start = 0x0; +__ram_size = 0x0; +__num_isrs = 6; diff --git a/targets/device/avr/attiny12.s b/targets/device/avr/attiny12.s new file mode 100644 index 00000000..bf8aa980 --- /dev/null +++ b/targets/device/avr/attiny12.s @@ -0,0 +1,36 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny12.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_IO_PINS + rjmp __vector_TIMER0_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_IO_PINS + IRQ __vector_TIMER0_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP diff --git a/targets/device/avr/attiny13.ld b/targets/device/avr/attiny13.ld new file mode 100644 index 00000000..b77e67be --- /dev/null +++ b/targets/device/avr/attiny13.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny13.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__ram_start = 0x60; +__ram_size = 0x40; +__num_isrs = 10; diff --git a/targets/device/avr/attiny13.s b/targets/device/avr/attiny13.s new file mode 100644 index 00000000..d3262d55 --- /dev/null +++ b/targets/device/avr/attiny13.s @@ -0,0 +1,44 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny13.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIM0_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_WDT + rjmp __vector_ADC + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIM0_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_WDT + IRQ __vector_ADC diff --git a/targets/device/avr/attiny13a.ld b/targets/device/avr/attiny13a.ld new file mode 100644 index 00000000..214b2527 --- /dev/null +++ b/targets/device/avr/attiny13a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny13A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__ram_start = 0x60; +__ram_size = 0x40; +__num_isrs = 10; diff --git a/targets/device/avr/attiny13a.s b/targets/device/avr/attiny13a.s new file mode 100644 index 00000000..34e4773a --- /dev/null +++ b/targets/device/avr/attiny13a.s @@ -0,0 +1,44 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny13A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIM0_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_WDT + rjmp __vector_ADC + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIM0_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_WDT + IRQ __vector_ADC diff --git a/targets/device/avr/attiny15.ld b/targets/device/avr/attiny15.ld new file mode 100644 index 00000000..f268d84f --- /dev/null +++ b/targets/device/avr/attiny15.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny15.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__ram_start = 0x0; +__ram_size = 0x0; +__num_isrs = 9; diff --git a/targets/device/avr/attiny15.s b/targets/device/avr/attiny15.s new file mode 100644 index 00000000..77dd251c --- /dev/null +++ b/targets/device/avr/attiny15.s @@ -0,0 +1,42 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny15.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_IO_PINS + rjmp __vector_TIMER1_COMP + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_IO_PINS + IRQ __vector_TIMER1_COMP + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC diff --git a/targets/device/avr/attiny1614.ld b/targets/device/avr/attiny1614.ld new file mode 100644 index 00000000..fd9441e6 --- /dev/null +++ b/targets/device/avr/attiny1614.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny1614.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3800; +__ram_size = 0x800; +__num_isrs = 34; diff --git a/targets/device/avr/attiny1614.s b/targets/device/avr/attiny1614.s new file mode 100644 index 00000000..7ec7a473 --- /dev/null +++ b/targets/device/avr/attiny1614.s @@ -0,0 +1,90 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny1614.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_CRCSCAN_NMI + jmp __vector_BOD_VLM + jmp __vector_PORTA_PORT + jmp __vector_PORTB_PORT + jmp __vector_PORTC_PORT + jmp __vector_RTC_CNT + jmp __vector_RTC_PIT + jmp __vector_TCA0_LUNF + jmp __vector_TCA0_HUNF + jmp __vector_TCA0_LCMP0 + jmp __vector_TCA0_CMP1 + jmp __vector_TCA0_CMP2 + jmp __vector_TCB0_INT + jmp __vector_TCB1_INT + jmp __vector_TCD0_OVF + jmp __vector_TCD0_TRIG + jmp __vector_AC0_AC + jmp __vector_AC1_AC + jmp __vector_AC2_AC + jmp __vector_ADC0_RESRDY + jmp __vector_ADC0_WCOMP + jmp __vector_ADC1_RESRDY + jmp __vector_ADC1_WCOMP + jmp __vector_TWI0_TWIS + jmp __vector_TWI0_TWIM + jmp __vector_SPI0_INT + jmp __vector_USART0_RXC + jmp __vector_USART0_DRE + jmp __vector_USART0_TXC + jmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCB1_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_AC1_AC + IRQ __vector_AC2_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_ADC1_RESRDY + IRQ __vector_ADC1_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny1616.ld b/targets/device/avr/attiny1616.ld new file mode 100644 index 00000000..296decc1 --- /dev/null +++ b/targets/device/avr/attiny1616.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny1616.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3800; +__ram_size = 0x800; +__num_isrs = 34; diff --git a/targets/device/avr/attiny1616.s b/targets/device/avr/attiny1616.s new file mode 100644 index 00000000..a044e210 --- /dev/null +++ b/targets/device/avr/attiny1616.s @@ -0,0 +1,90 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny1616.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_CRCSCAN_NMI + jmp __vector_BOD_VLM + jmp __vector_PORTA_PORT + jmp __vector_PORTB_PORT + jmp __vector_PORTC_PORT + jmp __vector_RTC_CNT + jmp __vector_RTC_PIT + jmp __vector_TCA0_LUNF + jmp __vector_TCA0_HUNF + jmp __vector_TCA0_LCMP0 + jmp __vector_TCA0_CMP1 + jmp __vector_TCA0_CMP2 + jmp __vector_TCB0_INT + jmp __vector_TCB1_INT + jmp __vector_TCD0_OVF + jmp __vector_TCD0_TRIG + jmp __vector_AC0_AC + jmp __vector_AC1_AC + jmp __vector_AC2_AC + jmp __vector_ADC0_RESRDY + jmp __vector_ADC0_WCOMP + jmp __vector_ADC1_RESRDY + jmp __vector_ADC1_WCOMP + jmp __vector_TWI0_TWIS + jmp __vector_TWI0_TWIM + jmp __vector_SPI0_INT + jmp __vector_USART0_RXC + jmp __vector_USART0_DRE + jmp __vector_USART0_TXC + jmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCB1_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_AC1_AC + IRQ __vector_AC2_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_ADC1_RESRDY + IRQ __vector_ADC1_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny1617.ld b/targets/device/avr/attiny1617.ld new file mode 100644 index 00000000..3f5a2e1a --- /dev/null +++ b/targets/device/avr/attiny1617.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny1617.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3800; +__ram_size = 0x800; +__num_isrs = 34; diff --git a/targets/device/avr/attiny1617.s b/targets/device/avr/attiny1617.s new file mode 100644 index 00000000..0e5c4701 --- /dev/null +++ b/targets/device/avr/attiny1617.s @@ -0,0 +1,90 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny1617.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_CRCSCAN_NMI + jmp __vector_BOD_VLM + jmp __vector_PORTA_PORT + jmp __vector_PORTB_PORT + jmp __vector_PORTC_PORT + jmp __vector_RTC_CNT + jmp __vector_RTC_PIT + jmp __vector_TCA0_LUNF + jmp __vector_TCA0_HUNF + jmp __vector_TCA0_LCMP0 + jmp __vector_TCA0_CMP1 + jmp __vector_TCA0_CMP2 + jmp __vector_TCB0_INT + jmp __vector_TCB1_INT + jmp __vector_TCD0_OVF + jmp __vector_TCD0_TRIG + jmp __vector_AC0_AC + jmp __vector_AC1_AC + jmp __vector_AC2_AC + jmp __vector_ADC0_RESRDY + jmp __vector_ADC0_WCOMP + jmp __vector_ADC1_RESRDY + jmp __vector_ADC1_WCOMP + jmp __vector_TWI0_TWIS + jmp __vector_TWI0_TWIM + jmp __vector_SPI0_INT + jmp __vector_USART0_RXC + jmp __vector_USART0_DRE + jmp __vector_USART0_TXC + jmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCB1_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_AC1_AC + IRQ __vector_AC2_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_ADC1_RESRDY + IRQ __vector_ADC1_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny1634.ld b/targets/device/avr/attiny1634.ld new file mode 100644 index 00000000..0b90ca30 --- /dev/null +++ b/targets/device/avr/attiny1634.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny1634.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 47; diff --git a/targets/device/avr/attiny1634.s b/targets/device/avr/attiny1634.s new file mode 100644 index 00000000..747fde3b --- /dev/null +++ b/targets/device/avr/attiny1634.s @@ -0,0 +1,99 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny1634.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_PCINT2 + jmp __vector_WDT + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_COMPB + jmp __vector_TIMER0_OVF + jmp __vector_ANA_COMP + jmp __vector_ADC + jmp __vector_USART0_START + jmp __vector_USART0_RX + jmp __vector_USART0_UDRE + jmp __vector_USART0_TX + jmp __vector_USART1_START + jmp __vector_USART1_RX + jmp __vector_USART1_UDRE + jmp __vector_USART1_TX + jmp __vector_USI_START + jmp __vector_USI_OVERFLOW + jmp __vector_TWI_SLAVE + jmp __vector_EE_RDY + jmp __vector_QTRIP + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIM1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIM1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIM1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIM0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIM0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_ADC_READY + IRQ __vector_USART0_START + IRQ __vector_USART0_RXS + IRQ __vector_USART0_RX + IRQ __vector_USART0_RXC + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TX + IRQ __vector_USART0_TXC + IRQ __vector_USART1_START + IRQ __vector_USART1_RXS + IRQ __vector_USART1_RX + IRQ __vector_USART1_RXC + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_DRE + IRQ __vector_USART1_TX + IRQ __vector_USART1_TXC + IRQ __vector_USI_START + IRQ __vector_USI_STR + IRQ __vector_USI_OVERFLOW + IRQ __vector_USI_OVF + IRQ __vector_TWI_SLAVE + IRQ __vector_TWI + IRQ __vector_EE_RDY + IRQ __vector_QTRIP diff --git a/targets/device/avr/attiny167.ld b/targets/device/avr/attiny167.ld new file mode 100644 index 00000000..fb114e92 --- /dev/null +++ b/targets/device/avr/attiny167.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny167.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 20; diff --git a/targets/device/avr/attiny167.s b/targets/device/avr/attiny167.s new file mode 100644 index 00000000..c6ae21ee --- /dev/null +++ b/targets/device/avr/attiny167.s @@ -0,0 +1,64 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny167.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_INT0 + jmp __vector_INT1 + jmp __vector_PCINT0 + jmp __vector_PCINT1 + jmp __vector_WDT + jmp __vector_TIMER1_CAPT + jmp __vector_TIMER1_COMPA + jmp __vector_TIMER1_COMPB + jmp __vector_TIMER1_OVF + jmp __vector_TIMER0_COMPA + jmp __vector_TIMER0_OVF + jmp __vector_LIN_TC + jmp __vector_LIN_ERR + jmp __vector_SPI_STC + jmp __vector_ADC + jmp __vector_EE_RDY + jmp __vector_ANA_COMP + jmp __vector_USI_START + jmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_OVF + IRQ __vector_LIN_TC + IRQ __vector_LIN_ERR + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_USI_START + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny20.ld b/targets/device/avr/attiny20.ld new file mode 100644 index 00000000..a76ce0af --- /dev/null +++ b/targets/device/avr/attiny20.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny20.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__mapped_flash_start = 0x4000; +__ram_start = 0x40; +__ram_size = 0x80; +__num_isrs = 17; diff --git a/targets/device/avr/attiny20.s b/targets/device/avr/attiny20.s new file mode 100644 index 00000000..b105d024 --- /dev/null +++ b/targets/device/avr/attiny20.s @@ -0,0 +1,58 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny20.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIM1_CAPT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC_ADC + rjmp __vector_TWI_SLAVE + rjmp __vector_SPI + rjmp __vector_QTRIP + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC_ADC + IRQ __vector_TWI_SLAVE + IRQ __vector_SPI + IRQ __vector_QTRIP diff --git a/targets/device/avr/attiny212.ld b/targets/device/avr/attiny212.ld new file mode 100644 index 00000000..6c05eb5e --- /dev/null +++ b/targets/device/avr/attiny212.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny212.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__mapped_flash_start = 0x8000; +__ram_start = 0x3f80; +__ram_size = 0x80; +__num_isrs = 27; diff --git a/targets/device/avr/attiny212.s b/targets/device/avr/attiny212.s new file mode 100644 index 00000000..d5076436 --- /dev/null +++ b/targets/device/avr/attiny212.s @@ -0,0 +1,78 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny212.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_default + rjmp __vector_default + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_CMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny214.ld b/targets/device/avr/attiny214.ld new file mode 100644 index 00000000..b9045a99 --- /dev/null +++ b/targets/device/avr/attiny214.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny214.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__mapped_flash_start = 0x8000; +__ram_start = 0x3f80; +__ram_size = 0x80; +__num_isrs = 28; diff --git a/targets/device/avr/attiny214.s b/targets/device/avr/attiny214.s new file mode 100644 index 00000000..72e5c3b8 --- /dev/null +++ b/targets/device/avr/attiny214.s @@ -0,0 +1,79 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny214.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_PORTB_PORT + rjmp __vector_default + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_CMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny2313.ld b/targets/device/avr/attiny2313.ld new file mode 100644 index 00000000..b6e9a53c --- /dev/null +++ b/targets/device/avr/attiny2313.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny2313.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__ram_start = 0x60; +__ram_size = 0x80; +__num_isrs = 19; diff --git a/targets/device/avr/attiny2313.s b/targets/device/avr/attiny2313.s new file mode 100644 index 00000000..2fa233b8 --- /dev/null +++ b/targets/device/avr/attiny2313.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny2313.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ANA_COMP + rjmp __vector_PCINT + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_USI_START + rjmp __vector_USI_OVERFLOW + rjmp __vector_EEPROM_Ready + rjmp __vector_WDT_OVERFLOW + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ANA_COMP + IRQ __vector_PCINT + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_EEPROM_Ready + IRQ __vector_WDT_OVERFLOW diff --git a/targets/device/avr/attiny2313a.ld b/targets/device/avr/attiny2313a.ld new file mode 100644 index 00000000..345ae9cb --- /dev/null +++ b/targets/device/avr/attiny2313a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny2313A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__ram_start = 0x60; +__ram_size = 0x80; +__num_isrs = 21; diff --git a/targets/device/avr/attiny2313a.s b/targets/device/avr/attiny2313a.s new file mode 100644 index 00000000..b61172ed --- /dev/null +++ b/targets/device/avr/attiny2313a.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny2313A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ANA_COMP + rjmp __vector_PCINT_B + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_USI_START + rjmp __vector_USI_OVERFLOW + rjmp __vector_EEPROM_Ready + rjmp __vector_WDT_OVERFLOW + rjmp __vector_PCINT_A + rjmp __vector_PCINT_D + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ANA_COMP + IRQ __vector_PCINT_B + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_EEPROM_Ready + IRQ __vector_WDT_OVERFLOW + IRQ __vector_PCINT_A + IRQ __vector_PCINT_D diff --git a/targets/device/avr/attiny24.ld b/targets/device/avr/attiny24.ld new file mode 100644 index 00000000..63b24efd --- /dev/null +++ b/targets/device/avr/attiny24.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny24.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__ram_start = 0x60; +__ram_size = 0x80; +__num_isrs = 17; diff --git a/targets/device/avr/attiny24.s b/targets/device/avr/attiny24.s new file mode 100644 index 00000000..9bb2f4b2 --- /dev/null +++ b/targets/device/avr/attiny24.s @@ -0,0 +1,58 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny24.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_EXT_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIM1_CAPT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_USI_STR + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_EXT_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_USI_STR + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny24a.ld b/targets/device/avr/attiny24a.ld new file mode 100644 index 00000000..0de99de8 --- /dev/null +++ b/targets/device/avr/attiny24a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny24A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__ram_start = 0x60; +__ram_size = 0x80; +__num_isrs = 17; diff --git a/targets/device/avr/attiny24a.s b/targets/device/avr/attiny24a.s new file mode 100644 index 00000000..8c04b876 --- /dev/null +++ b/targets/device/avr/attiny24a.s @@ -0,0 +1,58 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny24A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_EXT_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIM1_CAPT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_USI_STR + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_EXT_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_USI_STR + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny25.ld b/targets/device/avr/attiny25.ld new file mode 100644 index 00000000..3c7aa242 --- /dev/null +++ b/targets/device/avr/attiny25.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny25.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__ram_start = 0x60; +__ram_size = 0x80; +__num_isrs = 15; diff --git a/targets/device/avr/attiny25.s b/targets/device/avr/attiny25.s new file mode 100644 index 00000000..7c3e7236 --- /dev/null +++ b/targets/device/avr/attiny25.s @@ -0,0 +1,54 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny25.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_WDT + rjmp __vector_USI_START + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_WDT + IRQ __vector_USI_START + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny26.ld b/targets/device/avr/attiny26.ld new file mode 100644 index 00000000..52a76994 --- /dev/null +++ b/targets/device/avr/attiny26.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny26.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__ram_start = 0x60; +__ram_size = 0x80; +__num_isrs = 12; diff --git a/targets/device/avr/attiny26.s b/targets/device/avr/attiny26.s new file mode 100644 index 00000000..b3c9c4c1 --- /dev/null +++ b/targets/device/avr/attiny26.s @@ -0,0 +1,48 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny26.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_IO_PINS + rjmp __vector_TIMER1_CMPA + rjmp __vector_TIMER1_CMPB + rjmp __vector_TIMER1_OVF1 + rjmp __vector_TIMER0_OVF0 + rjmp __vector_USI_STRT + rjmp __vector_USI_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_IO_PINS + IRQ __vector_TIMER1_CMPA + IRQ __vector_TIMER1_CMPB + IRQ __vector_TIMER1_OVF1 + IRQ __vector_TIMER0_OVF0 + IRQ __vector_USI_STRT + IRQ __vector_USI_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC diff --git a/targets/device/avr/attiny261.ld b/targets/device/avr/attiny261.ld new file mode 100644 index 00000000..e1098fc5 --- /dev/null +++ b/targets/device/avr/attiny261.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny261.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__ram_start = 0x60; +__ram_size = 0x80; +__num_isrs = 19; diff --git a/targets/device/avr/attiny261.s b/targets/device/avr/attiny261.s new file mode 100644 index 00000000..5fea0cbe --- /dev/null +++ b/targets/device/avr/attiny261.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny261.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USI_START + rjmp __vector_USI_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_WDT + rjmp __vector_INT1 + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_CAPT + rjmp __vector_TIMER1_COMPD + rjmp __vector_FAULT_PROTECTION + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USI_START + IRQ __vector_USI_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_INT1 + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_CAPT + IRQ __vector_TIMER1_COMPD + IRQ __vector_FAULT_PROTECTION diff --git a/targets/device/avr/attiny261a.ld b/targets/device/avr/attiny261a.ld new file mode 100644 index 00000000..00a402a0 --- /dev/null +++ b/targets/device/avr/attiny261a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny261A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x800; +__ram_start = 0x60; +__ram_size = 0x80; +__num_isrs = 19; diff --git a/targets/device/avr/attiny261a.s b/targets/device/avr/attiny261a.s new file mode 100644 index 00000000..9fc1e8bc --- /dev/null +++ b/targets/device/avr/attiny261a.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny261A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USI_START + rjmp __vector_USI_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_WDT + rjmp __vector_INT1 + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_CAPT + rjmp __vector_TIMER1_COMPD + rjmp __vector_FAULT_PROTECTION + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USI_START + IRQ __vector_USI_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_INT1 + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_CAPT + IRQ __vector_TIMER1_COMPD + IRQ __vector_FAULT_PROTECTION diff --git a/targets/device/avr/attiny3214.ld b/targets/device/avr/attiny3214.ld new file mode 100644 index 00000000..6cccd2aa --- /dev/null +++ b/targets/device/avr/attiny3214.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny3214.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3800; +__ram_size = 0x800; +__num_isrs = 34; diff --git a/targets/device/avr/attiny3214.s b/targets/device/avr/attiny3214.s new file mode 100644 index 00000000..f920fdbd --- /dev/null +++ b/targets/device/avr/attiny3214.s @@ -0,0 +1,90 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny3214.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_CRCSCAN_NMI + jmp __vector_BOD_VLM + jmp __vector_PORTA_PORT + jmp __vector_PORTB_PORT + jmp __vector_PORTC_PORT + jmp __vector_RTC_CNT + jmp __vector_RTC_PIT + jmp __vector_TCA0_LUNF + jmp __vector_TCA0_HUNF + jmp __vector_TCA0_LCMP0 + jmp __vector_TCA0_LCMP1 + jmp __vector_TCA0_CMP2 + jmp __vector_TCB0_INT + jmp __vector_TCB1_INT + jmp __vector_TCD0_OVF + jmp __vector_TCD0_TRIG + jmp __vector_AC0_AC + jmp __vector_AC1_AC + jmp __vector_AC2_AC + jmp __vector_ADC0_RESRDY + jmp __vector_ADC0_WCOMP + jmp __vector_ADC1_RESRDY + jmp __vector_ADC1_WCOMP + jmp __vector_TWI0_TWIS + jmp __vector_TWI0_TWIM + jmp __vector_SPI0_INT + jmp __vector_USART0_RXC + jmp __vector_USART0_DRE + jmp __vector_USART0_TXC + jmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCB1_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_AC1_AC + IRQ __vector_AC2_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_ADC1_RESRDY + IRQ __vector_ADC1_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny3216.ld b/targets/device/avr/attiny3216.ld new file mode 100644 index 00000000..51d8f1b1 --- /dev/null +++ b/targets/device/avr/attiny3216.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny3216.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3800; +__ram_size = 0x800; +__num_isrs = 34; diff --git a/targets/device/avr/attiny3216.s b/targets/device/avr/attiny3216.s new file mode 100644 index 00000000..c83e1a82 --- /dev/null +++ b/targets/device/avr/attiny3216.s @@ -0,0 +1,90 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny3216.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_CRCSCAN_NMI + jmp __vector_BOD_VLM + jmp __vector_PORTA_PORT + jmp __vector_PORTB_PORT + jmp __vector_PORTC_PORT + jmp __vector_RTC_CNT + jmp __vector_RTC_PIT + jmp __vector_TCA0_LUNF + jmp __vector_TCA0_HUNF + jmp __vector_TCA0_LCMP0 + jmp __vector_TCA0_CMP1 + jmp __vector_TCA0_CMP2 + jmp __vector_TCB0_INT + jmp __vector_TCB1_INT + jmp __vector_TCD0_OVF + jmp __vector_TCD0_TRIG + jmp __vector_AC0_AC + jmp __vector_AC1_AC + jmp __vector_AC2_AC + jmp __vector_ADC0_RESRDY + jmp __vector_ADC0_WCOMP + jmp __vector_ADC1_RESRDY + jmp __vector_ADC1_WCOMP + jmp __vector_TWI0_TWIS + jmp __vector_TWI0_TWIM + jmp __vector_SPI0_INT + jmp __vector_USART0_RXC + jmp __vector_USART0_DRE + jmp __vector_USART0_TXC + jmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCB1_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_AC1_AC + IRQ __vector_AC2_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_ADC1_RESRDY + IRQ __vector_ADC1_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny3217.ld b/targets/device/avr/attiny3217.ld new file mode 100644 index 00000000..a4583856 --- /dev/null +++ b/targets/device/avr/attiny3217.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny3217.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3800; +__ram_size = 0x800; +__num_isrs = 34; diff --git a/targets/device/avr/attiny3217.s b/targets/device/avr/attiny3217.s new file mode 100644 index 00000000..aa2432a4 --- /dev/null +++ b/targets/device/avr/attiny3217.s @@ -0,0 +1,90 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny3217.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + jmp __vector_RESET + jmp __vector_CRCSCAN_NMI + jmp __vector_BOD_VLM + jmp __vector_PORTA_PORT + jmp __vector_PORTB_PORT + jmp __vector_PORTC_PORT + jmp __vector_RTC_CNT + jmp __vector_RTC_PIT + jmp __vector_TCA0_LUNF + jmp __vector_TCA0_HUNF + jmp __vector_TCA0_LCMP0 + jmp __vector_TCA0_CMP1 + jmp __vector_TCA0_CMP2 + jmp __vector_TCB0_INT + jmp __vector_TCB1_INT + jmp __vector_TCD0_OVF + jmp __vector_TCD0_TRIG + jmp __vector_AC0_AC + jmp __vector_AC1_AC + jmp __vector_AC2_AC + jmp __vector_ADC0_RESRDY + jmp __vector_ADC0_WCOMP + jmp __vector_ADC1_RESRDY + jmp __vector_ADC1_WCOMP + jmp __vector_TWI0_TWIS + jmp __vector_TWI0_TWIM + jmp __vector_SPI0_INT + jmp __vector_USART0_RXC + jmp __vector_USART0_DRE + jmp __vector_USART0_TXC + jmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCB1_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_AC1_AC + IRQ __vector_AC2_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_ADC1_RESRDY + IRQ __vector_ADC1_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny4.ld b/targets/device/avr/attiny4.ld new file mode 100644 index 00000000..ae1d21cc --- /dev/null +++ b/targets/device/avr/attiny4.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny4.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x200; +__mapped_flash_start = 0x4000; +__ram_start = 0x40; +__ram_size = 0x20; +__num_isrs = 10; diff --git a/targets/device/avr/attiny4.s b/targets/device/avr/attiny4.s new file mode 100644 index 00000000..e8c53ae8 --- /dev/null +++ b/targets/device/avr/attiny4.s @@ -0,0 +1,44 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny4.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIM0_CAPT + rjmp __vector_TIM0_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_ANA_COMP + rjmp __vector_WDT + rjmp __vector_VLM + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIM0_CAPT + IRQ __vector_TIM0_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_ANA_COMP + IRQ __vector_WDT + IRQ __vector_VLM diff --git a/targets/device/avr/attiny40.ld b/targets/device/avr/attiny40.ld new file mode 100644 index 00000000..4b48f62b --- /dev/null +++ b/targets/device/avr/attiny40.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny40.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__mapped_flash_start = 0x4000; +__ram_start = 0x40; +__ram_size = 0x100; +__num_isrs = 18; diff --git a/targets/device/avr/attiny40.s b/targets/device/avr/attiny40.s new file mode 100644 index 00000000..55b111f0 --- /dev/null +++ b/targets/device/avr/attiny40.s @@ -0,0 +1,60 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny40.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIM1_CAPT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_TWI_SLAVE + rjmp __vector_SPI + rjmp __vector_QTRIP + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_TWI_SLAVE + IRQ __vector_SPI + IRQ __vector_QTRIP diff --git a/targets/device/avr/attiny412.ld b/targets/device/avr/attiny412.ld new file mode 100644 index 00000000..17fe0215 --- /dev/null +++ b/targets/device/avr/attiny412.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny412.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3f00; +__ram_size = 0x100; +__num_isrs = 27; diff --git a/targets/device/avr/attiny412.s b/targets/device/avr/attiny412.s new file mode 100644 index 00000000..1605c8d8 --- /dev/null +++ b/targets/device/avr/attiny412.s @@ -0,0 +1,78 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny412.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_default + rjmp __vector_default + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_CMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny414.ld b/targets/device/avr/attiny414.ld new file mode 100644 index 00000000..487e3727 --- /dev/null +++ b/targets/device/avr/attiny414.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny414.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3f00; +__ram_size = 0x100; +__num_isrs = 28; diff --git a/targets/device/avr/attiny414.s b/targets/device/avr/attiny414.s new file mode 100644 index 00000000..af154188 --- /dev/null +++ b/targets/device/avr/attiny414.s @@ -0,0 +1,79 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny414.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_PORTB_PORT + rjmp __vector_default + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_CMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny416.ld b/targets/device/avr/attiny416.ld new file mode 100644 index 00000000..0ddccd2d --- /dev/null +++ b/targets/device/avr/attiny416.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny416.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3f00; +__ram_size = 0x100; +__num_isrs = 29; diff --git a/targets/device/avr/attiny416.s b/targets/device/avr/attiny416.s new file mode 100644 index 00000000..88d47f49 --- /dev/null +++ b/targets/device/avr/attiny416.s @@ -0,0 +1,80 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny416.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_PORTB_PORT + rjmp __vector_PORTC_PORT + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_CMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny417.ld b/targets/device/avr/attiny417.ld new file mode 100644 index 00000000..97d5ef20 --- /dev/null +++ b/targets/device/avr/attiny417.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny417.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3f00; +__ram_size = 0x100; +__num_isrs = 29; diff --git a/targets/device/avr/attiny417.s b/targets/device/avr/attiny417.s new file mode 100644 index 00000000..dd7a3c12 --- /dev/null +++ b/targets/device/avr/attiny417.s @@ -0,0 +1,80 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny417.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_PORTB_PORT + rjmp __vector_PORTC_PORT + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_CMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny4313.ld b/targets/device/avr/attiny4313.ld new file mode 100644 index 00000000..042e60c0 --- /dev/null +++ b/targets/device/avr/attiny4313.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny4313.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x60; +__ram_size = 0x100; +__num_isrs = 21; diff --git a/targets/device/avr/attiny4313.s b/targets/device/avr/attiny4313.s new file mode 100644 index 00000000..21981db7 --- /dev/null +++ b/targets/device/avr/attiny4313.s @@ -0,0 +1,66 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny4313.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ANA_COMP + rjmp __vector_PCINT_B + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_USI_START + rjmp __vector_USI_OVERFLOW + rjmp __vector_EEPROM_Ready + rjmp __vector_WDT_OVERFLOW + rjmp __vector_PCINT_A + rjmp __vector_PCINT_D + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ANA_COMP + IRQ __vector_PCINT_B + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_USI_START + IRQ __vector_USI_OVERFLOW + IRQ __vector_EEPROM_Ready + IRQ __vector_WDT_OVERFLOW + IRQ __vector_PCINT_A + IRQ __vector_PCINT_D diff --git a/targets/device/avr/attiny43u.ld b/targets/device/avr/attiny43u.ld new file mode 100644 index 00000000..5dfe1c0a --- /dev/null +++ b/targets/device/avr/attiny43u.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny43U.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x60; +__ram_size = 0x100; +__num_isrs = 16; diff --git a/targets/device/avr/attiny43u.s b/targets/device/avr/attiny43u.s new file mode 100644 index 00000000..6b2bc46a --- /dev/null +++ b/targets/device/avr/attiny43u.s @@ -0,0 +1,56 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny43U.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_USI_START + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_USI_START + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny44.ld b/targets/device/avr/attiny44.ld new file mode 100644 index 00000000..ced98d04 --- /dev/null +++ b/targets/device/avr/attiny44.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny44.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x60; +__ram_size = 0x100; +__num_isrs = 17; diff --git a/targets/device/avr/attiny44.s b/targets/device/avr/attiny44.s new file mode 100644 index 00000000..b6dcbe73 --- /dev/null +++ b/targets/device/avr/attiny44.s @@ -0,0 +1,58 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny44.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_EXT_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIM1_CAPT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_USI_STR + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_EXT_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_USI_STR + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny441.ld b/targets/device/avr/attiny441.ld new file mode 100644 index 00000000..9858d573 --- /dev/null +++ b/targets/device/avr/attiny441.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny441.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x100; +__ram_size = 0x100; +__num_isrs = 30; diff --git a/targets/device/avr/attiny441.s b/targets/device/avr/attiny441.s new file mode 100644 index 00000000..397fa7bf --- /dev/null +++ b/targets/device/avr/attiny441.s @@ -0,0 +1,84 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny441.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_ANA_COMP0 + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP1 + rjmp __vector_TIMER2_CAPT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_SPI + rjmp __vector_USART0_START + rjmp __vector_USART0_RX + rjmp __vector_USART0_UDRE + rjmp __vector_USART0_TX + rjmp __vector_USART1_START + rjmp __vector_USART1_RX + rjmp __vector_USART1_UDRE + rjmp __vector_USART1_TX + rjmp __vector_TWI_SLAVE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_ANA_COMP0 + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP1 + IRQ __vector_TIMER2_CAPT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_SPI + IRQ __vector_USART0_START + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USART1_START + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI_SLAVE diff --git a/targets/device/avr/attiny44a.ld b/targets/device/avr/attiny44a.ld new file mode 100644 index 00000000..5a421a96 --- /dev/null +++ b/targets/device/avr/attiny44a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny44A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x60; +__ram_size = 0x100; +__num_isrs = 17; diff --git a/targets/device/avr/attiny44a.s b/targets/device/avr/attiny44a.s new file mode 100644 index 00000000..ab7e18da --- /dev/null +++ b/targets/device/avr/attiny44a.s @@ -0,0 +1,58 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny44A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_EXT_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIM1_CAPT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_USI_STR + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_EXT_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_USI_STR + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny45.ld b/targets/device/avr/attiny45.ld new file mode 100644 index 00000000..e81bf54e --- /dev/null +++ b/targets/device/avr/attiny45.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny45.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x60; +__ram_size = 0x100; +__num_isrs = 15; diff --git a/targets/device/avr/attiny45.s b/targets/device/avr/attiny45.s new file mode 100644 index 00000000..7e20d709 --- /dev/null +++ b/targets/device/avr/attiny45.s @@ -0,0 +1,54 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny45.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_WDT + rjmp __vector_USI_START + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_WDT + IRQ __vector_USI_START + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny461.ld b/targets/device/avr/attiny461.ld new file mode 100644 index 00000000..d85b9680 --- /dev/null +++ b/targets/device/avr/attiny461.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny461.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x60; +__ram_size = 0x100; +__num_isrs = 19; diff --git a/targets/device/avr/attiny461.s b/targets/device/avr/attiny461.s new file mode 100644 index 00000000..031fd50e --- /dev/null +++ b/targets/device/avr/attiny461.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny461.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USI_START + rjmp __vector_USI_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_WDT + rjmp __vector_INT1 + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_CAPT + rjmp __vector_TIMER1_COMPD + rjmp __vector_FAULT_PROTECTION + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USI_START + IRQ __vector_USI_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_INT1 + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_CAPT + IRQ __vector_TIMER1_COMPD + IRQ __vector_FAULT_PROTECTION diff --git a/targets/device/avr/attiny461a.ld b/targets/device/avr/attiny461a.ld new file mode 100644 index 00000000..c9338eb9 --- /dev/null +++ b/targets/device/avr/attiny461a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny461A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x60; +__ram_size = 0x100; +__num_isrs = 19; diff --git a/targets/device/avr/attiny461a.s b/targets/device/avr/attiny461a.s new file mode 100644 index 00000000..b85f7f3e --- /dev/null +++ b/targets/device/avr/attiny461a.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny461A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USI_START + rjmp __vector_USI_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_WDT + rjmp __vector_INT1 + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_CAPT + rjmp __vector_TIMER1_COMPD + rjmp __vector_FAULT_PROTECTION + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USI_START + IRQ __vector_USI_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_INT1 + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_CAPT + IRQ __vector_TIMER1_COMPD + IRQ __vector_FAULT_PROTECTION diff --git a/targets/device/avr/attiny48.ld b/targets/device/avr/attiny48.ld new file mode 100644 index 00000000..ae0b1b52 --- /dev/null +++ b/targets/device/avr/attiny48.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny48.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_start = 0x100; +__ram_size = 0x100; +__num_isrs = 20; diff --git a/targets/device/avr/attiny48.s b/targets/device/avr/attiny48.s new file mode 100644 index 00000000..1e96d274 --- /dev/null +++ b/targets/device/avr/attiny48.s @@ -0,0 +1,64 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny48.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_PCINT3 + rjmp __vector_WDT + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI diff --git a/targets/device/avr/attiny5.ld b/targets/device/avr/attiny5.ld new file mode 100644 index 00000000..41cc19ae --- /dev/null +++ b/targets/device/avr/attiny5.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny5.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x200; +__mapped_flash_start = 0x4000; +__ram_start = 0x40; +__ram_size = 0x20; +__num_isrs = 11; diff --git a/targets/device/avr/attiny5.s b/targets/device/avr/attiny5.s new file mode 100644 index 00000000..007448eb --- /dev/null +++ b/targets/device/avr/attiny5.s @@ -0,0 +1,46 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny5.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIM0_CAPT + rjmp __vector_TIM0_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_ANA_COMP + rjmp __vector_WDT + rjmp __vector_VLM + rjmp __vector_ADC + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIM0_CAPT + IRQ __vector_TIM0_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_ANA_COMP + IRQ __vector_WDT + IRQ __vector_VLM + IRQ __vector_ADC diff --git a/targets/device/avr/attiny80.ld b/targets/device/avr/attiny80.ld new file mode 100644 index 00000000..8da4071a --- /dev/null +++ b/targets/device/avr/attiny80.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny80.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/targets/device/avr/attiny80.s b/targets/device/avr/attiny80.s new file mode 100644 index 00000000..56409d5b --- /dev/null +++ b/targets/device/avr/attiny80.s @@ -0,0 +1,94 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny80.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_default + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_default + rjmp __vector_default + rjmp __vector_default + rjmp __vector_CLI + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_default + rjmp __vector_SPM_Ready + rjmp __vector_default + rjmp __vector_default + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_USART_START + rjmp __vector_TIMER3_CAPT + rjmp __vector_TIMER3_COMPA + rjmp __vector_TIMER3_COMPB + rjmp __vector_TIMER3_OVF + rjmp __vector_default + rjmp __vector_PTC_EOC + rjmp __vector_PTC_WCOMP + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_CLI + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_SPM_Ready + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_USART_START + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_OVF + IRQ __vector_PTC_EOC + IRQ __vector_PTC_WCOMP diff --git a/targets/device/avr/attiny814.ld b/targets/device/avr/attiny814.ld new file mode 100644 index 00000000..aa26cd42 --- /dev/null +++ b/targets/device/avr/attiny814.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny814.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3e00; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/targets/device/avr/attiny814.s b/targets/device/avr/attiny814.s new file mode 100644 index 00000000..471ef175 --- /dev/null +++ b/targets/device/avr/attiny814.s @@ -0,0 +1,80 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny814.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_PORTB_PORT + rjmp __vector_PORTC_PORT + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_CMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny816.ld b/targets/device/avr/attiny816.ld new file mode 100644 index 00000000..a85be201 --- /dev/null +++ b/targets/device/avr/attiny816.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny816.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3e00; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/targets/device/avr/attiny816.s b/targets/device/avr/attiny816.s new file mode 100644 index 00000000..fd029ada --- /dev/null +++ b/targets/device/avr/attiny816.s @@ -0,0 +1,80 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny816.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_PORTB_PORT + rjmp __vector_PORTC_PORT + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_CMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny817.ld b/targets/device/avr/attiny817.ld new file mode 100644 index 00000000..946cc03b --- /dev/null +++ b/targets/device/avr/attiny817.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny817.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__mapped_flash_start = 0x8000; +__ram_start = 0x3e00; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/targets/device/avr/attiny817.s b/targets/device/avr/attiny817.s new file mode 100644 index 00000000..52d187a2 --- /dev/null +++ b/targets/device/avr/attiny817.s @@ -0,0 +1,80 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny817.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_CRCSCAN_NMI + rjmp __vector_BOD_VLM + rjmp __vector_PORTA_PORT + rjmp __vector_PORTB_PORT + rjmp __vector_PORTC_PORT + rjmp __vector_RTC_CNT + rjmp __vector_RTC_PIT + rjmp __vector_TCA0_LUNF + rjmp __vector_TCA0_HUNF + rjmp __vector_TCA0_LCMP0 + rjmp __vector_TCA0_CMP1 + rjmp __vector_TCA0_LCMP2 + rjmp __vector_TCB0_INT + rjmp __vector_TCD0_OVF + rjmp __vector_TCD0_TRIG + rjmp __vector_AC0_AC + rjmp __vector_ADC0_RESRDY + rjmp __vector_ADC0_WCOMP + rjmp __vector_TWI0_TWIS + rjmp __vector_TWI0_TWIM + rjmp __vector_SPI0_INT + rjmp __vector_USART0_RXC + rjmp __vector_USART0_DRE + rjmp __vector_USART0_TXC + rjmp __vector_NVMCTRL_EE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_CRCSCAN_NMI + IRQ __vector_BOD_VLM + IRQ __vector_PORTA_PORT + IRQ __vector_PORTB_PORT + IRQ __vector_PORTC_PORT + IRQ __vector_RTC_CNT + IRQ __vector_RTC_PIT + IRQ __vector_TCA0_LUNF + IRQ __vector_TCA0_OVF + IRQ __vector_TCA0_HUNF + IRQ __vector_TCA0_LCMP0 + IRQ __vector_TCA0_CMP0 + IRQ __vector_TCA0_CMP1 + IRQ __vector_TCA0_LCMP1 + IRQ __vector_TCA0_LCMP2 + IRQ __vector_TCA0_CMP2 + IRQ __vector_TCB0_INT + IRQ __vector_TCD0_OVF + IRQ __vector_TCD0_TRIG + IRQ __vector_AC0_AC + IRQ __vector_ADC0_RESRDY + IRQ __vector_ADC0_WCOMP + IRQ __vector_TWI0_TWIS + IRQ __vector_TWI0_TWIM + IRQ __vector_SPI0_INT + IRQ __vector_USART0_RXC + IRQ __vector_USART0_DRE + IRQ __vector_USART0_TXC + IRQ __vector_NVMCTRL_EE diff --git a/targets/device/avr/attiny828.ld b/targets/device/avr/attiny828.ld new file mode 100644 index 00000000..8bffb50d --- /dev/null +++ b/targets/device/avr/attiny828.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny828.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/targets/device/avr/attiny828.s b/targets/device/avr/attiny828.s new file mode 100644 index 00000000..4fe0fe5a --- /dev/null +++ b/targets/device/avr/attiny828.s @@ -0,0 +1,76 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny828.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_PCINT3 + rjmp __vector_WDT + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_USART_START + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_ADC + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI_SLAVE + rjmp __vector_SPM_Ready + rjmp __vector_QTRIP + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_USART_START + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_ADC + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI_SLAVE + IRQ __vector_SPM_Ready + IRQ __vector_QTRIP diff --git a/targets/device/avr/attiny84.ld b/targets/device/avr/attiny84.ld new file mode 100644 index 00000000..aa98af5c --- /dev/null +++ b/targets/device/avr/attiny84.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny84.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x200; +__num_isrs = 17; diff --git a/targets/device/avr/attiny84.s b/targets/device/avr/attiny84.s new file mode 100644 index 00000000..8bf25c6a --- /dev/null +++ b/targets/device/avr/attiny84.s @@ -0,0 +1,58 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny84.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_EXT_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIM1_CAPT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_USI_STR + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_EXT_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_USI_STR + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny840.ld b/targets/device/avr/attiny840.ld new file mode 100644 index 00000000..fc510418 --- /dev/null +++ b/targets/device/avr/attiny840.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny840.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/targets/device/avr/attiny840.s b/targets/device/avr/attiny840.s new file mode 100644 index 00000000..659628ba --- /dev/null +++ b/targets/device/avr/attiny840.s @@ -0,0 +1,94 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny840.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_default + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_WDT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_default + rjmp __vector_default + rjmp __vector_default + rjmp __vector_CLI + rjmp __vector_EE_READY + rjmp __vector_ANALOG_COMP + rjmp __vector_default + rjmp __vector_SPM_Ready + rjmp __vector_default + rjmp __vector_default + rjmp __vector_USART_RX + rjmp __vector_USART_UDRE + rjmp __vector_USART_TX + rjmp __vector_USART_START + rjmp __vector_TIMER3_CAPT + rjmp __vector_TIMER3_COMPA + rjmp __vector_TIMER3_COMPB + rjmp __vector_TIMER3_OVF + rjmp __vector_default + rjmp __vector_PTC_EOC + rjmp __vector_PTC_WCOMP + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_WDT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_CLI + IRQ __vector_EE_READY + IRQ __vector_ANALOG_COMP + IRQ __vector_SPM_Ready + IRQ __vector_USART_RX + IRQ __vector_USART_UDRE + IRQ __vector_USART_TX + IRQ __vector_USART_START + IRQ __vector_TIMER3_CAPT + IRQ __vector_TIMER3_COMPA + IRQ __vector_TIMER3_COMPB + IRQ __vector_TIMER3_OVF + IRQ __vector_PTC_EOC + IRQ __vector_PTC_WCOMP diff --git a/targets/device/avr/attiny841.ld b/targets/device/avr/attiny841.ld new file mode 100644 index 00000000..3204cfeb --- /dev/null +++ b/targets/device/avr/attiny841.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny841.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 30; diff --git a/targets/device/avr/attiny841.s b/targets/device/avr/attiny841.s new file mode 100644 index 00000000..5b86c936 --- /dev/null +++ b/targets/device/avr/attiny841.s @@ -0,0 +1,84 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny841.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_ANA_COMP0 + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP1 + rjmp __vector_TIMER2_CAPT + rjmp __vector_TIMER2_COMPA + rjmp __vector_TIMER2_COMPB + rjmp __vector_TIMER2_OVF + rjmp __vector_SPI + rjmp __vector_USART0_START + rjmp __vector_USART0_RX + rjmp __vector_USART0_UDRE + rjmp __vector_USART0_TX + rjmp __vector_USART1_START + rjmp __vector_USART1_RX + rjmp __vector_USART1_UDRE + rjmp __vector_USART1_TX + rjmp __vector_TWI_SLAVE + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_ANA_COMP0 + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP1 + IRQ __vector_TIMER2_CAPT + IRQ __vector_TIMER2_COMPA + IRQ __vector_TIMER2_COMPB + IRQ __vector_TIMER2_OVF + IRQ __vector_SPI + IRQ __vector_USART0_START + IRQ __vector_USART0_RX + IRQ __vector_USART0_UDRE + IRQ __vector_USART0_TX + IRQ __vector_USART1_START + IRQ __vector_USART1_RX + IRQ __vector_USART1_UDRE + IRQ __vector_USART1_TX + IRQ __vector_TWI_SLAVE diff --git a/targets/device/avr/attiny84a.ld b/targets/device/avr/attiny84a.ld new file mode 100644 index 00000000..5df167e4 --- /dev/null +++ b/targets/device/avr/attiny84a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny84A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x200; +__num_isrs = 17; diff --git a/targets/device/avr/attiny84a.s b/targets/device/avr/attiny84a.s new file mode 100644 index 00000000..73e7ed74 --- /dev/null +++ b/targets/device/avr/attiny84a.s @@ -0,0 +1,58 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny84A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_EXT_INT0 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIM1_CAPT + rjmp __vector_TIM1_COMPA + rjmp __vector_TIM1_COMPB + rjmp __vector_TIM1_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_TIM0_OVF + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_USI_STR + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_EXT_INT0 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIM1_CAPT + IRQ __vector_TIM1_COMPA + IRQ __vector_TIM1_COMPB + IRQ __vector_TIM1_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_TIM0_OVF + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_USI_STR + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny85.ld b/targets/device/avr/attiny85.ld new file mode 100644 index 00000000..9873f2fb --- /dev/null +++ b/targets/device/avr/attiny85.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny85.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x200; +__num_isrs = 15; diff --git a/targets/device/avr/attiny85.s b/targets/device/avr/attiny85.s new file mode 100644 index 00000000..5eafa67d --- /dev/null +++ b/targets/device/avr/attiny85.s @@ -0,0 +1,54 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny85.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_WDT + rjmp __vector_USI_START + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_WDT + IRQ __vector_USI_START + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny861.ld b/targets/device/avr/attiny861.ld new file mode 100644 index 00000000..dc09a546 --- /dev/null +++ b/targets/device/avr/attiny861.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny861.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x200; +__num_isrs = 19; diff --git a/targets/device/avr/attiny861.s b/targets/device/avr/attiny861.s new file mode 100644 index 00000000..d44a43b5 --- /dev/null +++ b/targets/device/avr/attiny861.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny861.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USI_START + rjmp __vector_USI_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_WDT + rjmp __vector_INT1 + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_CAPT + rjmp __vector_TIMER1_COMPD + rjmp __vector_FAULT_PROTECTION + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USI_START + IRQ __vector_USI_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_INT1 + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_CAPT + IRQ __vector_TIMER1_COMPD + IRQ __vector_FAULT_PROTECTION diff --git a/targets/device/avr/attiny861a.ld b/targets/device/avr/attiny861a.ld new file mode 100644 index 00000000..df8a3507 --- /dev/null +++ b/targets/device/avr/attiny861a.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny861A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x60; +__ram_size = 0x200; +__num_isrs = 19; diff --git a/targets/device/avr/attiny861a.s b/targets/device/avr/attiny861a.s new file mode 100644 index 00000000..d0b02596 --- /dev/null +++ b/targets/device/avr/attiny861a.s @@ -0,0 +1,62 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny861A.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_OVF + rjmp __vector_USI_START + rjmp __vector_USI_OVF + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_ADC + rjmp __vector_WDT + rjmp __vector_INT1 + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_CAPT + rjmp __vector_TIMER1_COMPD + rjmp __vector_FAULT_PROTECTION + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_OVF + IRQ __vector_USI_START + IRQ __vector_USI_OVF + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_ADC + IRQ __vector_WDT + IRQ __vector_INT1 + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_CAPT + IRQ __vector_TIMER1_COMPD + IRQ __vector_FAULT_PROTECTION diff --git a/targets/device/avr/attiny87.ld b/targets/device/avr/attiny87.ld new file mode 100644 index 00000000..0d0874d4 --- /dev/null +++ b/targets/device/avr/attiny87.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny87.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 20; diff --git a/targets/device/avr/attiny87.s b/targets/device/avr/attiny87.s new file mode 100644 index 00000000..1caa4a8c --- /dev/null +++ b/targets/device/avr/attiny87.s @@ -0,0 +1,64 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny87.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_WDT + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_OVF + rjmp __vector_LIN_TC + rjmp __vector_LIN_ERR + rjmp __vector_SPI_STC + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_ANA_COMP + rjmp __vector_USI_START + rjmp __vector_USI_OVF + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_OVF + IRQ __vector_LIN_TC + IRQ __vector_LIN_ERR + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANA_COMP + IRQ __vector_USI_START + IRQ __vector_USI_OVF diff --git a/targets/device/avr/attiny88.ld b/targets/device/avr/attiny88.ld new file mode 100644 index 00000000..47fda961 --- /dev/null +++ b/targets/device/avr/attiny88.ld @@ -0,0 +1,7 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny88.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_start = 0x100; +__ram_size = 0x200; +__num_isrs = 20; diff --git a/targets/device/avr/attiny88.s b/targets/device/avr/attiny88.s new file mode 100644 index 00000000..ca34a58a --- /dev/null +++ b/targets/device/avr/attiny88.s @@ -0,0 +1,64 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny88.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_INT1 + rjmp __vector_PCINT0 + rjmp __vector_PCINT1 + rjmp __vector_PCINT2 + rjmp __vector_PCINT3 + rjmp __vector_WDT + rjmp __vector_TIMER1_CAPT + rjmp __vector_TIMER1_COMPA + rjmp __vector_TIMER1_COMPB + rjmp __vector_TIMER1_OVF + rjmp __vector_TIMER0_COMPA + rjmp __vector_TIMER0_COMPB + rjmp __vector_TIMER0_OVF + rjmp __vector_SPI_STC + rjmp __vector_ADC + rjmp __vector_EE_RDY + rjmp __vector_ANALOG_COMP + rjmp __vector_TWI + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_INT1 + IRQ __vector_PCINT0 + IRQ __vector_PCINT1 + IRQ __vector_PCINT2 + IRQ __vector_PCINT3 + IRQ __vector_WDT + IRQ __vector_TIMER1_CAPT + IRQ __vector_TIMER1_COMPA + IRQ __vector_TIMER1_COMPB + IRQ __vector_TIMER1_OVF + IRQ __vector_TIMER0_COMPA + IRQ __vector_TIMER0_COMPB + IRQ __vector_TIMER0_OVF + IRQ __vector_SPI_STC + IRQ __vector_ADC + IRQ __vector_EE_RDY + IRQ __vector_ANALOG_COMP + IRQ __vector_TWI diff --git a/targets/device/avr/attiny9.ld b/targets/device/avr/attiny9.ld new file mode 100644 index 00000000..b943a518 --- /dev/null +++ b/targets/device/avr/attiny9.ld @@ -0,0 +1,8 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device-avr.go from ATtiny9.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x400; +__mapped_flash_start = 0x4000; +__ram_start = 0x40; +__ram_size = 0x20; +__num_isrs = 10; diff --git a/targets/device/avr/attiny9.s b/targets/device/avr/attiny9.s new file mode 100644 index 00000000..3207c6bf --- /dev/null +++ b/targets/device/avr/attiny9.s @@ -0,0 +1,44 @@ +; Automatically generated file. DO NOT EDIT. +; Generated by gen-device-avr.go from ATtiny9.atdf, see http://packs.download.atmel.com/ + +; This is the default handler for interrupts, if triggered but not defined. +; Sleep inside so that an accidentally triggered interrupt won't drain the +; battery of a battery-powered device. +.section .text.__vector_default +.global __vector_default +__vector_default: + sleep + rjmp __vector_default + +; Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, __vector_default +.endm + +; The interrupt vector of this device. Must be placed at address 0 by the linker. +.section .vectors, "a", %progbits +.global __vectors + rjmp __vector_RESET + rjmp __vector_INT0 + rjmp __vector_PCINT0 + rjmp __vector_TIM0_CAPT + rjmp __vector_TIM0_OVF + rjmp __vector_TIM0_COMPA + rjmp __vector_TIM0_COMPB + rjmp __vector_ANA_COMP + rjmp __vector_WDT + rjmp __vector_VLM + + ; Define default implementations for interrupts, redirecting to + ; __vector_default when not implemented. + IRQ __vector_RESET + IRQ __vector_INT0 + IRQ __vector_PCINT0 + IRQ __vector_TIM0_CAPT + IRQ __vector_TIM0_OVF + IRQ __vector_TIM0_COMPA + IRQ __vector_TIM0_COMPB + IRQ __vector_ANA_COMP + IRQ __vector_WDT + IRQ __vector_VLM diff --git a/targets/device/esp/esp32.S b/targets/device/esp/esp32.S new file mode 100644 index 00000000..1179a2da --- /dev/null +++ b/targets/device/esp/esp32.S @@ -0,0 +1,57 @@ + +// The following definitions were copied from: +// esp-idf/components/xtensa/include/xtensa/corebits.h +#define PS_WOE_MASK 0x00040000 +#define PS_OWB_MASK 0x00000F00 +#define PS_CALLINC_MASK 0x00030000 +#define PS_WOE PS_WOE_MASK + +// Only calling it call_start_cpu0 for consistency with ESP-IDF. +.section .text.call_start_cpu0 +1: + .long _stack_top +.global call_start_cpu0 +call_start_cpu0: + // We need to set the stack pointer to a different value. This is somewhat + // complicated in the Xtensa architecture. The code below is a modified + // version of the following code: + // https://github.com/espressif/esp-idf/blob/c77c4ccf/components/xtensa/include/xt_instr_macros.h#L47 + + // Disable WOE. + rsr.ps a2 + movi a3, ~(PS_WOE_MASK) + and a2, a2, a3 + wsr.ps a2 + rsync + + // Set WINDOWSTART to 1 << WINDOWBASE. + rsr.windowbase a2 + ssl a2 + movi a2, 1 + sll a2, a2 + wsr.windowstart a2 + rsync + + // Load new stack pointer. + l32r sp, 1b + + // Re-enable WOE. + rsr.ps a2 + movi a3, PS_WOE + or a2, a2, a3 + wsr.ps a2 + rsync + + // Enable the FPU (coprocessor 0 so the lowest bit). + movi a2, 1 + wsr.cpenable a2 + rsync + + // Jump to the runtime start function written in Go. + call4 main + +.section .text.tinygo_scanCurrentStack +.global tinygo_scanCurrentStack +tinygo_scanCurrentStack: + // TODO: save callee saved registers on the stack + j tinygo_scanstack diff --git a/targets/device/esp/esp32c3.S b/targets/device/esp/esp32c3.S new file mode 100644 index 00000000..0395d73b --- /dev/null +++ b/targets/device/esp/esp32c3.S @@ -0,0 +1,67 @@ +// This is a very minimal bootloader for the ESP32-C3. It only initializes the +// flash and then continues with the generic RISC-V initialization code, which +// in turn will call runtime.main. +// It is written in assembly (and not in a higher level language) to make sure +// it is entirely loaded into IRAM and doesn't accidentally call functions +// stored in IROM. +// +// For reference, here is a nice introduction into RISC-V assembly: +// https://www.imperialviolet.org/2016/12/31/riscv.html + +.section .init +.global call_start_cpu0 +.type call_start_cpu0,@function +call_start_cpu0: + // At this point: + // - The ROM bootloader is finished and has jumped to here. + // - We're running from IRAM: both IRAM and DRAM segments have been loaded + // by the ROM bootloader. + // - We have a usable stack (but not the one we would like to use). + // - No flash mappings (MMU) are set up yet. + + // Reset MMU, see bootloader_reset_mmu in the ESP-IDF. + call Cache_Suspend_ICache + mv s0, a0 // autoload value + call Cache_Invalidate_ICache_All + call Cache_MMU_Init + + // Set up DROM from flash. + // Somehow, this also sets up IROM from flash. Not sure why, but it avoids + // the need for another such call. + // C equivalent: + // Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, 0x3C00_0000, 0, 64, 128, 0) + li a0, 0 // ext_ram: MMU_ACCESS_FLASH + li a1, 0x3C000000 // vaddr: address in the data bus + li a2, 0 // paddr: physical address in the flash chip + li a3, 64 // psize: always 64 (kilobytes) + li a4, 128 // num: pages to be set (8192K / 64K = 128) + li a5, 0 // fixed + call Cache_Dbus_MMU_Set + + // Enable the flash cache. + mv a0, s0 // restore autoload value from Cache_Suspend_ICache call + call Cache_Resume_ICache + + // Jump to generic RISC-V initialization, which initializes the stack + // pointer and globals register. It should not return. + // (It appears that the linker relaxes this jump and instead inserts the + // _start function right after here). + j _start + +.section .text.exception_vectors +.global _vector_table +.type _vector_table,@function + +_vector_table: + + .option push + .option norvc + + .rept 32 + j handleInterruptASM /* interrupt handler */ + .endr + + .option pop + +.size _vector_table, .-_vector_table + diff --git a/targets/device/esp/esp8266.S b/targets/device/esp/esp8266.S new file mode 100644 index 00000000..cffa5037 --- /dev/null +++ b/targets/device/esp/esp8266.S @@ -0,0 +1,6 @@ + +.section .text.tinygo_scanCurrentStack +.global tinygo_scanCurrentStack +tinygo_scanCurrentStack: + // TODO: save callee saved registers on the stack + j tinygo_scanstack diff --git a/targets/device/nrf/README.markdown b/targets/device/nrf/README.markdown new file mode 100644 index 00000000..4363613b --- /dev/null +++ b/targets/device/nrf/README.markdown @@ -0,0 +1,12 @@ +# Generated Go files for Nordic Semiconductors devices + +In this directory, Go register description files are stored that are generated +by `gen-device.py` from .svd files provided by Nordic. See the SVD files [over +here](https://github.com/NordicSemiconductor/nrfx/tree/master/mdk). + +The original files are provided under the 3-clause BSD license, see [this +post](https://devzone.nordicsemi.com/b/blog/posts/introducing-nordics-new-software-licensing-schemes) +for details. As the generated files transform most of the original file, I think +they should be licensed under the same license as the original files. Generated +files will contain the license statement that is included in the original SVD +files. diff --git a/targets/device/nrf/nrf51.s b/targets/device/nrf/nrf51.s new file mode 100644 index 00000000..c4b0ebbd --- /dev/null +++ b/targets/device/nrf/nrf51.s @@ -0,0 +1,153 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf51.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 Microcontroller at 16MHz CPU clock +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UART0_IRQHandler + .long SPI0_TWI0_IRQHandler + .long SPI1_TWI1_IRQHandler + .long 0 + .long GPIOTE_IRQHandler + .long ADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long LPCOMP_IRQHandler + .long SWI0_IRQHandler + .long SWI1_IRQHandler + .long SWI2_IRQHandler + .long SWI3_IRQHandler + .long SWI4_IRQHandler + .long SWI5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ POWER_CLOCK_IRQHandler + IRQ POWER_IRQHandler + IRQ CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UART0_IRQHandler + IRQ SPI0_TWI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ TWI0_IRQHandler + IRQ SPI1_TWI1_IRQHandler + IRQ SPIS1_IRQHandler + IRQ SPI1_IRQHandler + IRQ TWI1_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ ADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ AAR_IRQHandler + IRQ CCM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ LPCOMP_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf52.s b/targets/device/nrf/nrf52.s new file mode 100644 index 00000000..e34971af --- /dev/null +++ b/targets/device/nrf/nrf52.s @@ -0,0 +1,204 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf52.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .long NFCT_IRQHandler + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_EGU2_IRQHandler + .long SWI3_EGU3_IRQHandler + .long SWI4_EGU4_IRQHandler + .long SWI5_EGU5_IRQHandler + .long TIMER3_IRQHandler + .long TIMER4_IRQHandler + .long PWM0_IRQHandler + .long PDM_IRQHandler + .long 0 + .long 0 + .long MWU_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long SPIM2_SPIS2_SPI2_IRQHandler + .long RTC2_IRQHandler + .long I2S_IRQHandler + .long FPU_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ POWER_CLOCK_IRQHandler + IRQ POWER_IRQHandler + IRQ CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ UARTE0_IRQHandler + IRQ UART0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPIM0_IRQHandler + IRQ SPIS0_IRQHandler + IRQ TWIM0_IRQHandler + IRQ TWIS0_IRQHandler + IRQ SPI0_IRQHandler + IRQ TWI0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ SPIM1_IRQHandler + IRQ SPIS1_IRQHandler + IRQ TWIM1_IRQHandler + IRQ TWIS1_IRQHandler + IRQ SPI1_IRQHandler + IRQ TWI1_IRQHandler + IRQ NFCT_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ CCM_IRQHandler + IRQ AAR_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ COMP_IRQHandler + IRQ LPCOMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ SWI0_IRQHandler + IRQ EGU0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ SWI1_IRQHandler + IRQ EGU1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ SWI2_IRQHandler + IRQ EGU2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ SWI3_IRQHandler + IRQ EGU3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ SWI4_IRQHandler + IRQ EGU4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ SWI5_IRQHandler + IRQ EGU5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ TIMER4_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + IRQ MWU_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM2_IRQHandler + IRQ SPIM2_SPIS2_SPI2_IRQHandler + IRQ SPIM2_IRQHandler + IRQ SPIS2_IRQHandler + IRQ SPI2_IRQHandler + IRQ RTC2_IRQHandler + IRQ I2S_IRQHandler + IRQ FPU_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf52805.s b/targets/device/nrf/nrf52805.s new file mode 100644 index 00000000..10ab4cb5 --- /dev/null +++ b/targets/device/nrf/nrf52805.s @@ -0,0 +1,159 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf52805.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF52805 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long TWIM0_TWIS0_TWI0_IRQHandler + .long SPIM0_SPIS0_SPI0_IRQHandler + .long 0 + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long 0 + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_IRQHandler + .long SWI3_IRQHandler + .long SWI4_IRQHandler + .long SWI5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ POWER_CLOCK_IRQHandler + IRQ CLOCK_IRQHandler + IRQ POWER_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UARTE0_IRQHandler + IRQ TWIM0_TWIS0_TWI0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWIM0_IRQHandler + IRQ TWIS0_IRQHandler + IRQ SPIM0_SPIS0_SPI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPIM0_IRQHandler + IRQ SPIS0_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ AAR_IRQHandler + IRQ CCM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ EGU0_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ EGU1_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf52810.s b/targets/device/nrf/nrf52810.s new file mode 100644 index 00000000..873599ca --- /dev/null +++ b/targets/device/nrf/nrf52810.s @@ -0,0 +1,166 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf52810.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF52810 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long TWIM0_TWIS0_TWI0_IRQHandler + .long SPIM0_SPIS0_SPI0_IRQHandler + .long 0 + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_IRQHandler + .long SWI3_IRQHandler + .long SWI4_IRQHandler + .long SWI5_IRQHandler + .long 0 + .long 0 + .long PWM0_IRQHandler + .long PDM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ POWER_CLOCK_IRQHandler + IRQ CLOCK_IRQHandler + IRQ POWER_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UARTE0_IRQHandler + IRQ TWIM0_TWIS0_TWI0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWIM0_IRQHandler + IRQ TWIS0_IRQHandler + IRQ SPIM0_SPIS0_SPI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPIM0_IRQHandler + IRQ SPIS0_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ AAR_IRQHandler + IRQ CCM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ EGU0_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ EGU1_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf52811.s b/targets/device/nrf/nrf52811.s new file mode 100644 index 00000000..145b7277 --- /dev/null +++ b/targets/device/nrf/nrf52811.s @@ -0,0 +1,169 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf52811.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF52811 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + .long SPIM0_SPIS0_SPI0_IRQHandler + .long 0 + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_IRQHandler + .long SWI3_IRQHandler + .long SWI4_IRQHandler + .long SWI5_IRQHandler + .long 0 + .long 0 + .long PWM0_IRQHandler + .long PDM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ POWER_CLOCK_IRQHandler + IRQ CLOCK_IRQHandler + IRQ POWER_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UARTE0_IRQHandler + IRQ TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPIM1_IRQHandler + IRQ SPIS1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWIM0_IRQHandler + IRQ TWIS0_IRQHandler + IRQ SPIM0_SPIS0_SPI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPIM0_IRQHandler + IRQ SPIS0_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ AAR_IRQHandler + IRQ CCM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ EGU0_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ EGU1_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf52820.s b/targets/device/nrf/nrf52820.s new file mode 100644 index 00000000..f99ad45d --- /dev/null +++ b/targets/device/nrf/nrf52820.s @@ -0,0 +1,189 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf52820.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF52833 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .long 0 + .long GPIOTE_IRQHandler + .long 0 + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_EGU2_IRQHandler + .long SWI3_EGU3_IRQHandler + .long SWI4_EGU4_IRQHandler + .long SWI5_EGU5_IRQHandler + .long TIMER3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USBD_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ POWER_CLOCK_IRQHandler + IRQ CLOCK_IRQHandler + IRQ POWER_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UARTE0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPIM0_IRQHandler + IRQ SPIS0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWIM0_IRQHandler + IRQ TWIS0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPIM1_IRQHandler + IRQ SPIS1_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWIM1_IRQHandler + IRQ TWIS1_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ AAR_IRQHandler + IRQ CCM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ EGU0_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ EGU1_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ EGU2_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ EGU3_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ EGU4_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ EGU5_IRQHandler + IRQ SWI5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ USBD_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf52833.s b/targets/device/nrf/nrf52833.s new file mode 100644 index 00000000..cdab041c --- /dev/null +++ b/targets/device/nrf/nrf52833.s @@ -0,0 +1,217 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf52833.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF52833 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .long NFCT_IRQHandler + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_EGU2_IRQHandler + .long SWI3_EGU3_IRQHandler + .long SWI4_EGU4_IRQHandler + .long SWI5_EGU5_IRQHandler + .long TIMER3_IRQHandler + .long TIMER4_IRQHandler + .long PWM0_IRQHandler + .long PDM_IRQHandler + .long 0 + .long 0 + .long MWU_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long SPIM2_SPIS2_SPI2_IRQHandler + .long RTC2_IRQHandler + .long I2S_IRQHandler + .long FPU_IRQHandler + .long USBD_IRQHandler + .long UARTE1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long PWM3_IRQHandler + .long 0 + .long SPIM3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ POWER_CLOCK_IRQHandler + IRQ CLOCK_IRQHandler + IRQ POWER_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UARTE0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPIM0_IRQHandler + IRQ SPIS0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWIM0_IRQHandler + IRQ TWIS0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPIM1_IRQHandler + IRQ SPIS1_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWIM1_IRQHandler + IRQ TWIS1_IRQHandler + IRQ NFCT_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ AAR_IRQHandler + IRQ CCM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ COMP_IRQHandler + IRQ LPCOMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ EGU0_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ EGU1_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ EGU2_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ EGU3_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ EGU4_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ EGU5_IRQHandler + IRQ SWI5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ TIMER4_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + IRQ MWU_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM2_IRQHandler + IRQ SPIM2_SPIS2_SPI2_IRQHandler + IRQ SPI2_IRQHandler + IRQ SPIM2_IRQHandler + IRQ SPIS2_IRQHandler + IRQ RTC2_IRQHandler + IRQ I2S_IRQHandler + IRQ FPU_IRQHandler + IRQ USBD_IRQHandler + IRQ UARTE1_IRQHandler + IRQ PWM3_IRQHandler + IRQ SPIM3_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf52840.s b/targets/device/nrf/nrf52840.s new file mode 100644 index 00000000..32df6d58 --- /dev/null +++ b/targets/device/nrf/nrf52840.s @@ -0,0 +1,219 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf52840.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .long NFCT_IRQHandler + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_EGU2_IRQHandler + .long SWI3_EGU3_IRQHandler + .long SWI4_EGU4_IRQHandler + .long SWI5_EGU5_IRQHandler + .long TIMER3_IRQHandler + .long TIMER4_IRQHandler + .long PWM0_IRQHandler + .long PDM_IRQHandler + .long 0 + .long 0 + .long MWU_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long SPIM2_SPIS2_SPI2_IRQHandler + .long RTC2_IRQHandler + .long I2S_IRQHandler + .long FPU_IRQHandler + .long USBD_IRQHandler + .long UARTE1_IRQHandler + .long QSPI_IRQHandler + .long CRYPTOCELL_IRQHandler + .long 0 + .long 0 + .long PWM3_IRQHandler + .long 0 + .long SPIM3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ POWER_CLOCK_IRQHandler + IRQ CLOCK_IRQHandler + IRQ POWER_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UARTE0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPIM0_IRQHandler + IRQ SPIS0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWIM0_IRQHandler + IRQ TWIS0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPIM1_IRQHandler + IRQ SPIS1_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWIM1_IRQHandler + IRQ TWIS1_IRQHandler + IRQ NFCT_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ AAR_IRQHandler + IRQ CCM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ COMP_IRQHandler + IRQ LPCOMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ EGU0_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ EGU1_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ EGU2_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ EGU3_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ EGU4_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ EGU5_IRQHandler + IRQ SWI5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ TIMER4_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + IRQ MWU_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM2_IRQHandler + IRQ SPIM2_SPIS2_SPI2_IRQHandler + IRQ SPI2_IRQHandler + IRQ SPIM2_IRQHandler + IRQ SPIS2_IRQHandler + IRQ RTC2_IRQHandler + IRQ I2S_IRQHandler + IRQ FPU_IRQHandler + IRQ USBD_IRQHandler + IRQ UARTE1_IRQHandler + IRQ QSPI_IRQHandler + IRQ CRYPTOCELL_IRQHandler + IRQ PWM3_IRQHandler + IRQ SPIM3_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf5340_application.s b/targets/device/nrf/nrf5340_application.s new file mode 100644 index 00000000..46ed9fb1 --- /dev/null +++ b/targets/device/nrf/nrf5340_application.s @@ -0,0 +1,290 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf5340_application.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FPU_IRQHandler + .long CACHE_IRQHandler + .long 0 + .long SPU_IRQHandler + .long 0 + .long CLOCK_POWER_IRQHandler + .long 0 + .long 0 + .long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + .long SPIM4_IRQHandler + .long SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + .long SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + .long GPIOTE0_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long 0 + .long 0 + .long RTC0_IRQHandler + .long RTC1_IRQHandler + .long 0 + .long 0 + .long WDT0_IRQHandler + .long WDT1_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long EGU0_IRQHandler + .long EGU1_IRQHandler + .long EGU2_IRQHandler + .long EGU3_IRQHandler + .long EGU4_IRQHandler + .long EGU5_IRQHandler + .long PWM0_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long PWM3_IRQHandler + .long 0 + .long PDM0_IRQHandler + .long 0 + .long I2S0_IRQHandler + .long 0 + .long IPC_IRQHandler + .long QSPI_IRQHandler + .long 0 + .long NFCT_IRQHandler + .long 0 + .long GPIOTE1_IRQHandler + .long 0 + .long 0 + .long 0 + .long QDEC0_IRQHandler + .long QDEC1_IRQHandler + .long 0 + .long USBD_IRQHandler + .long USBREGULATOR_IRQHandler + .long 0 + .long KMU_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRYPTOCELL_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FPU_IRQHandler + IRQ FPU_NS_IRQHandler + IRQ FPU_S_IRQHandler + IRQ CACHE_IRQHandler + IRQ CACHE_S_IRQHandler + IRQ SPU_IRQHandler + IRQ SPU_S_IRQHandler + IRQ CLOCK_POWER_IRQHandler + IRQ CLOCK_NS_IRQHandler + IRQ POWER_NS_IRQHandler + IRQ CLOCK_S_IRQHandler + IRQ POWER_S_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + IRQ SPIM0_NS_IRQHandler + IRQ SPIS0_NS_IRQHandler + IRQ TWIM0_NS_IRQHandler + IRQ TWIS0_NS_IRQHandler + IRQ UARTE0_NS_IRQHandler + IRQ SPIM0_S_IRQHandler + IRQ SPIS0_S_IRQHandler + IRQ TWIM0_S_IRQHandler + IRQ TWIS0_S_IRQHandler + IRQ UARTE0_S_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + IRQ SPIM1_NS_IRQHandler + IRQ SPIS1_NS_IRQHandler + IRQ TWIM1_NS_IRQHandler + IRQ TWIS1_NS_IRQHandler + IRQ UARTE1_NS_IRQHandler + IRQ SPIM1_S_IRQHandler + IRQ SPIS1_S_IRQHandler + IRQ TWIM1_S_IRQHandler + IRQ TWIS1_S_IRQHandler + IRQ UARTE1_S_IRQHandler + IRQ SPIM4_IRQHandler + IRQ SPIM4_NS_IRQHandler + IRQ SPIM4_S_IRQHandler + IRQ SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + IRQ SPIM2_NS_IRQHandler + IRQ SPIS2_NS_IRQHandler + IRQ TWIM2_NS_IRQHandler + IRQ TWIS2_NS_IRQHandler + IRQ UARTE2_NS_IRQHandler + IRQ SPIM2_S_IRQHandler + IRQ SPIS2_S_IRQHandler + IRQ TWIM2_S_IRQHandler + IRQ TWIS2_S_IRQHandler + IRQ UARTE2_S_IRQHandler + IRQ SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + IRQ SPIM3_NS_IRQHandler + IRQ SPIS3_NS_IRQHandler + IRQ TWIM3_NS_IRQHandler + IRQ TWIS3_NS_IRQHandler + IRQ UARTE3_NS_IRQHandler + IRQ SPIM3_S_IRQHandler + IRQ SPIS3_S_IRQHandler + IRQ TWIM3_S_IRQHandler + IRQ TWIS3_S_IRQHandler + IRQ UARTE3_S_IRQHandler + IRQ GPIOTE0_IRQHandler + IRQ GPIOTE0_S_IRQHandler + IRQ SAADC_IRQHandler + IRQ SAADC_NS_IRQHandler + IRQ SAADC_S_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER0_NS_IRQHandler + IRQ TIMER0_S_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER1_NS_IRQHandler + IRQ TIMER1_S_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER2_NS_IRQHandler + IRQ TIMER2_S_IRQHandler + IRQ RTC0_IRQHandler + IRQ RTC0_NS_IRQHandler + IRQ RTC0_S_IRQHandler + IRQ RTC1_IRQHandler + IRQ RTC1_NS_IRQHandler + IRQ RTC1_S_IRQHandler + IRQ WDT0_IRQHandler + IRQ WDT0_NS_IRQHandler + IRQ WDT0_S_IRQHandler + IRQ WDT1_IRQHandler + IRQ WDT1_NS_IRQHandler + IRQ WDT1_S_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ COMP_NS_IRQHandler + IRQ LPCOMP_NS_IRQHandler + IRQ COMP_S_IRQHandler + IRQ LPCOMP_S_IRQHandler + IRQ EGU0_IRQHandler + IRQ EGU0_NS_IRQHandler + IRQ EGU0_S_IRQHandler + IRQ EGU1_IRQHandler + IRQ EGU1_NS_IRQHandler + IRQ EGU1_S_IRQHandler + IRQ EGU2_IRQHandler + IRQ EGU2_NS_IRQHandler + IRQ EGU2_S_IRQHandler + IRQ EGU3_IRQHandler + IRQ EGU3_NS_IRQHandler + IRQ EGU3_S_IRQHandler + IRQ EGU4_IRQHandler + IRQ EGU4_NS_IRQHandler + IRQ EGU4_S_IRQHandler + IRQ EGU5_IRQHandler + IRQ EGU5_NS_IRQHandler + IRQ EGU5_S_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM0_NS_IRQHandler + IRQ PWM0_S_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM1_NS_IRQHandler + IRQ PWM1_S_IRQHandler + IRQ PWM2_IRQHandler + IRQ PWM2_NS_IRQHandler + IRQ PWM2_S_IRQHandler + IRQ PWM3_IRQHandler + IRQ PWM3_NS_IRQHandler + IRQ PWM3_S_IRQHandler + IRQ PDM0_IRQHandler + IRQ PDM0_NS_IRQHandler + IRQ PDM0_S_IRQHandler + IRQ I2S0_IRQHandler + IRQ I2S0_NS_IRQHandler + IRQ I2S0_S_IRQHandler + IRQ IPC_IRQHandler + IRQ IPC_NS_IRQHandler + IRQ IPC_S_IRQHandler + IRQ QSPI_IRQHandler + IRQ QSPI_NS_IRQHandler + IRQ QSPI_S_IRQHandler + IRQ NFCT_IRQHandler + IRQ NFCT_NS_IRQHandler + IRQ NFCT_S_IRQHandler + IRQ GPIOTE1_IRQHandler + IRQ GPIOTE1_NS_IRQHandler + IRQ QDEC0_IRQHandler + IRQ QDEC0_NS_IRQHandler + IRQ QDEC0_S_IRQHandler + IRQ QDEC1_IRQHandler + IRQ QDEC1_NS_IRQHandler + IRQ QDEC1_S_IRQHandler + IRQ USBD_IRQHandler + IRQ USBD_NS_IRQHandler + IRQ USBD_S_IRQHandler + IRQ USBREGULATOR_IRQHandler + IRQ USBREGULATOR_NS_IRQHandler + IRQ USBREGULATOR_S_IRQHandler + IRQ KMU_IRQHandler + IRQ KMU_NS_IRQHandler + IRQ KMU_S_IRQHandler + IRQ CRYPTOCELL_IRQHandler + IRQ CRYPTOCELL_S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf5340_network.s b/targets/device/nrf/nrf5340_network.s new file mode 100644 index 00000000..8136ed15 --- /dev/null +++ b/targets/device/nrf/nrf5340_network.s @@ -0,0 +1,143 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf5340_network.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CLOCK_POWER_IRQHandler + .long 0 + .long 0 + .long RADIO_IRQHandler + .long RNG_IRQHandler + .long GPIOTE_IRQHandler + .long WDT_IRQHandler + .long TIMER0_IRQHandler + .long ECB_IRQHandler + .long AAR_CCM_IRQHandler + .long 0 + .long TEMP_IRQHandler + .long RTC0_IRQHandler + .long IPC_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + .long EGU0_IRQHandler + .long 0 + .long RTC1_IRQHandler + .long 0 + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long SWI0_IRQHandler + .long SWI1_IRQHandler + .long SWI2_IRQHandler + .long SWI3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ CLOCK_POWER_IRQHandler + IRQ CLOCK_NS_IRQHandler + IRQ POWER_NS_IRQHandler + IRQ RADIO_IRQHandler + IRQ RADIO_NS_IRQHandler + IRQ RNG_IRQHandler + IRQ RNG_NS_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ GPIOTE_NS_IRQHandler + IRQ WDT_IRQHandler + IRQ WDT_NS_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER0_NS_IRQHandler + IRQ ECB_IRQHandler + IRQ ECB_NS_IRQHandler + IRQ AAR_CCM_IRQHandler + IRQ AAR_NS_IRQHandler + IRQ CCM_NS_IRQHandler + IRQ TEMP_IRQHandler + IRQ TEMP_NS_IRQHandler + IRQ RTC0_IRQHandler + IRQ RTC0_NS_IRQHandler + IRQ IPC_IRQHandler + IRQ IPC_NS_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + IRQ SPIM0_NS_IRQHandler + IRQ SPIS0_NS_IRQHandler + IRQ TWIM0_NS_IRQHandler + IRQ TWIS0_NS_IRQHandler + IRQ UARTE0_NS_IRQHandler + IRQ EGU0_IRQHandler + IRQ EGU0_NS_IRQHandler + IRQ RTC1_IRQHandler + IRQ RTC1_NS_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER1_NS_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER2_NS_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI0_NS_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI1_NS_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI2_NS_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI3_NS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nrf/nrf9160.s b/targets/device/nrf/nrf9160.s new file mode 100644 index 00000000..f19ab658 --- /dev/null +++ b/targets/device/nrf/nrf9160.s @@ -0,0 +1,281 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from nrf9160.svd, see https://github.com/NordicSemiconductor/nrfx/tree/master/mdk + +/* +// nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller +*/ + +// Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of Nordic Semiconductor ASA nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long SPU_IRQHandler + .long 0 + .long CLOCK_POWER_IRQHandler + .long 0 + .long 0 + .long UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler + .long UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler + .long UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler + .long UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler + .long 0 + .long GPIOTE0_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long 0 + .long 0 + .long RTC0_IRQHandler + .long RTC1_IRQHandler + .long 0 + .long 0 + .long WDT_IRQHandler + .long 0 + .long 0 + .long EGU0_IRQHandler + .long EGU1_IRQHandler + .long EGU2_IRQHandler + .long EGU3_IRQHandler + .long EGU4_IRQHandler + .long EGU5_IRQHandler + .long PWM0_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long PWM3_IRQHandler + .long 0 + .long PDM_IRQHandler + .long 0 + .long I2S_IRQHandler + .long 0 + .long IPC_IRQHandler + .long 0 + .long FPU_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long GPIOTE1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long KMU_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRYPTOCELL_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SPU_IRQHandler + IRQ SPU_S_IRQHandler + IRQ CLOCK_POWER_IRQHandler + IRQ CLOCK_NS_IRQHandler + IRQ POWER_NS_IRQHandler + IRQ CLOCK_S_IRQHandler + IRQ POWER_S_IRQHandler + IRQ UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler + IRQ SPIM0_NS_IRQHandler + IRQ SPIS0_NS_IRQHandler + IRQ TWIM0_NS_IRQHandler + IRQ TWIS0_NS_IRQHandler + IRQ UARTE0_NS_IRQHandler + IRQ SPIM0_S_IRQHandler + IRQ SPIS0_S_IRQHandler + IRQ TWIM0_S_IRQHandler + IRQ TWIS0_S_IRQHandler + IRQ UARTE0_S_IRQHandler + IRQ UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler + IRQ SPIM1_NS_IRQHandler + IRQ SPIS1_NS_IRQHandler + IRQ TWIM1_NS_IRQHandler + IRQ TWIS1_NS_IRQHandler + IRQ UARTE1_NS_IRQHandler + IRQ SPIM1_S_IRQHandler + IRQ SPIS1_S_IRQHandler + IRQ TWIM1_S_IRQHandler + IRQ TWIS1_S_IRQHandler + IRQ UARTE1_S_IRQHandler + IRQ UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler + IRQ SPIM2_NS_IRQHandler + IRQ SPIS2_NS_IRQHandler + IRQ TWIM2_NS_IRQHandler + IRQ TWIS2_NS_IRQHandler + IRQ UARTE2_NS_IRQHandler + IRQ SPIM2_S_IRQHandler + IRQ SPIS2_S_IRQHandler + IRQ TWIM2_S_IRQHandler + IRQ TWIS2_S_IRQHandler + IRQ UARTE2_S_IRQHandler + IRQ UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler + IRQ SPIM3_NS_IRQHandler + IRQ SPIS3_NS_IRQHandler + IRQ TWIM3_NS_IRQHandler + IRQ TWIS3_NS_IRQHandler + IRQ UARTE3_NS_IRQHandler + IRQ SPIM3_S_IRQHandler + IRQ SPIS3_S_IRQHandler + IRQ TWIM3_S_IRQHandler + IRQ TWIS3_S_IRQHandler + IRQ UARTE3_S_IRQHandler + IRQ GPIOTE0_IRQHandler + IRQ GPIOTE0_S_IRQHandler + IRQ SAADC_IRQHandler + IRQ SAADC_NS_IRQHandler + IRQ SAADC_S_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER0_NS_IRQHandler + IRQ TIMER0_S_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER1_NS_IRQHandler + IRQ TIMER1_S_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER2_NS_IRQHandler + IRQ TIMER2_S_IRQHandler + IRQ RTC0_IRQHandler + IRQ RTC0_NS_IRQHandler + IRQ RTC0_S_IRQHandler + IRQ RTC1_IRQHandler + IRQ RTC1_NS_IRQHandler + IRQ RTC1_S_IRQHandler + IRQ WDT_IRQHandler + IRQ WDT_NS_IRQHandler + IRQ WDT_S_IRQHandler + IRQ EGU0_IRQHandler + IRQ EGU0_NS_IRQHandler + IRQ EGU0_S_IRQHandler + IRQ EGU1_IRQHandler + IRQ EGU1_NS_IRQHandler + IRQ EGU1_S_IRQHandler + IRQ EGU2_IRQHandler + IRQ EGU2_NS_IRQHandler + IRQ EGU2_S_IRQHandler + IRQ EGU3_IRQHandler + IRQ EGU3_NS_IRQHandler + IRQ EGU3_S_IRQHandler + IRQ EGU4_IRQHandler + IRQ EGU4_NS_IRQHandler + IRQ EGU4_S_IRQHandler + IRQ EGU5_IRQHandler + IRQ EGU5_NS_IRQHandler + IRQ EGU5_S_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM0_NS_IRQHandler + IRQ PWM0_S_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM1_NS_IRQHandler + IRQ PWM1_S_IRQHandler + IRQ PWM2_IRQHandler + IRQ PWM2_NS_IRQHandler + IRQ PWM2_S_IRQHandler + IRQ PWM3_IRQHandler + IRQ PWM3_NS_IRQHandler + IRQ PWM3_S_IRQHandler + IRQ PDM_IRQHandler + IRQ PDM_NS_IRQHandler + IRQ PDM_S_IRQHandler + IRQ I2S_IRQHandler + IRQ I2S_NS_IRQHandler + IRQ I2S_S_IRQHandler + IRQ IPC_IRQHandler + IRQ IPC_NS_IRQHandler + IRQ IPC_S_IRQHandler + IRQ FPU_IRQHandler + IRQ FPU_NS_IRQHandler + IRQ FPU_S_IRQHandler + IRQ GPIOTE1_IRQHandler + IRQ GPIOTE1_NS_IRQHandler + IRQ KMU_IRQHandler + IRQ KMU_NS_IRQHandler + IRQ KMU_S_IRQHandler + IRQ CRYPTOCELL_IRQHandler + IRQ CRYPTOCELL_S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc1102_04.s b/targets/device/nxp/lpc1102_04.s new file mode 100644 index 00000000..1f95c532 --- /dev/null +++ b/targets/device/nxp/lpc1102_04.s @@ -0,0 +1,117 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC1102_4_v4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC1102/04 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIO0_0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PIO0_8_IRQHandler + .long PIO0_9_IRQHandler + .long PIO0_10_IRQHandler + .long PIO0_11_IRQHandler + .long PIO1_0_IRQHandler + .long 0 + .long 0 + .long 0 + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SPI0_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long WDT_IRQHandler + .long BOD_IRQHandler + .long FMC_IRQHandler + .long 0 + .long 0 + .long GPIO1_IRQHandler + .long GPIO0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIO0_0_IRQHandler + IRQ PIO0_8_IRQHandler + IRQ PIO0_9_IRQHandler + IRQ PIO0_10_IRQHandler + IRQ PIO0_11_IRQHandler + IRQ PIO1_0_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART_IRQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ FMC_IRQHandler + IRQ GPIO1_IRQHandler + IRQ GPIO0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc111x_lpc11cxx.s b/targets/device/nxp/lpc111x_lpc11cxx.s new file mode 100644 index 00000000..1d5e023e --- /dev/null +++ b/targets/device/nxp/lpc111x_lpc11cxx.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC11xx_v6a.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIO0_0_IRQHandler + .long PIO0_1_IRQHandler + .long PIO0_2_IRQHandler + .long PIO0_3_IRQHandler + .long PIO0_4_IRQHandler + .long PIO0_5_IRQHandler + .long PIO0_6_IRQHandler + .long PIO0_7_IRQHandler + .long PIO0_8_IRQHandler + .long PIO0_9_IRQHandler + .long PIO0_10_IRQHandler + .long PIO0_11_IRQHandler + .long PIO1_0_IRQHandler + .long C_CAN_IRQHandler + .long SPI1_IRQHandler + .long I2C_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SPI0_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long WDT_IRQHandler + .long BOD_IRQHandler + .long FMC_IRQHandler + .long GPIO3_IRQHandler + .long GPIO2_IRQHandler + .long GPIO1_IRQHandler + .long GPIO0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIO0_0_IRQHandler + IRQ PIO0_1_IRQHandler + IRQ PIO0_2_IRQHandler + IRQ PIO0_3_IRQHandler + IRQ PIO0_4_IRQHandler + IRQ PIO0_5_IRQHandler + IRQ PIO0_6_IRQHandler + IRQ PIO0_7_IRQHandler + IRQ PIO0_8_IRQHandler + IRQ PIO0_9_IRQHandler + IRQ PIO0_10_IRQHandler + IRQ PIO0_11_IRQHandler + IRQ PIO1_0_IRQHandler + IRQ C_CAN_IRQHandler + IRQ SPI1_IRQHandler + IRQ I2C_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART_IRQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ FMC_IRQHandler + IRQ GPIO3_IRQHandler + IRQ GPIO2_IRQHandler + IRQ GPIO1_IRQHandler + IRQ GPIO0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc11axx.s b/targets/device/nxp/lpc11axx.s new file mode 100644 index 00000000..b13325fc --- /dev/null +++ b/targets/device/nxp/lpc11axx.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC11Axxv0.6.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC11Axx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler + .long CMP_IRQHandler + .long DAC_IRQHandler + .long RESERVED0_IRQHandler + .long RESERVED1_IRQHandler + .long SSP1_IRQHandler + .long I2C_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SSP0_IRQHandler + .long USART_IRQHandler + .long RESERVED2_IRQHandler + .long RESERVED3_IRQHandler + .long ADC_IRQHandler + .long WDT_IRQHandler + .long BOD_IRQHandler + .long FMC_IRQHandler + .long RESERVED4_IRQHandler + .long RESERVED5_IRQHandler + .long RESERVED6_IRQHandler + .long RESERVED7_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ GINT0_IRQHandler + IRQ GINT1_IRQHandler + IRQ CMP_IRQHandler + IRQ DAC_IRQHandler + IRQ RESERVED0_IRQHandler + IRQ RESERVED1_IRQHandler + IRQ SSP1_IRQHandler + IRQ I2C_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SSP0_IRQHandler + IRQ USART_IRQHandler + IRQ RESERVED2_IRQHandler + IRQ RESERVED3_IRQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ FMC_IRQHandler + IRQ RESERVED4_IRQHandler + IRQ RESERVED5_IRQHandler + IRQ RESERVED6_IRQHandler + IRQ RESERVED7_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc11cxx.s b/targets/device/nxp/lpc11cxx.s new file mode 100644 index 00000000..43b1413b --- /dev/null +++ b/targets/device/nxp/lpc11cxx.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC11Cxx_v9.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC11Cxx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIO0_0_IRQHandler + .long PIO0_1_IRQHandler + .long PIO0_2_IRQHandler + .long PIO0_3_IRQHandler + .long PIO0_4_IRQHandler + .long PIO0_5_IRQHandler + .long PIO0_6_IRQHandler + .long PIO0_7_IRQHandler + .long PIO0_8_IRQHandler + .long PIO0_9_IRQHandler + .long PIO0_10_IRQHandler + .long PIO0_11_IRQHandler + .long PIO1_0_IRQHandler + .long C_CAN_IRQHandler + .long SPI1_IRQHandler + .long I2C_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SPI0_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long WDT_IRQHandler + .long BOD_IRQHandler + .long FMC_IRQHandler + .long GPIO3_IRQHandler + .long GPIO2_IRQHandler + .long GPIO1_IRQHandler + .long GPIO0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIO0_0_IRQHandler + IRQ PIO0_1_IRQHandler + IRQ PIO0_2_IRQHandler + IRQ PIO0_3_IRQHandler + IRQ PIO0_4_IRQHandler + IRQ PIO0_5_IRQHandler + IRQ PIO0_6_IRQHandler + IRQ PIO0_7_IRQHandler + IRQ PIO0_8_IRQHandler + IRQ PIO0_9_IRQHandler + IRQ PIO0_10_IRQHandler + IRQ PIO0_11_IRQHandler + IRQ PIO1_0_IRQHandler + IRQ C_CAN_IRQHandler + IRQ SPI1_IRQHandler + IRQ I2C_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART_IRQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ FMC_IRQHandler + IRQ GPIO3_IRQHandler + IRQ GPIO2_IRQHandler + IRQ GPIO1_IRQHandler + IRQ GPIO0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc11d14.s b/targets/device/nxp/lpc11d14.s new file mode 100644 index 00000000..5a483ec3 --- /dev/null +++ b/targets/device/nxp/lpc11d14.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC11D14_svd_v4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC11D14 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIO0_0_IRQHandler + .long PIO0_1_IRQHandler + .long PIO0_2_IRQHandler + .long PIO0_3_IRQHandler + .long PIO0_4_IRQHandler + .long PIO0_5_IRQHandler + .long PIO0_6_IRQHandler + .long PIO0_7_IRQHandler + .long PIO0_8_IRQHandler + .long PIO0_9_IRQHandler + .long PIO0_10_IRQHandler + .long PIO0_11_IRQHandler + .long PIO1_0_IRQHandler + .long 0 + .long SPI1_IRQHandler + .long I2C_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SPI0_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long WDT_IRQHandler + .long BOD_IRQHandler + .long FMC_IRQHandler + .long GPIO3_IRQHandler + .long GPIO2_IRQHandler + .long GPIO1_IRQHandler + .long GPIO0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIO0_0_IRQHandler + IRQ PIO0_1_IRQHandler + IRQ PIO0_2_IRQHandler + IRQ PIO0_3_IRQHandler + IRQ PIO0_4_IRQHandler + IRQ PIO0_5_IRQHandler + IRQ PIO0_6_IRQHandler + IRQ PIO0_7_IRQHandler + IRQ PIO0_8_IRQHandler + IRQ PIO0_9_IRQHandler + IRQ PIO0_10_IRQHandler + IRQ PIO0_11_IRQHandler + IRQ PIO1_0_IRQHandler + IRQ SPI1_IRQHandler + IRQ I2C_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART_IRQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ FMC_IRQHandler + IRQ GPIO3_IRQHandler + IRQ GPIO2_IRQHandler + IRQ GPIO1_IRQHandler + IRQ GPIO0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc11e6x.s b/targets/device/nxp/lpc11e6x.s new file mode 100644 index 00000000..0adc1a9a --- /dev/null +++ b/targets/device/nxp/lpc11e6x.s @@ -0,0 +1,123 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC11E6x_v0.8.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC11E6x ARM cortex-m0+ +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler + .long I2C1_IRQHandler + .long USART1_4_IRQHandler + .long USART2_3_IRQHandler + .long SCT0_1_IRQHandler + .long SSP1_IRQHandler + .long I2C0_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SSP0_IRQHandler + .long USART_IRQHandler + .long 0 + .long 0 + .long ADC_A_IRQHandler + .long RTC_IRQHandler + .long BOD_WDT_IRQHandler + .long FLASH_IRQHandler + .long DMA_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ GINT0_IRQHandler + IRQ GINT1_IRQHandler + IRQ I2C1_IRQHandler + IRQ USART1_4_IRQHandler + IRQ USART2_3_IRQHandler + IRQ SCT0_1_IRQHandler + IRQ SSP1_IRQHandler + IRQ I2C0_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SSP0_IRQHandler + IRQ USART_IRQHandler + IRQ ADC_A_IRQHandler + IRQ RTC_IRQHandler + IRQ BOD_WDT_IRQHandler + IRQ FLASH_IRQHandler + IRQ DMA_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc11exx.s b/targets/device/nxp/lpc11exx.s new file mode 100644 index 00000000..342be7c2 --- /dev/null +++ b/targets/device/nxp/lpc11exx.s @@ -0,0 +1,116 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC11Exx_v5.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC11Exx 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up to 10 kB SRAM and 4 kB EEPROM; USART +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long SSP1_IRQHandler + .long I2C_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SSP0_IRQHandler + .long USART_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long WDT_IRQHandler + .long 0 + .long FLASH_IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ GINT0_IRQHandler + IRQ GINT1_IRQHandler + IRQ SSP1_IRQHandler + IRQ I2C_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SSP0_IRQHandler + IRQ USART_IRQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ FLASH_IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc11uxx.s b/targets/device/nxp/lpc11uxx.s new file mode 100644 index 00000000..044ccb99 --- /dev/null +++ b/targets/device/nxp/lpc11uxx.s @@ -0,0 +1,123 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC11Uxx_v7.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC11Uxx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long SSP1_IRQHandler + .long I2C_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SSP0_IRQHandler + .long USART_IRQHandler + .long USB_IRQ_IRQHandler + .long USB_FIQ_IRQHandler + .long ADC_IRQHandler + .long WDT_IRQHandler + .long BOD_IRQ_IRQHandler + .long FLASH_IRQ_IRQHandler + .long 0 + .long 0 + .long USBWAKEUP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ GINT0_IRQHandler + IRQ GINT1_IRQHandler + IRQ SSP1_IRQHandler + IRQ I2C_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SSP0_IRQHandler + IRQ USART_IRQHandler + IRQ USB_IRQ_IRQHandler + IRQ USB_FIQ_IRQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQ_IRQHandler + IRQ FLASH_IRQ_IRQHandler + IRQ USBWAKEUP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc13uxx.s b/targets/device/nxp/lpc13uxx.s new file mode 100644 index 00000000..c1ee00a9 --- /dev/null +++ b/targets/device/nxp/lpc13uxx.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC13Uxx_v1.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC1315/16/17/35/36/37 Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler + .long 0 + .long 0 + .long RIT_IRQ_IRQHandler + .long 0 + .long SSP1_IRQHandler + .long I2C_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SSP0_IRQHandler + .long USART_IRQHandler + .long USB_IRQ_IRQHandler + .long USB_FIQ_IRQHandler + .long ADC_IRQHandler + .long WWDT_IRQHandler + .long BOD_IRQ_IRQHandler + .long FLASH_IRQ_IRQHandler + .long 0 + .long 0 + .long USBWAKEUP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ GINT0_IRQHandler + IRQ GINT1_IRQHandler + IRQ RIT_IRQ_IRQHandler + IRQ SSP1_IRQHandler + IRQ I2C_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SSP0_IRQHandler + IRQ USART_IRQHandler + IRQ USB_IRQ_IRQHandler + IRQ USB_FIQ_IRQHandler + IRQ ADC_IRQHandler + IRQ WWDT_IRQHandler + IRQ BOD_IRQ_IRQHandler + IRQ FLASH_IRQ_IRQHandler + IRQ USBWAKEUP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc13xx.s b/targets/device/nxp/lpc13xx.s new file mode 100644 index 00000000..e4334458 --- /dev/null +++ b/targets/device/nxp/lpc13xx.s @@ -0,0 +1,182 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC13xx_svd_v1.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC13xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PIO0_0_IRQHandler + .long PIO0_1_IRQHandler + .long PIO0_2_IRQHandler + .long PIO0_3_IRQHandler + .long PIO0_4_IRQHandler + .long PIO0_5_IRQHandler + .long PIO0_6_IRQHandler + .long PIO0_7_IRQHandler + .long PIO0_8_IRQHandler + .long PIO0_9_IRQHandler + .long PIO0_10_IRQHandler + .long PIO0_11_IRQHandler + .long PIO1_0_IRQHandler + .long PIO1_1_IRQHandler + .long PIO1_2_IRQHandler + .long PIO1_3_IRQHandler + .long PIO1_4_IRQHandler + .long PIO1_5_IRQHandler + .long PIO1_6_IRQHandler + .long PIO1_7_IRQHandler + .long PIO1_8_IRQHandler + .long PIO1_9_IRQHandler + .long PIO1_10_IRQHandler + .long PIO1_11_IRQHandler + .long PIO2_0_IRQHandler + .long PIO2_1_IRQHandler + .long PIO2_2_IRQHandler + .long PIO2_3_IRQHandler + .long PIO2_4_IRQHandler + .long PIO2_5_IRQHandler + .long PIO2_6_IRQHandler + .long PIO2_7_IRQHandler + .long PIO2_8_IRQHandler + .long PIO2_9_IRQHandler + .long PIO2_10_IRQHandler + .long PIO2_11_IRQHandler + .long PIO3_0_IRQHandler + .long PIO3_1_IRQHandler + .long PIO3_2_IRQHandler + .long PIO3_3_IRQHandler + .long I2C0_IRQHandler + .long CT16B0_IRQHandler + .long CT16B1_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long SSP0_IRQHandler + .long UART_IRQHandler + .long USBIRQ_IRQHandler + .long USBFIQ_IRQHandler + .long ADC_IRQHandler + .long WDT_IRQHandler + .long BOD_IRQHandler + .long 0 + .long PIO_3_IRQHandler + .long PIO_2_IRQHandler + .long PIO_1_IRQHandler + .long PIO_0_IRQHandler + .long SSP1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PIO0_0_IRQHandler + IRQ PIO0_1_IRQHandler + IRQ PIO0_2_IRQHandler + IRQ PIO0_3_IRQHandler + IRQ PIO0_4_IRQHandler + IRQ PIO0_5_IRQHandler + IRQ PIO0_6_IRQHandler + IRQ PIO0_7_IRQHandler + IRQ PIO0_8_IRQHandler + IRQ PIO0_9_IRQHandler + IRQ PIO0_10_IRQHandler + IRQ PIO0_11_IRQHandler + IRQ PIO1_0_IRQHandler + IRQ PIO1_1_IRQHandler + IRQ PIO1_2_IRQHandler + IRQ PIO1_3_IRQHandler + IRQ PIO1_4_IRQHandler + IRQ PIO1_5_IRQHandler + IRQ PIO1_6_IRQHandler + IRQ PIO1_7_IRQHandler + IRQ PIO1_8_IRQHandler + IRQ PIO1_9_IRQHandler + IRQ PIO1_10_IRQHandler + IRQ PIO1_11_IRQHandler + IRQ PIO2_0_IRQHandler + IRQ PIO2_1_IRQHandler + IRQ PIO2_2_IRQHandler + IRQ PIO2_3_IRQHandler + IRQ PIO2_4_IRQHandler + IRQ PIO2_5_IRQHandler + IRQ PIO2_6_IRQHandler + IRQ PIO2_7_IRQHandler + IRQ PIO2_8_IRQHandler + IRQ PIO2_9_IRQHandler + IRQ PIO2_10_IRQHandler + IRQ PIO2_11_IRQHandler + IRQ PIO3_0_IRQHandler + IRQ PIO3_1_IRQHandler + IRQ PIO3_2_IRQHandler + IRQ PIO3_3_IRQHandler + IRQ I2C0_IRQHandler + IRQ CT16B0_IRQHandler + IRQ CT16B1_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ SSP0_IRQHandler + IRQ UART_IRQHandler + IRQ USBIRQ_IRQHandler + IRQ USBFIQ_IRQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ PIO_3_IRQHandler + IRQ PIO_2_IRQHandler + IRQ PIO_1_IRQHandler + IRQ PIO_0_IRQHandler + IRQ SSP1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc15xx.s b/targets/device/nxp/lpc15xx.s new file mode 100644 index 00000000..9087d2c6 --- /dev/null +++ b/targets/device/nxp/lpc15xx.s @@ -0,0 +1,161 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC15xx_v0.7.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC15xx Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WDT_IRQHandler + .long BOD_IRQ_IRQHandler + .long FLASH_IRQHandler + .long EE_IRQHandler + .long DMA_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long RIT_IRQHandler + .long SCT0_IRQHandler + .long SCT1_IRQHandler + .long SCT2_IRQHandler + .long SCT3_IRQHandler + .long MRT_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long UART2_IRQHandler + .long I2C0_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long C_CAN0_IRQHandler + .long USB_IRQ_IRQHandler + .long USB_FIQ_IRQHandler + .long USBWAKEUP_IRQHandler + .long ADC0_SEQA_IRQHandler + .long ADC0_SEQB_IRQHandler + .long ADC0_THCMP_IRQHandler + .long ADC0_OVR_IRQHandler + .long ADC1_SEQA_IRQHandler + .long ADC1_SEQB_IRQHandler + .long ADC1_THCMP_IRQHandler + .long ADC1_OVR_IRQHandler + .long DAC_IRQHandler + .long CMP0_IRQHandler + .long CMP1_IRQHandler + .long CMP2_IRQHandler + .long CMP3_IRQHandler + .long QEI_IRQHandler + .long RTC_ALARM_IRQHandler + .long RTC_WAKE_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ BOD_IRQ_IRQHandler + IRQ FLASH_IRQHandler + IRQ EE_IRQHandler + IRQ DMA_IRQHandler + IRQ GINT0_IRQHandler + IRQ GINT1_IRQHandler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ RIT_IRQHandler + IRQ SCT0_IRQHandler + IRQ SCT1_IRQHandler + IRQ SCT2_IRQHandler + IRQ SCT3_IRQHandler + IRQ MRT_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ C_CAN0_IRQHandler + IRQ USB_IRQ_IRQHandler + IRQ USB_FIQ_IRQHandler + IRQ USBWAKEUP_IRQHandler + IRQ ADC0_SEQA_IRQHandler + IRQ ADC0_SEQB_IRQHandler + IRQ ADC0_THCMP_IRQHandler + IRQ ADC0_OVR_IRQHandler + IRQ ADC1_SEQA_IRQHandler + IRQ ADC1_SEQB_IRQHandler + IRQ ADC1_THCMP_IRQHandler + IRQ ADC1_OVR_IRQHandler + IRQ DAC_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ CMP2_IRQHandler + IRQ CMP3_IRQHandler + IRQ QEI_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ RTC_WAKE_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc176x5x.s b/targets/device/nxp/lpc176x5x.s new file mode 100644 index 00000000..bda65649 --- /dev/null +++ b/targets/device/nxp/lpc176x5x.s @@ -0,0 +1,137 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC176x5x_v0.2.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC176x/LPC175x M3 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WDT_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long TIMER3_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long PWM1_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI_IRQHandler + .long SSP0_IRQHandler + .long SSP1_IRQHandler + .long PLL0_IRQHandler + .long RTC_IRQHandler + .long EINT0_IRQHandler + .long EINT1_IRQHandler + .long EINT2_IRQHandler + .long EINT3_IRQHandler + .long ADC_IRQHandler + .long BOD_IRQHandler + .long USB_IRQHandler + .long CAN_IRQHandler + .long DMA_IRQHandler + .long I2S_IRQHandler + .long ENET_IRQHandler + .long RIT_IRQHandler + .long MCPWM_IRQHandler + .long QEI_IRQHandler + .long PLL1_IRQHandler + .long USBActivity_IRQHandler + .long CANActivity_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER3_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ PWM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI_IRQHandler + IRQ SSP0_IRQHandler + IRQ SSP1_IRQHandler + IRQ PLL0_IRQHandler + IRQ RTC_IRQHandler + IRQ EINT0_IRQHandler + IRQ EINT1_IRQHandler + IRQ EINT2_IRQHandler + IRQ EINT3_IRQHandler + IRQ ADC_IRQHandler + IRQ BOD_IRQHandler + IRQ USB_IRQHandler + IRQ CAN_IRQHandler + IRQ DMA_IRQHandler + IRQ I2S_IRQHandler + IRQ ENET_IRQHandler + IRQ RIT_IRQHandler + IRQ MCPWM_IRQHandler + IRQ QEI_IRQHandler + IRQ PLL1_IRQHandler + IRQ USBActivity_IRQHandler + IRQ CANActivity_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc18xx.s b/targets/device/nxp/lpc18xx.s new file mode 100644 index 00000000..34da6387 --- /dev/null +++ b/targets/device/nxp/lpc18xx.s @@ -0,0 +1,165 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC18xx.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// Register cmsis file for LPC18xx parts +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DAC_IRQHandler + .long 0 + .long DMA_IRQHandler + .long 0 + .long FLASH_IRQHandler + .long ETHERNET_IRQHandler + .long SDIO_IRQHandler + .long LCD_IRQHandler + .long USB0_IRQHandler + .long USB1_IRQHandler + .long SCT_IRQHandler + .long RITIMER_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long TIMER3_IRQHandler + .long MCPWM_IRQHandler + .long ADC0_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long 0 + .long ADC1_IRQHandler + .long SSP0_IRQHandler + .long SSP1_IRQHandler + .long USART0_IRQHandler + .long UART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long I2S0_IRQHandler + .long I2S1_IRQHandler + .long SPIFI_IRQHandler + .long 0 + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler + .long EVENTROUTER_IRQHandler + .long C_CAN1_IRQHandler + .long 0 + .long 0 + .long ATIMER_IRQHandler + .long RTC_IRQHandler + .long 0 + .long WWDT_IRQHandler + .long 0 + .long C_CAN0_IRQHandler + .long QEI_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DAC_IRQHandler + IRQ DMA_IRQHandler + IRQ FLASH_IRQHandler + IRQ ETHERNET_IRQHandler + IRQ SDIO_IRQHandler + IRQ LCD_IRQHandler + IRQ USB0_IRQHandler + IRQ USB1_IRQHandler + IRQ SCT_IRQHandler + IRQ RITIMER_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER3_IRQHandler + IRQ MCPWM_IRQHandler + IRQ ADC0_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ ADC1_IRQHandler + IRQ SSP0_IRQHandler + IRQ SSP1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ I2S0_IRQHandler + IRQ I2S1_IRQHandler + IRQ SPIFI_IRQHandler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ GINT0_IRQHandler + IRQ GINT1_IRQHandler + IRQ EVENTROUTER_IRQHandler + IRQ C_CAN1_IRQHandler + IRQ ATIMER_IRQHandler + IRQ RTC_IRQHandler + IRQ WWDT_IRQHandler + IRQ C_CAN0_IRQHandler + IRQ QEI_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc408x_7x.s b/targets/device/nxp/lpc408x_7x.s new file mode 100644 index 00000000..bc7f82a7 --- /dev/null +++ b/targets/device/nxp/lpc408x_7x.s @@ -0,0 +1,149 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC408x_7x_v0.7.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC408x/7x M4 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDT_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long TIMER3_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long PWM1_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long 0 + .long SSP0_IRQHandler + .long SSP1_IRQHandler + .long 0 + .long RTC_IRQHandler + .long EINT0_IRQHandler + .long EINT1_IRQHandler + .long EINT2_IRQHandler + .long EINT3_IRQHandler + .long ADC_IRQHandler + .long BOD_IRQHandler + .long USB_IRQHandler + .long CAN_IRQHandler + .long GPDMA_IRQHandler + .long I2S_IRQHandler + .long ETHERNET_IRQHandler + .long SDMMC_IRQHandler + .long MCPWM_IRQHandler + .long QEI_IRQHandler + .long 0 + .long USB_NEED_CLK_IRQHandler + .long 0 + .long UART4_IRQHandler + .long SSP2_IRQHandler + .long LCD_IRQHandler + .long GPIOINT_IRQHandler + .long PWM0_IRQHandler + .long EEPROM_IRQHandler + .long CMP0_IRQHandler + .long CMP1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDT_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER3_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ PWM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SSP0_IRQHandler + IRQ SSP1_IRQHandler + IRQ RTC_IRQHandler + IRQ EINT0_IRQHandler + IRQ EINT1_IRQHandler + IRQ EINT2_IRQHandler + IRQ EINT3_IRQHandler + IRQ ADC_IRQHandler + IRQ BOD_IRQHandler + IRQ USB_IRQHandler + IRQ CAN_IRQHandler + IRQ GPDMA_IRQHandler + IRQ I2S_IRQHandler + IRQ ETHERNET_IRQHandler + IRQ SDMMC_IRQHandler + IRQ MCPWM_IRQHandler + IRQ QEI_IRQHandler + IRQ USB_NEED_CLK_IRQHandler + IRQ UART4_IRQHandler + IRQ SSP2_IRQHandler + IRQ LCD_IRQHandler + IRQ GPIOINT_IRQHandler + IRQ PWM0_IRQHandler + IRQ EEPROM_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc43xx.s b/targets/device/nxp/lpc43xx.s new file mode 100644 index 00000000..840620fd --- /dev/null +++ b/targets/device/nxp/lpc43xx.s @@ -0,0 +1,168 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC43xx_43Sxx.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// Register cmsis file for LPC43xx parts +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DAC_IRQHandler + .long 0 + .long DMA_IRQHandler + .long 0 + .long FLASH_IRQHandler + .long ETHERNET_IRQHandler + .long SDIO_IRQHandler + .long LCD_IRQHandler + .long USB0_IRQHandler + .long USB1_IRQHandler + .long SCT_IRQHandler + .long RITIMER_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long TIMER3_IRQHandler + .long MCPWM_IRQHandler + .long ADC0_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long SPI_INT_IRQHandler + .long ADC1_IRQHandler + .long SSP0_IRQHandler + .long SSP1_IRQHandler + .long USART0_IRQHandler + .long UART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long I2S0_IRQHandler + .long I2S1_IRQHandler + .long SPIFI_IRQHandler + .long SGPIO_IINT_IRQHandler + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler + .long EVENTROUTER_IRQHandler + .long C_CAN1_IRQHandler + .long 0 + .long ADCHS_IRQHandler + .long ATIMER_IRQHandler + .long RTC_IRQHandler + .long 0 + .long WWDT_IRQHandler + .long 0 + .long C_CAN0_IRQHandler + .long QEI_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DAC_IRQHandler + IRQ DMA_IRQHandler + IRQ FLASH_IRQHandler + IRQ ETHERNET_IRQHandler + IRQ SDIO_IRQHandler + IRQ LCD_IRQHandler + IRQ USB0_IRQHandler + IRQ USB1_IRQHandler + IRQ SCT_IRQHandler + IRQ RITIMER_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER3_IRQHandler + IRQ MCPWM_IRQHandler + IRQ ADC0_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI_INT_IRQHandler + IRQ ADC1_IRQHandler + IRQ SSP0_IRQHandler + IRQ SSP1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ I2S0_IRQHandler + IRQ I2S1_IRQHandler + IRQ SPIFI_IRQHandler + IRQ SGPIO_IINT_IRQHandler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ GINT0_IRQHandler + IRQ GINT1_IRQHandler + IRQ EVENTROUTER_IRQHandler + IRQ C_CAN1_IRQHandler + IRQ ADCHS_IRQHandler + IRQ ATIMER_IRQHandler + IRQ RTC_IRQHandler + IRQ WWDT_IRQHandler + IRQ C_CAN0_IRQHandler + IRQ QEI_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc5410x.s b/targets/device/nxp/lpc5410x.s new file mode 100644 index 00000000..5262e986 --- /dev/null +++ b/targets/device/nxp/lpc5410x.s @@ -0,0 +1,144 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC5410x_v0.4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC5410x Cortex-M4 MCU; Cortex-M0+ coprocessor +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WDT_IRQHandler + .long BOD_IRQHandler + .long 0 + .long DMA_IRQHandler + .long GINT0_IRQHandler + .long PIN_INT0_IRQHandler + .long PIN_INT1_IRQHandler + .long PIN_INT2_IRQHandler + .long PIN_INT3_IRQHandler + .long UTICK_IRQHandler + .long MRT_IRQHandler + .long CT32B0_IRQHandler + .long CT32B1_IRQHandler + .long CT32B2_IRQHandler + .long CT32B3_IRQHandler + .long CT32B4_IRQHandler + .long SCT0_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long ADC_SEQA_IRQHandler + .long ADC_SEQB_IRQHandler + .long ADC_THCMP_IRQHandler + .long RTC_IRQHandler + .long 0 + .long MAILBOX_IRQHandler + .long GINT1_IRQHandler + .long PIN_INT4_IRQHandler + .long PIN_INT5_IRQHandler + .long PIN_INT6_IRQHandler + .long PIN_INT7_IRQHandler + .long 0 + .long 0 + .long 0 + .long RIT_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ DMA_IRQHandler + IRQ GINT0_IRQHandler + IRQ PIN_INT0_IRQHandler + IRQ PIN_INT1_IRQHandler + IRQ PIN_INT2_IRQHandler + IRQ PIN_INT3_IRQHandler + IRQ UTICK_IRQHandler + IRQ MRT_IRQHandler + IRQ CT32B0_IRQHandler + IRQ CT32B1_IRQHandler + IRQ CT32B2_IRQHandler + IRQ CT32B3_IRQHandler + IRQ CT32B4_IRQHandler + IRQ SCT0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ ADC_SEQA_IRQHandler + IRQ ADC_SEQB_IRQHandler + IRQ ADC_THCMP_IRQHandler + IRQ RTC_IRQHandler + IRQ MAILBOX_IRQHandler + IRQ GINT1_IRQHandler + IRQ PIN_INT4_IRQHandler + IRQ PIN_INT5_IRQHandler + IRQ PIN_INT6_IRQHandler + IRQ PIN_INT7_IRQHandler + IRQ RIT_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/lpc800.s b/targets/device/nxp/lpc800.s new file mode 100644 index 00000000..f6b88f40 --- /dev/null +++ b/targets/device/nxp/lpc800.s @@ -0,0 +1,120 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC800_v0.3.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// LPC800 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long I2C_IRQHandler + .long SCT_IRQHandler + .long MRT_IRQHandler + .long CMP_IRQHandler + .long WDT_IRQHandler + .long BOD_IRQHandler + .long FLASH_IRQ_IRQHandler + .long WKT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PININT0_IRQHandler + .long PININT1_IRQHandler + .long PININT2_IRQHandler + .long PININT3_IRQHandler + .long PININT4_IRQHandler + .long PININT5_IRQHandler + .long PININT6_IRQHandler + .long PININT7_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ I2C_IRQHandler + IRQ SCT_IRQHandler + IRQ MRT_IRQHandler + IRQ CMP_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ FLASH_IRQ_IRQHandler + IRQ WKT_IRQHandler + IRQ PININT0_IRQHandler + IRQ PININT1_IRQHandler + IRQ PININT2_IRQHandler + IRQ PININT3_IRQHandler + IRQ PININT4_IRQHandler + IRQ PININT5_IRQHandler + IRQ PININT6_IRQHandler + IRQ PININT7_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mimxrt1011.s b/targets/device/nxp/mimxrt1011.s new file mode 100644 index 00000000..91ae9566 --- /dev/null +++ b/targets/device/nxp/mimxrt1011.s @@ -0,0 +1,227 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MIMXRT1011.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MIMXRT1011DAE5A +*/ + +// Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_IRQHandler + .long DMA1_IRQHandler + .long DMA2_IRQHandler + .long DMA3_IRQHandler + .long DMA4_IRQHandler + .long DMA5_IRQHandler + .long DMA6_IRQHandler + .long DMA7_IRQHandler + .long DMA8_IRQHandler + .long DMA9_IRQHandler + .long DMA10_IRQHandler + .long DMA11_IRQHandler + .long DMA12_IRQHandler + .long DMA13_IRQHandler + .long DMA14_IRQHandler + .long DMA15_IRQHandler + .long DMA_ERROR_IRQHandler + .long CTI0_ERROR_IRQHandler + .long CTI1_ERROR_IRQHandler + .long CORE_IRQHandler + .long LPUART1_IRQHandler + .long LPUART2_IRQHandler + .long LPUART3_IRQHandler + .long LPUART4_IRQHandler + .long PIT_IRQHandler + .long USB_OTG1_IRQHandler + .long FLEXSPI_IRQHandler + .long FLEXRAM_IRQHandler + .long LPI2C1_IRQHandler + .long LPI2C2_IRQHandler + .long GPT1_IRQHandler + .long GPT2_IRQHandler + .long LPSPI1_IRQHandler + .long LPSPI2_IRQHandler + .long PWM1_0_IRQHandler + .long PWM1_1_IRQHandler + .long PWM1_2_IRQHandler + .long PWM1_3_IRQHandler + .long PWM1_FAULT_IRQHandler + .long KPP_IRQHandler + .long SRC_IRQHandler + .long GPR_IRQ_IRQHandler + .long CCM_1_IRQHandler + .long CCM_2_IRQHandler + .long EWM_IRQHandler + .long WDOG2_IRQHandler + .long SNVS_HP_WRAPPER_IRQHandler + .long SNVS_HP_WRAPPER_TZ_IRQHandler + .long SNVS_LP_WRAPPER_IRQHandler + .long CSU_IRQHandler + .long DCP_IRQHandler + .long DCP_VMI_IRQHandler + .long Reserved68_IRQHandler + .long TRNG_IRQHandler + .long Reserved70_IRQHandler + .long Reserved71_IRQHandler + .long SAI1_IRQHandler + .long RTWDOG_IRQHandler + .long SAI3_RX_IRQHandler + .long SAI3_TX_IRQHandler + .long SPDIF_IRQHandler + .long PMU_IRQHandler + .long XBAR1_IRQ_0_1_2_3_IRQHandler + .long TEMP_LOW_HIGH_IRQHandler + .long TEMP_PANIC_IRQHandler + .long USB_PHY_IRQHandler + .long GPC_IRQHandler + .long ADC1_IRQHandler + .long FLEXIO1_IRQHandler + .long DCDC_IRQHandler + .long GPIO1_Combined_0_15_IRQHandler + .long GPIO1_Combined_16_31_IRQHandler + .long GPIO2_Combined_0_15_IRQHandler + .long GPIO5_Combined_0_15_IRQHandler + .long WDOG1_IRQHandler + .long ADC_ETC_IRQ0_IRQHandler + .long ADC_ETC_IRQ1_IRQHandler + .long ADC_ETC_IRQ2_IRQHandler + .long ADC_ETC_IRQ3_IRQHandler + .long ADC_ETC_ERROR_IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_IRQHandler + IRQ DMA1_IRQHandler + IRQ DMA2_IRQHandler + IRQ DMA3_IRQHandler + IRQ DMA4_IRQHandler + IRQ DMA5_IRQHandler + IRQ DMA6_IRQHandler + IRQ DMA7_IRQHandler + IRQ DMA8_IRQHandler + IRQ DMA9_IRQHandler + IRQ DMA10_IRQHandler + IRQ DMA11_IRQHandler + IRQ DMA12_IRQHandler + IRQ DMA13_IRQHandler + IRQ DMA14_IRQHandler + IRQ DMA15_IRQHandler + IRQ DMA_ERROR_IRQHandler + IRQ CTI0_ERROR_IRQHandler + IRQ CTI1_ERROR_IRQHandler + IRQ CORE_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPUART2_IRQHandler + IRQ LPUART3_IRQHandler + IRQ LPUART4_IRQHandler + IRQ PIT_IRQHandler + IRQ USB_OTG1_IRQHandler + IRQ FLEXSPI_IRQHandler + IRQ FLEXRAM_IRQHandler + IRQ LPI2C1_IRQHandler + IRQ LPI2C2_IRQHandler + IRQ GPT1_IRQHandler + IRQ GPT2_IRQHandler + IRQ LPSPI1_IRQHandler + IRQ LPSPI2_IRQHandler + IRQ PWM1_0_IRQHandler + IRQ PWM1_1_IRQHandler + IRQ PWM1_2_IRQHandler + IRQ PWM1_3_IRQHandler + IRQ PWM1_FAULT_IRQHandler + IRQ KPP_IRQHandler + IRQ SRC_IRQHandler + IRQ GPR_IRQ_IRQHandler + IRQ CCM_1_IRQHandler + IRQ CCM_2_IRQHandler + IRQ EWM_IRQHandler + IRQ WDOG2_IRQHandler + IRQ SNVS_HP_WRAPPER_IRQHandler + IRQ SNVS_HP_WRAPPER_TZ_IRQHandler + IRQ SNVS_LP_WRAPPER_IRQHandler + IRQ CSU_IRQHandler + IRQ DCP_IRQHandler + IRQ DCP_VMI_IRQHandler + IRQ Reserved68_IRQHandler + IRQ TRNG_IRQHandler + IRQ Reserved70_IRQHandler + IRQ Reserved71_IRQHandler + IRQ SAI1_IRQHandler + IRQ RTWDOG_IRQHandler + IRQ SAI3_RX_IRQHandler + IRQ SAI3_TX_IRQHandler + IRQ SPDIF_IRQHandler + IRQ PMU_IRQHandler + IRQ XBAR1_IRQ_0_1_2_3_IRQHandler + IRQ TEMP_LOW_HIGH_IRQHandler + IRQ TEMP_PANIC_IRQHandler + IRQ USB_PHY_IRQHandler + IRQ GPC_IRQHandler + IRQ ADC1_IRQHandler + IRQ FLEXIO1_IRQHandler + IRQ DCDC_IRQHandler + IRQ GPIO1_Combined_0_15_IRQHandler + IRQ GPIO1_Combined_16_31_IRQHandler + IRQ GPIO2_Combined_0_15_IRQHandler + IRQ GPIO5_Combined_0_15_IRQHandler + IRQ WDOG1_IRQHandler + IRQ ADC_ETC_IRQ0_IRQHandler + IRQ ADC_ETC_IRQ1_IRQHandler + IRQ ADC_ETC_IRQ2_IRQHandler + IRQ ADC_ETC_IRQ3_IRQHandler + IRQ ADC_ETC_ERROR_IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mimxrt1021.s b/targets/device/nxp/mimxrt1021.s new file mode 100644 index 00000000..9d6009dc --- /dev/null +++ b/targets/device/nxp/mimxrt1021.s @@ -0,0 +1,350 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MIMXRT1021.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MIMXRT1021DAG5A +*/ + +// Copyright 2016-2020 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_DMA16_IRQHandler + .long DMA1_DMA17_IRQHandler + .long DMA2_DMA18_IRQHandler + .long DMA3_DMA19_IRQHandler + .long DMA4_DMA20_IRQHandler + .long DMA5_DMA21_IRQHandler + .long DMA6_DMA22_IRQHandler + .long DMA7_DMA23_IRQHandler + .long DMA8_DMA24_IRQHandler + .long DMA9_DMA25_IRQHandler + .long DMA10_DMA26_IRQHandler + .long DMA11_DMA27_IRQHandler + .long DMA12_DMA28_IRQHandler + .long DMA13_DMA29_IRQHandler + .long DMA14_DMA30_IRQHandler + .long DMA15_DMA31_IRQHandler + .long DMA_ERROR_IRQHandler + .long CTI0_ERROR_IRQHandler + .long CTI1_ERROR_IRQHandler + .long CORE_IRQHandler + .long LPUART1_IRQHandler + .long LPUART2_IRQHandler + .long LPUART3_IRQHandler + .long LPUART4_IRQHandler + .long LPUART5_IRQHandler + .long LPUART6_IRQHandler + .long LPUART7_IRQHandler + .long LPUART8_IRQHandler + .long LPI2C1_IRQHandler + .long LPI2C2_IRQHandler + .long LPI2C3_IRQHandler + .long LPI2C4_IRQHandler + .long LPSPI1_IRQHandler + .long LPSPI2_IRQHandler + .long LPSPI3_IRQHandler + .long LPSPI4_IRQHandler + .long CAN1_IRQHandler + .long CAN2_IRQHandler + .long FLEXRAM_IRQHandler + .long KPP_IRQHandler + .long Reserved56_IRQHandler + .long GPR_IRQ_IRQHandler + .long Reserved58_IRQHandler + .long Reserved59_IRQHandler + .long Reserved60_IRQHandler + .long WDOG2_IRQHandler + .long SNVS_HP_WRAPPER_IRQHandler + .long SNVS_HP_WRAPPER_TZ_IRQHandler + .long SNVS_LP_HP_WRAPPER_IRQHandler + .long CSU_IRQHandler + .long DCP_IRQHandler + .long DCP_VMI_IRQHandler + .long Reserved68_IRQHandler + .long TRNG_IRQHandler + .long 0 + .long BEE_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long SAI3_RX_IRQHandler + .long SAI3_TX_IRQHandler + .long SPDIF_IRQHandler + .long PMU_IRQHandler + .long Reserved78_IRQHandler + .long TEMP_LOW_HIGH_IRQHandler + .long TEMP_PANIC_IRQHandler + .long USB_PHY_IRQHandler + .long Reserved82_IRQHandler + .long ADC1_IRQHandler + .long ADC2_IRQHandler + .long DCDC_IRQHandler + .long Reserved86_IRQHandler + .long Reserved87_IRQHandler + .long GPIO1_INT0_IRQHandler + .long GPIO1_INT1_IRQHandler + .long GPIO1_INT2_IRQHandler + .long GPIO1_INT3_IRQHandler + .long GPIO1_INT4_IRQHandler + .long GPIO1_INT5_IRQHandler + .long GPIO1_INT6_IRQHandler + .long GPIO1_INT7_IRQHandler + .long GPIO1_Combined_0_15_IRQHandler + .long GPIO1_Combined_16_31_IRQHandler + .long GPIO2_Combined_0_15_IRQHandler + .long GPIO2_Combined_16_31_IRQHandler + .long GPIO3_Combined_0_15_IRQHandler + .long GPIO3_Combined_16_31_IRQHandler + .long Reserved102_IRQHandler + .long Reserved103_IRQHandler + .long GPIO5_Combined_0_15_IRQHandler + .long GPIO5_Combined_16_31_IRQHandler + .long FLEXIO1_IRQHandler + .long Reserved107_IRQHandler + .long WDOG1_IRQHandler + .long RTWDOG_IRQHandler + .long EWM_IRQHandler + .long CCM_1_IRQHandler + .long CCM_2_IRQHandler + .long GPC_IRQHandler + .long SRC_IRQHandler + .long Reserved115_IRQHandler + .long GPT1_IRQHandler + .long GPT2_IRQHandler + .long PWM1_0_IRQHandler + .long PWM1_1_IRQHandler + .long PWM1_2_IRQHandler + .long PWM1_3_IRQHandler + .long PWM1_FAULT_IRQHandler + .long Reserved123_IRQHandler + .long FLEXSPI_IRQHandler + .long SEMC_IRQHandler + .long USDHC1_IRQHandler + .long USDHC2_IRQHandler + .long Reserved128_IRQHandler + .long USB_OTG1_IRQHandler + .long ENET_IRQHandler + .long ENET_1588_Timer_IRQHandler + .long XBAR1_IRQ_0_1_IRQHandler + .long XBAR1_IRQ_2_3_IRQHandler + .long ADC_ETC_IRQ0_IRQHandler + .long ADC_ETC_IRQ1_IRQHandler + .long ADC_ETC_IRQ2_IRQHandler + .long ADC_ETC_ERROR_IRQ_IRQHandler + .long PIT_IRQHandler + .long ACMP1_IRQHandler + .long ACMP2_IRQHandler + .long ACMP3_IRQHandler + .long ACMP4_IRQHandler + .long Reserved143_IRQHandler + .long Reserved144_IRQHandler + .long ENC1_IRQHandler + .long ENC2_IRQHandler + .long Reserved147_IRQHandler + .long Reserved148_IRQHandler + .long TMR1_IRQHandler + .long TMR2_IRQHandler + .long Reserved151_IRQHandler + .long Reserved152_IRQHandler + .long PWM2_0_IRQHandler + .long PWM2_1_IRQHandler + .long PWM2_2_IRQHandler + .long PWM2_3_IRQHandler + .long PWM2_FAULT_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_DMA16_IRQHandler + IRQ DMA1_DMA17_IRQHandler + IRQ DMA2_DMA18_IRQHandler + IRQ DMA3_DMA19_IRQHandler + IRQ DMA4_DMA20_IRQHandler + IRQ DMA5_DMA21_IRQHandler + IRQ DMA6_DMA22_IRQHandler + IRQ DMA7_DMA23_IRQHandler + IRQ DMA8_DMA24_IRQHandler + IRQ DMA9_DMA25_IRQHandler + IRQ DMA10_DMA26_IRQHandler + IRQ DMA11_DMA27_IRQHandler + IRQ DMA12_DMA28_IRQHandler + IRQ DMA13_DMA29_IRQHandler + IRQ DMA14_DMA30_IRQHandler + IRQ DMA15_DMA31_IRQHandler + IRQ DMA_ERROR_IRQHandler + IRQ CTI0_ERROR_IRQHandler + IRQ CTI1_ERROR_IRQHandler + IRQ CORE_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPUART2_IRQHandler + IRQ LPUART3_IRQHandler + IRQ LPUART4_IRQHandler + IRQ LPUART5_IRQHandler + IRQ LPUART6_IRQHandler + IRQ LPUART7_IRQHandler + IRQ LPUART8_IRQHandler + IRQ LPI2C1_IRQHandler + IRQ LPI2C2_IRQHandler + IRQ LPI2C3_IRQHandler + IRQ LPI2C4_IRQHandler + IRQ LPSPI1_IRQHandler + IRQ LPSPI2_IRQHandler + IRQ LPSPI3_IRQHandler + IRQ LPSPI4_IRQHandler + IRQ CAN1_IRQHandler + IRQ CAN2_IRQHandler + IRQ FLEXRAM_IRQHandler + IRQ KPP_IRQHandler + IRQ Reserved56_IRQHandler + IRQ GPR_IRQ_IRQHandler + IRQ Reserved58_IRQHandler + IRQ Reserved59_IRQHandler + IRQ Reserved60_IRQHandler + IRQ WDOG2_IRQHandler + IRQ SNVS_HP_WRAPPER_IRQHandler + IRQ SNVS_HP_WRAPPER_TZ_IRQHandler + IRQ SNVS_LP_HP_WRAPPER_IRQHandler + IRQ CSU_IRQHandler + IRQ DCP_IRQHandler + IRQ DCP_VMI_IRQHandler + IRQ Reserved68_IRQHandler + IRQ TRNG_IRQHandler + IRQ BEE_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ SAI3_RX_IRQHandler + IRQ SAI3_TX_IRQHandler + IRQ SPDIF_IRQHandler + IRQ PMU_IRQHandler + IRQ Reserved78_IRQHandler + IRQ TEMP_LOW_HIGH_IRQHandler + IRQ TEMP_PANIC_IRQHandler + IRQ USB_PHY_IRQHandler + IRQ Reserved82_IRQHandler + IRQ ADC1_IRQHandler + IRQ ADC2_IRQHandler + IRQ DCDC_IRQHandler + IRQ Reserved86_IRQHandler + IRQ Reserved87_IRQHandler + IRQ GPIO1_INT0_IRQHandler + IRQ GPIO1_INT1_IRQHandler + IRQ GPIO1_INT2_IRQHandler + IRQ GPIO1_INT3_IRQHandler + IRQ GPIO1_INT4_IRQHandler + IRQ GPIO1_INT5_IRQHandler + IRQ GPIO1_INT6_IRQHandler + IRQ GPIO1_INT7_IRQHandler + IRQ GPIO1_Combined_0_15_IRQHandler + IRQ GPIO1_Combined_16_31_IRQHandler + IRQ GPIO2_Combined_0_15_IRQHandler + IRQ GPIO2_Combined_16_31_IRQHandler + IRQ GPIO3_Combined_0_15_IRQHandler + IRQ GPIO3_Combined_16_31_IRQHandler + IRQ Reserved102_IRQHandler + IRQ Reserved103_IRQHandler + IRQ GPIO5_Combined_0_15_IRQHandler + IRQ GPIO5_Combined_16_31_IRQHandler + IRQ FLEXIO1_IRQHandler + IRQ Reserved107_IRQHandler + IRQ WDOG1_IRQHandler + IRQ RTWDOG_IRQHandler + IRQ EWM_IRQHandler + IRQ CCM_1_IRQHandler + IRQ CCM_2_IRQHandler + IRQ GPC_IRQHandler + IRQ SRC_IRQHandler + IRQ Reserved115_IRQHandler + IRQ GPT1_IRQHandler + IRQ GPT2_IRQHandler + IRQ PWM1_0_IRQHandler + IRQ PWM1_1_IRQHandler + IRQ PWM1_2_IRQHandler + IRQ PWM1_3_IRQHandler + IRQ PWM1_FAULT_IRQHandler + IRQ Reserved123_IRQHandler + IRQ FLEXSPI_IRQHandler + IRQ SEMC_IRQHandler + IRQ USDHC1_IRQHandler + IRQ USDHC2_IRQHandler + IRQ Reserved128_IRQHandler + IRQ USB_OTG1_IRQHandler + IRQ ENET_IRQHandler + IRQ ENET_1588_Timer_IRQHandler + IRQ XBAR1_IRQ_0_1_IRQHandler + IRQ XBAR1_IRQ_2_3_IRQHandler + IRQ ADC_ETC_IRQ0_IRQHandler + IRQ ADC_ETC_IRQ1_IRQHandler + IRQ ADC_ETC_IRQ2_IRQHandler + IRQ ADC_ETC_ERROR_IRQ_IRQHandler + IRQ PIT_IRQHandler + IRQ ACMP1_IRQHandler + IRQ ACMP2_IRQHandler + IRQ ACMP3_IRQHandler + IRQ ACMP4_IRQHandler + IRQ Reserved143_IRQHandler + IRQ Reserved144_IRQHandler + IRQ ENC1_IRQHandler + IRQ ENC2_IRQHandler + IRQ Reserved147_IRQHandler + IRQ Reserved148_IRQHandler + IRQ TMR1_IRQHandler + IRQ TMR2_IRQHandler + IRQ Reserved151_IRQHandler + IRQ Reserved152_IRQHandler + IRQ PWM2_0_IRQHandler + IRQ PWM2_1_IRQHandler + IRQ PWM2_2_IRQHandler + IRQ PWM2_3_IRQHandler + IRQ PWM2_FAULT_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mimxrt1052.s b/targets/device/nxp/mimxrt1052.s new file mode 100644 index 00000000..0f4c641d --- /dev/null +++ b/targets/device/nxp/mimxrt1052.s @@ -0,0 +1,371 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MIMXRT1052.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MIMXRT1052DVL6B +*/ + +// Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_DMA16_IRQHandler + .long DMA1_DMA17_IRQHandler + .long DMA2_DMA18_IRQHandler + .long DMA3_DMA19_IRQHandler + .long DMA4_DMA20_IRQHandler + .long DMA5_DMA21_IRQHandler + .long DMA6_DMA22_IRQHandler + .long DMA7_DMA23_IRQHandler + .long DMA8_DMA24_IRQHandler + .long DMA9_DMA25_IRQHandler + .long DMA10_DMA26_IRQHandler + .long DMA11_DMA27_IRQHandler + .long DMA12_DMA28_IRQHandler + .long DMA13_DMA29_IRQHandler + .long DMA14_DMA30_IRQHandler + .long DMA15_DMA31_IRQHandler + .long DMA_ERROR_IRQHandler + .long CTI0_ERROR_IRQHandler + .long CTI1_ERROR_IRQHandler + .long CORE_IRQHandler + .long LPUART1_IRQHandler + .long LPUART2_IRQHandler + .long LPUART3_IRQHandler + .long LPUART4_IRQHandler + .long LPUART5_IRQHandler + .long LPUART6_IRQHandler + .long LPUART7_IRQHandler + .long LPUART8_IRQHandler + .long LPI2C1_IRQHandler + .long LPI2C2_IRQHandler + .long LPI2C3_IRQHandler + .long LPI2C4_IRQHandler + .long LPSPI1_IRQHandler + .long LPSPI2_IRQHandler + .long LPSPI3_IRQHandler + .long LPSPI4_IRQHandler + .long CAN1_IRQHandler + .long CAN2_IRQHandler + .long FLEXRAM_IRQHandler + .long KPP_IRQHandler + .long TSC_DIG_IRQHandler + .long GPR_IRQ_IRQHandler + .long LCDIF_IRQHandler + .long CSI_IRQHandler + .long PXP_IRQHandler + .long WDOG2_IRQHandler + .long SNVS_HP_WRAPPER_IRQHandler + .long SNVS_HP_WRAPPER_TZ_IRQHandler + .long SNVS_LP_WRAPPER_IRQHandler + .long CSU_IRQHandler + .long DCP_IRQHandler + .long DCP_VMI_IRQHandler + .long Reserved68_IRQHandler + .long TRNG_IRQHandler + .long SJC_IRQHandler + .long BEE_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long SAI3_RX_IRQHandler + .long SAI3_TX_IRQHandler + .long SPDIF_IRQHandler + .long PMU_EVENT_IRQHandler + .long Reserved78_IRQHandler + .long TEMP_LOW_HIGH_IRQHandler + .long TEMP_PANIC_IRQHandler + .long USB_PHY1_IRQHandler + .long USB_PHY2_IRQHandler + .long ADC1_IRQHandler + .long ADC2_IRQHandler + .long DCDC_IRQHandler + .long Reserved86_IRQHandler + .long Reserved87_IRQHandler + .long GPIO1_INT0_IRQHandler + .long GPIO1_INT1_IRQHandler + .long GPIO1_INT2_IRQHandler + .long GPIO1_INT3_IRQHandler + .long GPIO1_INT4_IRQHandler + .long GPIO1_INT5_IRQHandler + .long GPIO1_INT6_IRQHandler + .long GPIO1_INT7_IRQHandler + .long GPIO1_Combined_0_15_IRQHandler + .long GPIO1_Combined_16_31_IRQHandler + .long GPIO2_Combined_0_15_IRQHandler + .long GPIO2_Combined_16_31_IRQHandler + .long GPIO3_Combined_0_15_IRQHandler + .long GPIO3_Combined_16_31_IRQHandler + .long GPIO4_Combined_0_15_IRQHandler + .long GPIO4_Combined_16_31_IRQHandler + .long GPIO5_Combined_0_15_IRQHandler + .long GPIO5_Combined_16_31_IRQHandler + .long FLEXIO1_IRQHandler + .long FLEXIO2_IRQHandler + .long WDOG1_IRQHandler + .long RTWDOG_IRQHandler + .long EWM_IRQHandler + .long CCM_1_IRQHandler + .long CCM_2_IRQHandler + .long GPC_IRQHandler + .long SRC_IRQHandler + .long Reserved115_IRQHandler + .long GPT1_IRQHandler + .long GPT2_IRQHandler + .long PWM1_0_IRQHandler + .long PWM1_1_IRQHandler + .long PWM1_2_IRQHandler + .long PWM1_3_IRQHandler + .long PWM1_FAULT_IRQHandler + .long Reserved123_IRQHandler + .long FLEXSPI_IRQHandler + .long SEMC_IRQHandler + .long USDHC1_IRQHandler + .long USDHC2_IRQHandler + .long USB_OTG2_IRQHandler + .long USB_OTG1_IRQHandler + .long ENET_IRQHandler + .long ENET_1588_Timer_IRQHandler + .long XBAR1_IRQ_0_1_IRQHandler + .long XBAR1_IRQ_2_3_IRQHandler + .long ADC_ETC_IRQ0_IRQHandler + .long ADC_ETC_IRQ1_IRQHandler + .long ADC_ETC_IRQ2_IRQHandler + .long ADC_ETC_ERROR_IRQ_IRQHandler + .long PIT_IRQHandler + .long ACMP1_IRQHandler + .long ACMP2_IRQHandler + .long ACMP3_IRQHandler + .long ACMP4_IRQHandler + .long Reserved143_IRQHandler + .long Reserved144_IRQHandler + .long ENC1_IRQHandler + .long ENC2_IRQHandler + .long ENC3_IRQHandler + .long ENC4_IRQHandler + .long TMR1_IRQHandler + .long TMR2_IRQHandler + .long TMR3_IRQHandler + .long TMR4_IRQHandler + .long PWM2_0_IRQHandler + .long PWM2_1_IRQHandler + .long PWM2_2_IRQHandler + .long PWM2_3_IRQHandler + .long PWM2_FAULT_IRQHandler + .long PWM3_0_IRQHandler + .long PWM3_1_IRQHandler + .long PWM3_2_IRQHandler + .long PWM3_3_IRQHandler + .long PWM3_FAULT_IRQHandler + .long PWM4_0_IRQHandler + .long PWM4_1_IRQHandler + .long PWM4_2_IRQHandler + .long PWM4_3_IRQHandler + .long PWM4_FAULT_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_DMA16_IRQHandler + IRQ DMA1_DMA17_IRQHandler + IRQ DMA2_DMA18_IRQHandler + IRQ DMA3_DMA19_IRQHandler + IRQ DMA4_DMA20_IRQHandler + IRQ DMA5_DMA21_IRQHandler + IRQ DMA6_DMA22_IRQHandler + IRQ DMA7_DMA23_IRQHandler + IRQ DMA8_DMA24_IRQHandler + IRQ DMA9_DMA25_IRQHandler + IRQ DMA10_DMA26_IRQHandler + IRQ DMA11_DMA27_IRQHandler + IRQ DMA12_DMA28_IRQHandler + IRQ DMA13_DMA29_IRQHandler + IRQ DMA14_DMA30_IRQHandler + IRQ DMA15_DMA31_IRQHandler + IRQ DMA_ERROR_IRQHandler + IRQ CTI0_ERROR_IRQHandler + IRQ CTI1_ERROR_IRQHandler + IRQ CORE_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPUART2_IRQHandler + IRQ LPUART3_IRQHandler + IRQ LPUART4_IRQHandler + IRQ LPUART5_IRQHandler + IRQ LPUART6_IRQHandler + IRQ LPUART7_IRQHandler + IRQ LPUART8_IRQHandler + IRQ LPI2C1_IRQHandler + IRQ LPI2C2_IRQHandler + IRQ LPI2C3_IRQHandler + IRQ LPI2C4_IRQHandler + IRQ LPSPI1_IRQHandler + IRQ LPSPI2_IRQHandler + IRQ LPSPI3_IRQHandler + IRQ LPSPI4_IRQHandler + IRQ CAN1_IRQHandler + IRQ CAN2_IRQHandler + IRQ FLEXRAM_IRQHandler + IRQ KPP_IRQHandler + IRQ TSC_DIG_IRQHandler + IRQ GPR_IRQ_IRQHandler + IRQ LCDIF_IRQHandler + IRQ CSI_IRQHandler + IRQ PXP_IRQHandler + IRQ WDOG2_IRQHandler + IRQ SNVS_HP_WRAPPER_IRQHandler + IRQ SNVS_HP_WRAPPER_TZ_IRQHandler + IRQ SNVS_LP_WRAPPER_IRQHandler + IRQ CSU_IRQHandler + IRQ DCP_IRQHandler + IRQ DCP_VMI_IRQHandler + IRQ Reserved68_IRQHandler + IRQ TRNG_IRQHandler + IRQ SJC_IRQHandler + IRQ BEE_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ SAI3_RX_IRQHandler + IRQ SAI3_TX_IRQHandler + IRQ SPDIF_IRQHandler + IRQ PMU_EVENT_IRQHandler + IRQ Reserved78_IRQHandler + IRQ TEMP_LOW_HIGH_IRQHandler + IRQ TEMP_PANIC_IRQHandler + IRQ USB_PHY1_IRQHandler + IRQ USB_PHY2_IRQHandler + IRQ ADC1_IRQHandler + IRQ ADC2_IRQHandler + IRQ DCDC_IRQHandler + IRQ Reserved86_IRQHandler + IRQ Reserved87_IRQHandler + IRQ GPIO1_INT0_IRQHandler + IRQ GPIO1_INT1_IRQHandler + IRQ GPIO1_INT2_IRQHandler + IRQ GPIO1_INT3_IRQHandler + IRQ GPIO1_INT4_IRQHandler + IRQ GPIO1_INT5_IRQHandler + IRQ GPIO1_INT6_IRQHandler + IRQ GPIO1_INT7_IRQHandler + IRQ GPIO1_Combined_0_15_IRQHandler + IRQ GPIO1_Combined_16_31_IRQHandler + IRQ GPIO2_Combined_0_15_IRQHandler + IRQ GPIO2_Combined_16_31_IRQHandler + IRQ GPIO3_Combined_0_15_IRQHandler + IRQ GPIO3_Combined_16_31_IRQHandler + IRQ GPIO4_Combined_0_15_IRQHandler + IRQ GPIO4_Combined_16_31_IRQHandler + IRQ GPIO5_Combined_0_15_IRQHandler + IRQ GPIO5_Combined_16_31_IRQHandler + IRQ FLEXIO1_IRQHandler + IRQ FLEXIO2_IRQHandler + IRQ WDOG1_IRQHandler + IRQ RTWDOG_IRQHandler + IRQ EWM_IRQHandler + IRQ CCM_1_IRQHandler + IRQ CCM_2_IRQHandler + IRQ GPC_IRQHandler + IRQ SRC_IRQHandler + IRQ Reserved115_IRQHandler + IRQ GPT1_IRQHandler + IRQ GPT2_IRQHandler + IRQ PWM1_0_IRQHandler + IRQ PWM1_1_IRQHandler + IRQ PWM1_2_IRQHandler + IRQ PWM1_3_IRQHandler + IRQ PWM1_FAULT_IRQHandler + IRQ Reserved123_IRQHandler + IRQ FLEXSPI_IRQHandler + IRQ SEMC_IRQHandler + IRQ USDHC1_IRQHandler + IRQ USDHC2_IRQHandler + IRQ USB_OTG2_IRQHandler + IRQ USB_OTG1_IRQHandler + IRQ ENET_IRQHandler + IRQ ENET_1588_Timer_IRQHandler + IRQ XBAR1_IRQ_0_1_IRQHandler + IRQ XBAR1_IRQ_2_3_IRQHandler + IRQ ADC_ETC_IRQ0_IRQHandler + IRQ ADC_ETC_IRQ1_IRQHandler + IRQ ADC_ETC_IRQ2_IRQHandler + IRQ ADC_ETC_ERROR_IRQ_IRQHandler + IRQ PIT_IRQHandler + IRQ ACMP1_IRQHandler + IRQ ACMP2_IRQHandler + IRQ ACMP3_IRQHandler + IRQ ACMP4_IRQHandler + IRQ Reserved143_IRQHandler + IRQ Reserved144_IRQHandler + IRQ ENC1_IRQHandler + IRQ ENC2_IRQHandler + IRQ ENC3_IRQHandler + IRQ ENC4_IRQHandler + IRQ TMR1_IRQHandler + IRQ TMR2_IRQHandler + IRQ TMR3_IRQHandler + IRQ TMR4_IRQHandler + IRQ PWM2_0_IRQHandler + IRQ PWM2_1_IRQHandler + IRQ PWM2_2_IRQHandler + IRQ PWM2_3_IRQHandler + IRQ PWM2_FAULT_IRQHandler + IRQ PWM3_0_IRQHandler + IRQ PWM3_1_IRQHandler + IRQ PWM3_2_IRQHandler + IRQ PWM3_3_IRQHandler + IRQ PWM3_FAULT_IRQHandler + IRQ PWM4_0_IRQHandler + IRQ PWM4_1_IRQHandler + IRQ PWM4_2_IRQHandler + IRQ PWM4_3_IRQHandler + IRQ PWM4_FAULT_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mimxrt1062.s b/targets/device/nxp/mimxrt1062.s new file mode 100644 index 00000000..03936bb8 --- /dev/null +++ b/targets/device/nxp/mimxrt1062.s @@ -0,0 +1,383 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MIMXRT1062.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MIMXRT1062DVL6A +*/ + +// Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_DMA16_IRQHandler + .long DMA1_DMA17_IRQHandler + .long DMA2_DMA18_IRQHandler + .long DMA3_DMA19_IRQHandler + .long DMA4_DMA20_IRQHandler + .long DMA5_DMA21_IRQHandler + .long DMA6_DMA22_IRQHandler + .long DMA7_DMA23_IRQHandler + .long DMA8_DMA24_IRQHandler + .long DMA9_DMA25_IRQHandler + .long DMA10_DMA26_IRQHandler + .long DMA11_DMA27_IRQHandler + .long DMA12_DMA28_IRQHandler + .long DMA13_DMA29_IRQHandler + .long DMA14_DMA30_IRQHandler + .long DMA15_DMA31_IRQHandler + .long DMA_ERROR_IRQHandler + .long CTI0_ERROR_IRQHandler + .long CTI1_ERROR_IRQHandler + .long CORE_IRQHandler + .long LPUART1_IRQHandler + .long LPUART2_IRQHandler + .long LPUART3_IRQHandler + .long LPUART4_IRQHandler + .long LPUART5_IRQHandler + .long LPUART6_IRQHandler + .long LPUART7_IRQHandler + .long LPUART8_IRQHandler + .long LPI2C1_IRQHandler + .long LPI2C2_IRQHandler + .long LPI2C3_IRQHandler + .long LPI2C4_IRQHandler + .long LPSPI1_IRQHandler + .long LPSPI2_IRQHandler + .long LPSPI3_IRQHandler + .long LPSPI4_IRQHandler + .long CAN1_IRQHandler + .long CAN2_IRQHandler + .long FLEXRAM_IRQHandler + .long KPP_IRQHandler + .long TSC_DIG_IRQHandler + .long GPR_IRQ_IRQHandler + .long LCDIF_IRQHandler + .long CSI_IRQHandler + .long PXP_IRQHandler + .long WDOG2_IRQHandler + .long SNVS_HP_WRAPPER_IRQHandler + .long SNVS_HP_WRAPPER_TZ_IRQHandler + .long SNVS_LP_WRAPPER_IRQHandler + .long CSU_IRQHandler + .long DCP_IRQHandler + .long DCP_VMI_IRQHandler + .long Reserved68_IRQHandler + .long TRNG_IRQHandler + .long SJC_IRQHandler + .long BEE_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long SAI3_RX_IRQHandler + .long SAI3_TX_IRQHandler + .long SPDIF_IRQHandler + .long PMU_EVENT_IRQHandler + .long Reserved78_IRQHandler + .long TEMP_LOW_HIGH_IRQHandler + .long TEMP_PANIC_IRQHandler + .long USB_PHY1_IRQHandler + .long USB_PHY2_IRQHandler + .long ADC1_IRQHandler + .long ADC2_IRQHandler + .long DCDC_IRQHandler + .long Reserved86_IRQHandler + .long Reserved87_IRQHandler + .long GPIO1_INT0_IRQHandler + .long GPIO1_INT1_IRQHandler + .long GPIO1_INT2_IRQHandler + .long GPIO1_INT3_IRQHandler + .long GPIO1_INT4_IRQHandler + .long GPIO1_INT5_IRQHandler + .long GPIO1_INT6_IRQHandler + .long GPIO1_INT7_IRQHandler + .long GPIO1_Combined_0_15_IRQHandler + .long GPIO1_Combined_16_31_IRQHandler + .long GPIO2_Combined_0_15_IRQHandler + .long GPIO2_Combined_16_31_IRQHandler + .long GPIO3_Combined_0_15_IRQHandler + .long GPIO3_Combined_16_31_IRQHandler + .long GPIO4_Combined_0_15_IRQHandler + .long GPIO4_Combined_16_31_IRQHandler + .long GPIO5_Combined_0_15_IRQHandler + .long GPIO5_Combined_16_31_IRQHandler + .long FLEXIO1_IRQHandler + .long FLEXIO2_IRQHandler + .long WDOG1_IRQHandler + .long RTWDOG_IRQHandler + .long EWM_IRQHandler + .long CCM_1_IRQHandler + .long CCM_2_IRQHandler + .long GPC_IRQHandler + .long SRC_IRQHandler + .long Reserved115_IRQHandler + .long GPT1_IRQHandler + .long GPT2_IRQHandler + .long PWM1_0_IRQHandler + .long PWM1_1_IRQHandler + .long PWM1_2_IRQHandler + .long PWM1_3_IRQHandler + .long PWM1_FAULT_IRQHandler + .long FLEXSPI2_IRQHandler + .long FLEXSPI_IRQHandler + .long SEMC_IRQHandler + .long USDHC1_IRQHandler + .long USDHC2_IRQHandler + .long USB_OTG2_IRQHandler + .long USB_OTG1_IRQHandler + .long ENET_IRQHandler + .long ENET_1588_Timer_IRQHandler + .long XBAR1_IRQ_0_1_IRQHandler + .long XBAR1_IRQ_2_3_IRQHandler + .long ADC_ETC_IRQ0_IRQHandler + .long ADC_ETC_IRQ1_IRQHandler + .long ADC_ETC_IRQ2_IRQHandler + .long ADC_ETC_ERROR_IRQ_IRQHandler + .long PIT_IRQHandler + .long ACMP1_IRQHandler + .long ACMP2_IRQHandler + .long ACMP3_IRQHandler + .long ACMP4_IRQHandler + .long Reserved143_IRQHandler + .long Reserved144_IRQHandler + .long ENC1_IRQHandler + .long ENC2_IRQHandler + .long ENC3_IRQHandler + .long ENC4_IRQHandler + .long TMR1_IRQHandler + .long TMR2_IRQHandler + .long TMR3_IRQHandler + .long TMR4_IRQHandler + .long PWM2_0_IRQHandler + .long PWM2_1_IRQHandler + .long PWM2_2_IRQHandler + .long PWM2_3_IRQHandler + .long PWM2_FAULT_IRQHandler + .long PWM3_0_IRQHandler + .long PWM3_1_IRQHandler + .long PWM3_2_IRQHandler + .long PWM3_3_IRQHandler + .long PWM3_FAULT_IRQHandler + .long PWM4_0_IRQHandler + .long PWM4_1_IRQHandler + .long PWM4_2_IRQHandler + .long PWM4_3_IRQHandler + .long PWM4_FAULT_IRQHandler + .long ENET2_IRQHandler + .long ENET2_1588_Timer_IRQHandler + .long CAN3_IRQHandler + .long Reserved171_IRQHandler + .long FLEXIO3_IRQHandler + .long GPIO6_7_8_9_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_DMA16_IRQHandler + IRQ DMA1_DMA17_IRQHandler + IRQ DMA2_DMA18_IRQHandler + IRQ DMA3_DMA19_IRQHandler + IRQ DMA4_DMA20_IRQHandler + IRQ DMA5_DMA21_IRQHandler + IRQ DMA6_DMA22_IRQHandler + IRQ DMA7_DMA23_IRQHandler + IRQ DMA8_DMA24_IRQHandler + IRQ DMA9_DMA25_IRQHandler + IRQ DMA10_DMA26_IRQHandler + IRQ DMA11_DMA27_IRQHandler + IRQ DMA12_DMA28_IRQHandler + IRQ DMA13_DMA29_IRQHandler + IRQ DMA14_DMA30_IRQHandler + IRQ DMA15_DMA31_IRQHandler + IRQ DMA_ERROR_IRQHandler + IRQ CTI0_ERROR_IRQHandler + IRQ CTI1_ERROR_IRQHandler + IRQ CORE_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPUART2_IRQHandler + IRQ LPUART3_IRQHandler + IRQ LPUART4_IRQHandler + IRQ LPUART5_IRQHandler + IRQ LPUART6_IRQHandler + IRQ LPUART7_IRQHandler + IRQ LPUART8_IRQHandler + IRQ LPI2C1_IRQHandler + IRQ LPI2C2_IRQHandler + IRQ LPI2C3_IRQHandler + IRQ LPI2C4_IRQHandler + IRQ LPSPI1_IRQHandler + IRQ LPSPI2_IRQHandler + IRQ LPSPI3_IRQHandler + IRQ LPSPI4_IRQHandler + IRQ CAN1_IRQHandler + IRQ CAN2_IRQHandler + IRQ FLEXRAM_IRQHandler + IRQ KPP_IRQHandler + IRQ TSC_DIG_IRQHandler + IRQ GPR_IRQ_IRQHandler + IRQ LCDIF_IRQHandler + IRQ CSI_IRQHandler + IRQ PXP_IRQHandler + IRQ WDOG2_IRQHandler + IRQ SNVS_HP_WRAPPER_IRQHandler + IRQ SNVS_HP_WRAPPER_TZ_IRQHandler + IRQ SNVS_LP_WRAPPER_IRQHandler + IRQ CSU_IRQHandler + IRQ DCP_IRQHandler + IRQ DCP_VMI_IRQHandler + IRQ Reserved68_IRQHandler + IRQ TRNG_IRQHandler + IRQ SJC_IRQHandler + IRQ BEE_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ SAI3_RX_IRQHandler + IRQ SAI3_TX_IRQHandler + IRQ SPDIF_IRQHandler + IRQ PMU_EVENT_IRQHandler + IRQ Reserved78_IRQHandler + IRQ TEMP_LOW_HIGH_IRQHandler + IRQ TEMP_PANIC_IRQHandler + IRQ USB_PHY1_IRQHandler + IRQ USB_PHY2_IRQHandler + IRQ ADC1_IRQHandler + IRQ ADC2_IRQHandler + IRQ DCDC_IRQHandler + IRQ Reserved86_IRQHandler + IRQ Reserved87_IRQHandler + IRQ GPIO1_INT0_IRQHandler + IRQ GPIO1_INT1_IRQHandler + IRQ GPIO1_INT2_IRQHandler + IRQ GPIO1_INT3_IRQHandler + IRQ GPIO1_INT4_IRQHandler + IRQ GPIO1_INT5_IRQHandler + IRQ GPIO1_INT6_IRQHandler + IRQ GPIO1_INT7_IRQHandler + IRQ GPIO1_Combined_0_15_IRQHandler + IRQ GPIO1_Combined_16_31_IRQHandler + IRQ GPIO2_Combined_0_15_IRQHandler + IRQ GPIO2_Combined_16_31_IRQHandler + IRQ GPIO3_Combined_0_15_IRQHandler + IRQ GPIO3_Combined_16_31_IRQHandler + IRQ GPIO4_Combined_0_15_IRQHandler + IRQ GPIO4_Combined_16_31_IRQHandler + IRQ GPIO5_Combined_0_15_IRQHandler + IRQ GPIO5_Combined_16_31_IRQHandler + IRQ FLEXIO1_IRQHandler + IRQ FLEXIO2_IRQHandler + IRQ WDOG1_IRQHandler + IRQ RTWDOG_IRQHandler + IRQ EWM_IRQHandler + IRQ CCM_1_IRQHandler + IRQ CCM_2_IRQHandler + IRQ GPC_IRQHandler + IRQ SRC_IRQHandler + IRQ Reserved115_IRQHandler + IRQ GPT1_IRQHandler + IRQ GPT2_IRQHandler + IRQ PWM1_0_IRQHandler + IRQ PWM1_1_IRQHandler + IRQ PWM1_2_IRQHandler + IRQ PWM1_3_IRQHandler + IRQ PWM1_FAULT_IRQHandler + IRQ FLEXSPI2_IRQHandler + IRQ FLEXSPI_IRQHandler + IRQ SEMC_IRQHandler + IRQ USDHC1_IRQHandler + IRQ USDHC2_IRQHandler + IRQ USB_OTG2_IRQHandler + IRQ USB_OTG1_IRQHandler + IRQ ENET_IRQHandler + IRQ ENET_1588_Timer_IRQHandler + IRQ XBAR1_IRQ_0_1_IRQHandler + IRQ XBAR1_IRQ_2_3_IRQHandler + IRQ ADC_ETC_IRQ0_IRQHandler + IRQ ADC_ETC_IRQ1_IRQHandler + IRQ ADC_ETC_IRQ2_IRQHandler + IRQ ADC_ETC_ERROR_IRQ_IRQHandler + IRQ PIT_IRQHandler + IRQ ACMP1_IRQHandler + IRQ ACMP2_IRQHandler + IRQ ACMP3_IRQHandler + IRQ ACMP4_IRQHandler + IRQ Reserved143_IRQHandler + IRQ Reserved144_IRQHandler + IRQ ENC1_IRQHandler + IRQ ENC2_IRQHandler + IRQ ENC3_IRQHandler + IRQ ENC4_IRQHandler + IRQ TMR1_IRQHandler + IRQ TMR2_IRQHandler + IRQ TMR3_IRQHandler + IRQ TMR4_IRQHandler + IRQ PWM2_0_IRQHandler + IRQ PWM2_1_IRQHandler + IRQ PWM2_2_IRQHandler + IRQ PWM2_3_IRQHandler + IRQ PWM2_FAULT_IRQHandler + IRQ PWM3_0_IRQHandler + IRQ PWM3_1_IRQHandler + IRQ PWM3_2_IRQHandler + IRQ PWM3_3_IRQHandler + IRQ PWM3_FAULT_IRQHandler + IRQ PWM4_0_IRQHandler + IRQ PWM4_1_IRQHandler + IRQ PWM4_2_IRQHandler + IRQ PWM4_3_IRQHandler + IRQ PWM4_FAULT_IRQHandler + IRQ ENET2_IRQHandler + IRQ ENET2_1588_Timer_IRQHandler + IRQ CAN3_IRQHandler + IRQ Reserved171_IRQHandler + IRQ FLEXIO3_IRQHandler + IRQ GPIO6_7_8_9_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mimxrt1064.s b/targets/device/nxp/mimxrt1064.s new file mode 100644 index 00000000..6cdcfee9 --- /dev/null +++ b/targets/device/nxp/mimxrt1064.s @@ -0,0 +1,383 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MIMXRT1064.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MIMXRT1064DVL6A +*/ + +// Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_DMA16_IRQHandler + .long DMA1_DMA17_IRQHandler + .long DMA2_DMA18_IRQHandler + .long DMA3_DMA19_IRQHandler + .long DMA4_DMA20_IRQHandler + .long DMA5_DMA21_IRQHandler + .long DMA6_DMA22_IRQHandler + .long DMA7_DMA23_IRQHandler + .long DMA8_DMA24_IRQHandler + .long DMA9_DMA25_IRQHandler + .long DMA10_DMA26_IRQHandler + .long DMA11_DMA27_IRQHandler + .long DMA12_DMA28_IRQHandler + .long DMA13_DMA29_IRQHandler + .long DMA14_DMA30_IRQHandler + .long DMA15_DMA31_IRQHandler + .long DMA_ERROR_IRQHandler + .long CTI0_ERROR_IRQHandler + .long CTI1_ERROR_IRQHandler + .long CORE_IRQHandler + .long LPUART1_IRQHandler + .long LPUART2_IRQHandler + .long LPUART3_IRQHandler + .long LPUART4_IRQHandler + .long LPUART5_IRQHandler + .long LPUART6_IRQHandler + .long LPUART7_IRQHandler + .long LPUART8_IRQHandler + .long LPI2C1_IRQHandler + .long LPI2C2_IRQHandler + .long LPI2C3_IRQHandler + .long LPI2C4_IRQHandler + .long LPSPI1_IRQHandler + .long LPSPI2_IRQHandler + .long LPSPI3_IRQHandler + .long LPSPI4_IRQHandler + .long CAN1_IRQHandler + .long CAN2_IRQHandler + .long FLEXRAM_IRQHandler + .long KPP_IRQHandler + .long TSC_DIG_IRQHandler + .long GPR_IRQ_IRQHandler + .long LCDIF_IRQHandler + .long CSI_IRQHandler + .long PXP_IRQHandler + .long WDOG2_IRQHandler + .long SNVS_HP_WRAPPER_IRQHandler + .long SNVS_HP_WRAPPER_TZ_IRQHandler + .long SNVS_LP_WRAPPER_IRQHandler + .long CSU_IRQHandler + .long DCP_IRQHandler + .long DCP_VMI_IRQHandler + .long Reserved68_IRQHandler + .long TRNG_IRQHandler + .long SJC_IRQHandler + .long BEE_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long SAI3_RX_IRQHandler + .long SAI3_TX_IRQHandler + .long SPDIF_IRQHandler + .long PMU_EVENT_IRQHandler + .long Reserved78_IRQHandler + .long TEMP_LOW_HIGH_IRQHandler + .long TEMP_PANIC_IRQHandler + .long USB_PHY1_IRQHandler + .long USB_PHY2_IRQHandler + .long ADC1_IRQHandler + .long ADC2_IRQHandler + .long DCDC_IRQHandler + .long Reserved86_IRQHandler + .long Reserved87_IRQHandler + .long GPIO1_INT0_IRQHandler + .long GPIO1_INT1_IRQHandler + .long GPIO1_INT2_IRQHandler + .long GPIO1_INT3_IRQHandler + .long GPIO1_INT4_IRQHandler + .long GPIO1_INT5_IRQHandler + .long GPIO1_INT6_IRQHandler + .long GPIO1_INT7_IRQHandler + .long GPIO1_Combined_0_15_IRQHandler + .long GPIO1_Combined_16_31_IRQHandler + .long GPIO2_Combined_0_15_IRQHandler + .long GPIO2_Combined_16_31_IRQHandler + .long GPIO3_Combined_0_15_IRQHandler + .long GPIO3_Combined_16_31_IRQHandler + .long GPIO4_Combined_0_15_IRQHandler + .long GPIO4_Combined_16_31_IRQHandler + .long GPIO5_Combined_0_15_IRQHandler + .long GPIO5_Combined_16_31_IRQHandler + .long FLEXIO1_IRQHandler + .long FLEXIO2_IRQHandler + .long WDOG1_IRQHandler + .long RTWDOG_IRQHandler + .long EWM_IRQHandler + .long CCM_1_IRQHandler + .long CCM_2_IRQHandler + .long GPC_IRQHandler + .long SRC_IRQHandler + .long Reserved115_IRQHandler + .long GPT1_IRQHandler + .long GPT2_IRQHandler + .long PWM1_0_IRQHandler + .long PWM1_1_IRQHandler + .long PWM1_2_IRQHandler + .long PWM1_3_IRQHandler + .long PWM1_FAULT_IRQHandler + .long FLEXSPI2_IRQHandler + .long FLEXSPI_IRQHandler + .long SEMC_IRQHandler + .long USDHC1_IRQHandler + .long USDHC2_IRQHandler + .long USB_OTG2_IRQHandler + .long USB_OTG1_IRQHandler + .long ENET_IRQHandler + .long ENET_1588_Timer_IRQHandler + .long XBAR1_IRQ_0_1_IRQHandler + .long XBAR1_IRQ_2_3_IRQHandler + .long ADC_ETC_IRQ0_IRQHandler + .long ADC_ETC_IRQ1_IRQHandler + .long ADC_ETC_IRQ2_IRQHandler + .long ADC_ETC_ERROR_IRQ_IRQHandler + .long PIT_IRQHandler + .long ACMP1_IRQHandler + .long ACMP2_IRQHandler + .long ACMP3_IRQHandler + .long ACMP4_IRQHandler + .long Reserved143_IRQHandler + .long Reserved144_IRQHandler + .long ENC1_IRQHandler + .long ENC2_IRQHandler + .long ENC3_IRQHandler + .long ENC4_IRQHandler + .long TMR1_IRQHandler + .long TMR2_IRQHandler + .long TMR3_IRQHandler + .long TMR4_IRQHandler + .long PWM2_0_IRQHandler + .long PWM2_1_IRQHandler + .long PWM2_2_IRQHandler + .long PWM2_3_IRQHandler + .long PWM2_FAULT_IRQHandler + .long PWM3_0_IRQHandler + .long PWM3_1_IRQHandler + .long PWM3_2_IRQHandler + .long PWM3_3_IRQHandler + .long PWM3_FAULT_IRQHandler + .long PWM4_0_IRQHandler + .long PWM4_1_IRQHandler + .long PWM4_2_IRQHandler + .long PWM4_3_IRQHandler + .long PWM4_FAULT_IRQHandler + .long ENET2_IRQHandler + .long ENET2_1588_Timer_IRQHandler + .long CAN3_IRQHandler + .long Reserved171_IRQHandler + .long FLEXIO3_IRQHandler + .long GPIO6_7_8_9_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_DMA16_IRQHandler + IRQ DMA1_DMA17_IRQHandler + IRQ DMA2_DMA18_IRQHandler + IRQ DMA3_DMA19_IRQHandler + IRQ DMA4_DMA20_IRQHandler + IRQ DMA5_DMA21_IRQHandler + IRQ DMA6_DMA22_IRQHandler + IRQ DMA7_DMA23_IRQHandler + IRQ DMA8_DMA24_IRQHandler + IRQ DMA9_DMA25_IRQHandler + IRQ DMA10_DMA26_IRQHandler + IRQ DMA11_DMA27_IRQHandler + IRQ DMA12_DMA28_IRQHandler + IRQ DMA13_DMA29_IRQHandler + IRQ DMA14_DMA30_IRQHandler + IRQ DMA15_DMA31_IRQHandler + IRQ DMA_ERROR_IRQHandler + IRQ CTI0_ERROR_IRQHandler + IRQ CTI1_ERROR_IRQHandler + IRQ CORE_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPUART2_IRQHandler + IRQ LPUART3_IRQHandler + IRQ LPUART4_IRQHandler + IRQ LPUART5_IRQHandler + IRQ LPUART6_IRQHandler + IRQ LPUART7_IRQHandler + IRQ LPUART8_IRQHandler + IRQ LPI2C1_IRQHandler + IRQ LPI2C2_IRQHandler + IRQ LPI2C3_IRQHandler + IRQ LPI2C4_IRQHandler + IRQ LPSPI1_IRQHandler + IRQ LPSPI2_IRQHandler + IRQ LPSPI3_IRQHandler + IRQ LPSPI4_IRQHandler + IRQ CAN1_IRQHandler + IRQ CAN2_IRQHandler + IRQ FLEXRAM_IRQHandler + IRQ KPP_IRQHandler + IRQ TSC_DIG_IRQHandler + IRQ GPR_IRQ_IRQHandler + IRQ LCDIF_IRQHandler + IRQ CSI_IRQHandler + IRQ PXP_IRQHandler + IRQ WDOG2_IRQHandler + IRQ SNVS_HP_WRAPPER_IRQHandler + IRQ SNVS_HP_WRAPPER_TZ_IRQHandler + IRQ SNVS_LP_WRAPPER_IRQHandler + IRQ CSU_IRQHandler + IRQ DCP_IRQHandler + IRQ DCP_VMI_IRQHandler + IRQ Reserved68_IRQHandler + IRQ TRNG_IRQHandler + IRQ SJC_IRQHandler + IRQ BEE_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ SAI3_RX_IRQHandler + IRQ SAI3_TX_IRQHandler + IRQ SPDIF_IRQHandler + IRQ PMU_EVENT_IRQHandler + IRQ Reserved78_IRQHandler + IRQ TEMP_LOW_HIGH_IRQHandler + IRQ TEMP_PANIC_IRQHandler + IRQ USB_PHY1_IRQHandler + IRQ USB_PHY2_IRQHandler + IRQ ADC1_IRQHandler + IRQ ADC2_IRQHandler + IRQ DCDC_IRQHandler + IRQ Reserved86_IRQHandler + IRQ Reserved87_IRQHandler + IRQ GPIO1_INT0_IRQHandler + IRQ GPIO1_INT1_IRQHandler + IRQ GPIO1_INT2_IRQHandler + IRQ GPIO1_INT3_IRQHandler + IRQ GPIO1_INT4_IRQHandler + IRQ GPIO1_INT5_IRQHandler + IRQ GPIO1_INT6_IRQHandler + IRQ GPIO1_INT7_IRQHandler + IRQ GPIO1_Combined_0_15_IRQHandler + IRQ GPIO1_Combined_16_31_IRQHandler + IRQ GPIO2_Combined_0_15_IRQHandler + IRQ GPIO2_Combined_16_31_IRQHandler + IRQ GPIO3_Combined_0_15_IRQHandler + IRQ GPIO3_Combined_16_31_IRQHandler + IRQ GPIO4_Combined_0_15_IRQHandler + IRQ GPIO4_Combined_16_31_IRQHandler + IRQ GPIO5_Combined_0_15_IRQHandler + IRQ GPIO5_Combined_16_31_IRQHandler + IRQ FLEXIO1_IRQHandler + IRQ FLEXIO2_IRQHandler + IRQ WDOG1_IRQHandler + IRQ RTWDOG_IRQHandler + IRQ EWM_IRQHandler + IRQ CCM_1_IRQHandler + IRQ CCM_2_IRQHandler + IRQ GPC_IRQHandler + IRQ SRC_IRQHandler + IRQ Reserved115_IRQHandler + IRQ GPT1_IRQHandler + IRQ GPT2_IRQHandler + IRQ PWM1_0_IRQHandler + IRQ PWM1_1_IRQHandler + IRQ PWM1_2_IRQHandler + IRQ PWM1_3_IRQHandler + IRQ PWM1_FAULT_IRQHandler + IRQ FLEXSPI2_IRQHandler + IRQ FLEXSPI_IRQHandler + IRQ SEMC_IRQHandler + IRQ USDHC1_IRQHandler + IRQ USDHC2_IRQHandler + IRQ USB_OTG2_IRQHandler + IRQ USB_OTG1_IRQHandler + IRQ ENET_IRQHandler + IRQ ENET_1588_Timer_IRQHandler + IRQ XBAR1_IRQ_0_1_IRQHandler + IRQ XBAR1_IRQ_2_3_IRQHandler + IRQ ADC_ETC_IRQ0_IRQHandler + IRQ ADC_ETC_IRQ1_IRQHandler + IRQ ADC_ETC_IRQ2_IRQHandler + IRQ ADC_ETC_ERROR_IRQ_IRQHandler + IRQ PIT_IRQHandler + IRQ ACMP1_IRQHandler + IRQ ACMP2_IRQHandler + IRQ ACMP3_IRQHandler + IRQ ACMP4_IRQHandler + IRQ Reserved143_IRQHandler + IRQ Reserved144_IRQHandler + IRQ ENC1_IRQHandler + IRQ ENC2_IRQHandler + IRQ ENC3_IRQHandler + IRQ ENC4_IRQHandler + IRQ TMR1_IRQHandler + IRQ TMR2_IRQHandler + IRQ TMR3_IRQHandler + IRQ TMR4_IRQHandler + IRQ PWM2_0_IRQHandler + IRQ PWM2_1_IRQHandler + IRQ PWM2_2_IRQHandler + IRQ PWM2_3_IRQHandler + IRQ PWM2_FAULT_IRQHandler + IRQ PWM3_0_IRQHandler + IRQ PWM3_1_IRQHandler + IRQ PWM3_2_IRQHandler + IRQ PWM3_3_IRQHandler + IRQ PWM3_FAULT_IRQHandler + IRQ PWM4_0_IRQHandler + IRQ PWM4_1_IRQHandler + IRQ PWM4_2_IRQHandler + IRQ PWM4_3_IRQHandler + IRQ PWM4_FAULT_IRQHandler + IRQ ENET2_IRQHandler + IRQ ENET2_1588_Timer_IRQHandler + IRQ CAN3_IRQHandler + IRQ Reserved171_IRQHandler + IRQ FLEXIO3_IRQHandler + IRQ GPIO6_7_8_9_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mk22f25612.s b/targets/device/nxp/mk22f25612.s new file mode 100644 index 00000000..0dec90d2 --- /dev/null +++ b/targets/device/nxp/mk22f25612.s @@ -0,0 +1,218 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MK22F25612.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MK22F25612 NXP Microcontroller +*/ + +// Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met: +// o Redistributions of source code must retain the above copyright notice, this list +// of conditions and the following disclaimer. +// o Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// o Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_IRQHandler + .long DMA1_IRQHandler + .long DMA2_IRQHandler + .long DMA3_IRQHandler + .long DMA4_IRQHandler + .long DMA5_IRQHandler + .long DMA6_IRQHandler + .long DMA7_IRQHandler + .long DMA8_IRQHandler + .long DMA9_IRQHandler + .long DMA10_IRQHandler + .long DMA11_IRQHandler + .long DMA12_IRQHandler + .long DMA13_IRQHandler + .long DMA14_IRQHandler + .long DMA15_IRQHandler + .long DMA_Error_IRQHandler + .long MCM_IRQHandler + .long FTF_IRQHandler + .long Read_Collision_IRQHandler + .long LVD_LVW_IRQHandler + .long LLWU_IRQHandler + .long WDOG_EWM_IRQHandler + .long RNG_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long I2S0_Tx_IRQHandler + .long I2S0_Rx_IRQHandler + .long LPUART0_IRQHandler + .long UART0_RX_TX_IRQHandler + .long UART0_ERR_IRQHandler + .long UART1_RX_TX_IRQHandler + .long UART1_ERR_IRQHandler + .long UART2_RX_TX_IRQHandler + .long UART2_ERR_IRQHandler + .long 0 + .long 0 + .long ADC0_IRQHandler + .long CMP0_IRQHandler + .long CMP1_IRQHandler + .long FTM0_IRQHandler + .long FTM1_IRQHandler + .long FTM2_IRQHandler + .long 0 + .long RTC_IRQHandler + .long RTC_Seconds_IRQHandler + .long PIT0_IRQHandler + .long PIT1_IRQHandler + .long PIT2_IRQHandler + .long PIT3_IRQHandler + .long PDB0_IRQHandler + .long USB0_IRQHandler + .long 0 + .long 0 + .long DAC0_IRQHandler + .long 0 + .long LPTMR0_IRQHandler + .long PORTA_IRQHandler + .long PORTB_IRQHandler + .long PORTC_IRQHandler + .long PORTD_IRQHandler + .long PORTE_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long ADC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_IRQHandler + IRQ DMA1_IRQHandler + IRQ DMA2_IRQHandler + IRQ DMA3_IRQHandler + IRQ DMA4_IRQHandler + IRQ DMA5_IRQHandler + IRQ DMA6_IRQHandler + IRQ DMA7_IRQHandler + IRQ DMA8_IRQHandler + IRQ DMA9_IRQHandler + IRQ DMA10_IRQHandler + IRQ DMA11_IRQHandler + IRQ DMA12_IRQHandler + IRQ DMA13_IRQHandler + IRQ DMA14_IRQHandler + IRQ DMA15_IRQHandler + IRQ DMA_Error_IRQHandler + IRQ MCM_IRQHandler + IRQ FTF_IRQHandler + IRQ Read_Collision_IRQHandler + IRQ LVD_LVW_IRQHandler + IRQ LLWU_IRQHandler + IRQ WDOG_EWM_IRQHandler + IRQ RNG_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ I2S0_Tx_IRQHandler + IRQ I2S0_Rx_IRQHandler + IRQ LPUART0_IRQHandler + IRQ UART0_RX_TX_IRQHandler + IRQ UART0_ERR_IRQHandler + IRQ UART1_RX_TX_IRQHandler + IRQ UART1_ERR_IRQHandler + IRQ UART2_RX_TX_IRQHandler + IRQ UART2_ERR_IRQHandler + IRQ ADC0_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ FTM0_IRQHandler + IRQ FTM1_IRQHandler + IRQ FTM2_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_Seconds_IRQHandler + IRQ PIT0_IRQHandler + IRQ PIT1_IRQHandler + IRQ PIT2_IRQHandler + IRQ PIT3_IRQHandler + IRQ PDB0_IRQHandler + IRQ USB0_IRQHandler + IRQ DAC0_IRQHandler + IRQ LPTMR0_IRQHandler + IRQ PORTA_IRQHandler + IRQ PORTB_IRQHandler + IRQ PORTC_IRQHandler + IRQ PORTD_IRQHandler + IRQ PORTE_IRQHandler + IRQ ADC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mk22f51212.s b/targets/device/nxp/mk22f51212.s new file mode 100644 index 00000000..94f267fc --- /dev/null +++ b/targets/device/nxp/mk22f51212.s @@ -0,0 +1,220 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MK22F51212.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MK22F51212 NXP Microcontroller +*/ + +// Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met: +// o Redistributions of source code must retain the above copyright notice, this list +// of conditions and the following disclaimer. +// o Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// o Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_IRQHandler + .long DMA1_IRQHandler + .long DMA2_IRQHandler + .long DMA3_IRQHandler + .long DMA4_IRQHandler + .long DMA5_IRQHandler + .long DMA6_IRQHandler + .long DMA7_IRQHandler + .long DMA8_IRQHandler + .long DMA9_IRQHandler + .long DMA10_IRQHandler + .long DMA11_IRQHandler + .long DMA12_IRQHandler + .long DMA13_IRQHandler + .long DMA14_IRQHandler + .long DMA15_IRQHandler + .long DMA_Error_IRQHandler + .long MCM_IRQHandler + .long FTF_IRQHandler + .long Read_Collision_IRQHandler + .long LVD_LVW_IRQHandler + .long LLWU_IRQHandler + .long WDOG_EWM_IRQHandler + .long RNG_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long I2S0_Tx_IRQHandler + .long I2S0_Rx_IRQHandler + .long LPUART0_IRQHandler + .long UART0_RX_TX_IRQHandler + .long UART0_ERR_IRQHandler + .long UART1_RX_TX_IRQHandler + .long UART1_ERR_IRQHandler + .long UART2_RX_TX_IRQHandler + .long UART2_ERR_IRQHandler + .long 0 + .long 0 + .long ADC0_IRQHandler + .long CMP0_IRQHandler + .long CMP1_IRQHandler + .long FTM0_IRQHandler + .long FTM1_IRQHandler + .long FTM2_IRQHandler + .long 0 + .long RTC_IRQHandler + .long RTC_Seconds_IRQHandler + .long PIT0_IRQHandler + .long PIT1_IRQHandler + .long PIT2_IRQHandler + .long PIT3_IRQHandler + .long PDB0_IRQHandler + .long USB0_IRQHandler + .long 0 + .long 0 + .long DAC0_IRQHandler + .long 0 + .long LPTMR0_IRQHandler + .long PORTA_IRQHandler + .long PORTB_IRQHandler + .long PORTC_IRQHandler + .long PORTD_IRQHandler + .long PORTE_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long FTM3_IRQHandler + .long DAC1_IRQHandler + .long ADC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_IRQHandler + IRQ DMA1_IRQHandler + IRQ DMA2_IRQHandler + IRQ DMA3_IRQHandler + IRQ DMA4_IRQHandler + IRQ DMA5_IRQHandler + IRQ DMA6_IRQHandler + IRQ DMA7_IRQHandler + IRQ DMA8_IRQHandler + IRQ DMA9_IRQHandler + IRQ DMA10_IRQHandler + IRQ DMA11_IRQHandler + IRQ DMA12_IRQHandler + IRQ DMA13_IRQHandler + IRQ DMA14_IRQHandler + IRQ DMA15_IRQHandler + IRQ DMA_Error_IRQHandler + IRQ MCM_IRQHandler + IRQ FTF_IRQHandler + IRQ Read_Collision_IRQHandler + IRQ LVD_LVW_IRQHandler + IRQ LLWU_IRQHandler + IRQ WDOG_EWM_IRQHandler + IRQ RNG_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ I2S0_Tx_IRQHandler + IRQ I2S0_Rx_IRQHandler + IRQ LPUART0_IRQHandler + IRQ UART0_RX_TX_IRQHandler + IRQ UART0_ERR_IRQHandler + IRQ UART1_RX_TX_IRQHandler + IRQ UART1_ERR_IRQHandler + IRQ UART2_RX_TX_IRQHandler + IRQ UART2_ERR_IRQHandler + IRQ ADC0_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ FTM0_IRQHandler + IRQ FTM1_IRQHandler + IRQ FTM2_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_Seconds_IRQHandler + IRQ PIT0_IRQHandler + IRQ PIT1_IRQHandler + IRQ PIT2_IRQHandler + IRQ PIT3_IRQHandler + IRQ PDB0_IRQHandler + IRQ USB0_IRQHandler + IRQ DAC0_IRQHandler + IRQ LPTMR0_IRQHandler + IRQ PORTA_IRQHandler + IRQ PORTB_IRQHandler + IRQ PORTC_IRQHandler + IRQ PORTD_IRQHandler + IRQ PORTE_IRQHandler + IRQ FTM3_IRQHandler + IRQ DAC1_IRQHandler + IRQ ADC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mk64f12.s b/targets/device/nxp/mk64f12.s new file mode 100644 index 00000000..c5822cec --- /dev/null +++ b/targets/device/nxp/mk64f12.s @@ -0,0 +1,236 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MK64F12.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MK64F12 NXP Microcontroller +*/ + +// Copyright 2016-2018 NXP SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_IRQHandler + .long DMA1_IRQHandler + .long DMA2_IRQHandler + .long DMA3_IRQHandler + .long DMA4_IRQHandler + .long DMA5_IRQHandler + .long DMA6_IRQHandler + .long DMA7_IRQHandler + .long DMA8_IRQHandler + .long DMA9_IRQHandler + .long DMA10_IRQHandler + .long DMA11_IRQHandler + .long DMA12_IRQHandler + .long DMA13_IRQHandler + .long DMA14_IRQHandler + .long DMA15_IRQHandler + .long DMA_Error_IRQHandler + .long MCM_IRQHandler + .long FTFE_IRQHandler + .long Read_Collision_IRQHandler + .long LVD_LVW_IRQHandler + .long LLWU_IRQHandler + .long WDOG_EWM_IRQHandler + .long RNG_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long I2S0_Tx_IRQHandler + .long I2S0_Rx_IRQHandler + .long UART0_LON_IRQHandler + .long UART0_RX_TX_IRQHandler + .long UART0_ERR_IRQHandler + .long UART1_RX_TX_IRQHandler + .long UART1_ERR_IRQHandler + .long UART2_RX_TX_IRQHandler + .long UART2_ERR_IRQHandler + .long UART3_RX_TX_IRQHandler + .long UART3_ERR_IRQHandler + .long ADC0_IRQHandler + .long CMP0_IRQHandler + .long CMP1_IRQHandler + .long FTM0_IRQHandler + .long FTM1_IRQHandler + .long FTM2_IRQHandler + .long CMT_IRQHandler + .long RTC_IRQHandler + .long RTC_Seconds_IRQHandler + .long PIT0_IRQHandler + .long PIT1_IRQHandler + .long PIT2_IRQHandler + .long PIT3_IRQHandler + .long PDB0_IRQHandler + .long USB0_IRQHandler + .long USBDCD_IRQHandler + .long 0 + .long DAC0_IRQHandler + .long 0 + .long LPTMR0_IRQHandler + .long PORTA_IRQHandler + .long PORTB_IRQHandler + .long PORTC_IRQHandler + .long PORTD_IRQHandler + .long PORTE_IRQHandler + .long 0 + .long SPI2_IRQHandler + .long UART4_RX_TX_IRQHandler + .long UART4_ERR_IRQHandler + .long UART5_RX_TX_IRQHandler + .long UART5_ERR_IRQHandler + .long CMP2_IRQHandler + .long FTM3_IRQHandler + .long DAC1_IRQHandler + .long ADC1_IRQHandler + .long I2C2_IRQHandler + .long CAN0_ORed_Message_buffer_IRQHandler + .long CAN0_Bus_Off_IRQHandler + .long CAN0_Error_IRQHandler + .long CAN0_Tx_Warning_IRQHandler + .long CAN0_Rx_Warning_IRQHandler + .long CAN0_Wake_Up_IRQHandler + .long SDHC_IRQHandler + .long ENET_1588_Timer_IRQHandler + .long ENET_Transmit_IRQHandler + .long ENET_Receive_IRQHandler + .long ENET_Error_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_IRQHandler + IRQ DMA1_IRQHandler + IRQ DMA2_IRQHandler + IRQ DMA3_IRQHandler + IRQ DMA4_IRQHandler + IRQ DMA5_IRQHandler + IRQ DMA6_IRQHandler + IRQ DMA7_IRQHandler + IRQ DMA8_IRQHandler + IRQ DMA9_IRQHandler + IRQ DMA10_IRQHandler + IRQ DMA11_IRQHandler + IRQ DMA12_IRQHandler + IRQ DMA13_IRQHandler + IRQ DMA14_IRQHandler + IRQ DMA15_IRQHandler + IRQ DMA_Error_IRQHandler + IRQ MCM_IRQHandler + IRQ FTFE_IRQHandler + IRQ Read_Collision_IRQHandler + IRQ LVD_LVW_IRQHandler + IRQ LLWU_IRQHandler + IRQ WDOG_EWM_IRQHandler + IRQ RNG_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ I2S0_Tx_IRQHandler + IRQ I2S0_Rx_IRQHandler + IRQ UART0_LON_IRQHandler + IRQ UART0_RX_TX_IRQHandler + IRQ UART0_ERR_IRQHandler + IRQ UART1_RX_TX_IRQHandler + IRQ UART1_ERR_IRQHandler + IRQ UART2_RX_TX_IRQHandler + IRQ UART2_ERR_IRQHandler + IRQ UART3_RX_TX_IRQHandler + IRQ UART3_ERR_IRQHandler + IRQ ADC0_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ FTM0_IRQHandler + IRQ FTM1_IRQHandler + IRQ FTM2_IRQHandler + IRQ CMT_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_Seconds_IRQHandler + IRQ PIT0_IRQHandler + IRQ PIT1_IRQHandler + IRQ PIT2_IRQHandler + IRQ PIT3_IRQHandler + IRQ PDB0_IRQHandler + IRQ USB0_IRQHandler + IRQ USBDCD_IRQHandler + IRQ DAC0_IRQHandler + IRQ LPTMR0_IRQHandler + IRQ PORTA_IRQHandler + IRQ PORTB_IRQHandler + IRQ PORTC_IRQHandler + IRQ PORTD_IRQHandler + IRQ PORTE_IRQHandler + IRQ SPI2_IRQHandler + IRQ UART4_RX_TX_IRQHandler + IRQ UART4_ERR_IRQHandler + IRQ UART5_RX_TX_IRQHandler + IRQ UART5_ERR_IRQHandler + IRQ CMP2_IRQHandler + IRQ FTM3_IRQHandler + IRQ DAC1_IRQHandler + IRQ ADC1_IRQHandler + IRQ I2C2_IRQHandler + IRQ CAN0_ORed_Message_buffer_IRQHandler + IRQ CAN0_Bus_Off_IRQHandler + IRQ CAN0_Error_IRQHandler + IRQ CAN0_Tx_Warning_IRQHandler + IRQ CAN0_Rx_Warning_IRQHandler + IRQ CAN0_Wake_Up_IRQHandler + IRQ SDHC_IRQHandler + IRQ ENET_1588_Timer_IRQHandler + IRQ ENET_Transmit_IRQHandler + IRQ ENET_Receive_IRQHandler + IRQ ENET_Error_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mk65f18.s b/targets/device/nxp/mk65f18.s new file mode 100644 index 00000000..07b6f82d --- /dev/null +++ b/targets/device/nxp/mk65f18.s @@ -0,0 +1,261 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MK65F18.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MK65F18 NXP Microcontroller +*/ + +// Copyright 2016-2018 NXP SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_DMA16_IRQHandler + .long DMA1_DMA17_IRQHandler + .long DMA2_DMA18_IRQHandler + .long DMA3_DMA19_IRQHandler + .long DMA4_DMA20_IRQHandler + .long DMA5_DMA21_IRQHandler + .long DMA6_DMA22_IRQHandler + .long DMA7_DMA23_IRQHandler + .long DMA8_DMA24_IRQHandler + .long DMA9_DMA25_IRQHandler + .long DMA10_DMA26_IRQHandler + .long DMA11_DMA27_IRQHandler + .long DMA12_DMA28_IRQHandler + .long DMA13_DMA29_IRQHandler + .long DMA14_DMA30_IRQHandler + .long DMA15_DMA31_IRQHandler + .long DMA_Error_IRQHandler + .long MCM_IRQHandler + .long FTFE_IRQHandler + .long Read_Collision_IRQHandler + .long LVD_LVW_IRQHandler + .long LLWU_IRQHandler + .long WDOG_EWM_IRQHandler + .long RNG_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long I2S0_Tx_IRQHandler + .long I2S0_Rx_IRQHandler + .long 0 + .long UART0_RX_TX_IRQHandler + .long UART0_ERR_IRQHandler + .long UART1_RX_TX_IRQHandler + .long UART1_ERR_IRQHandler + .long UART2_RX_TX_IRQHandler + .long UART2_ERR_IRQHandler + .long UART3_RX_TX_IRQHandler + .long UART3_ERR_IRQHandler + .long ADC0_IRQHandler + .long CMP0_IRQHandler + .long CMP1_IRQHandler + .long FTM0_IRQHandler + .long FTM1_IRQHandler + .long FTM2_IRQHandler + .long CMT_IRQHandler + .long RTC_IRQHandler + .long RTC_Seconds_IRQHandler + .long PIT0_IRQHandler + .long PIT1_IRQHandler + .long PIT2_IRQHandler + .long PIT3_IRQHandler + .long PDB0_IRQHandler + .long USB0_IRQHandler + .long USBDCD_IRQHandler + .long 0 + .long DAC0_IRQHandler + .long 0 + .long LPTMR0_IRQHandler + .long PORTA_IRQHandler + .long PORTB_IRQHandler + .long PORTC_IRQHandler + .long PORTD_IRQHandler + .long PORTE_IRQHandler + .long 0 + .long SPI2_IRQHandler + .long UART4_RX_TX_IRQHandler + .long UART4_ERR_IRQHandler + .long 0 + .long 0 + .long CMP2_IRQHandler + .long FTM3_IRQHandler + .long DAC1_IRQHandler + .long ADC1_IRQHandler + .long I2C2_IRQHandler + .long CAN0_ORed_Message_buffer_IRQHandler + .long CAN0_Bus_Off_IRQHandler + .long CAN0_Error_IRQHandler + .long CAN0_Tx_Warning_IRQHandler + .long CAN0_Rx_Warning_IRQHandler + .long CAN0_Wake_Up_IRQHandler + .long SDHC_IRQHandler + .long ENET_1588_Timer_IRQHandler + .long ENET_Transmit_IRQHandler + .long ENET_Receive_IRQHandler + .long ENET_Error_IRQHandler + .long LPUART0_IRQHandler + .long TSI0_IRQHandler + .long TPM1_IRQHandler + .long TPM2_IRQHandler + .long USBHSDCD_IRQHandler + .long I2C3_IRQHandler + .long CMP3_IRQHandler + .long USBHS_IRQHandler + .long CAN1_ORed_Message_buffer_IRQHandler + .long CAN1_Bus_Off_IRQHandler + .long CAN1_Error_IRQHandler + .long CAN1_Tx_Warning_IRQHandler + .long CAN1_Rx_Warning_IRQHandler + .long CAN1_Wake_Up_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_DMA16_IRQHandler + IRQ DMA1_DMA17_IRQHandler + IRQ DMA2_DMA18_IRQHandler + IRQ DMA3_DMA19_IRQHandler + IRQ DMA4_DMA20_IRQHandler + IRQ DMA5_DMA21_IRQHandler + IRQ DMA6_DMA22_IRQHandler + IRQ DMA7_DMA23_IRQHandler + IRQ DMA8_DMA24_IRQHandler + IRQ DMA9_DMA25_IRQHandler + IRQ DMA10_DMA26_IRQHandler + IRQ DMA11_DMA27_IRQHandler + IRQ DMA12_DMA28_IRQHandler + IRQ DMA13_DMA29_IRQHandler + IRQ DMA14_DMA30_IRQHandler + IRQ DMA15_DMA31_IRQHandler + IRQ DMA_Error_IRQHandler + IRQ MCM_IRQHandler + IRQ FTFE_IRQHandler + IRQ Read_Collision_IRQHandler + IRQ LVD_LVW_IRQHandler + IRQ LLWU_IRQHandler + IRQ WDOG_EWM_IRQHandler + IRQ RNG_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ I2S0_Tx_IRQHandler + IRQ I2S0_Rx_IRQHandler + IRQ UART0_RX_TX_IRQHandler + IRQ UART0_ERR_IRQHandler + IRQ UART1_RX_TX_IRQHandler + IRQ UART1_ERR_IRQHandler + IRQ UART2_RX_TX_IRQHandler + IRQ UART2_ERR_IRQHandler + IRQ UART3_RX_TX_IRQHandler + IRQ UART3_ERR_IRQHandler + IRQ ADC0_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ FTM0_IRQHandler + IRQ FTM1_IRQHandler + IRQ FTM2_IRQHandler + IRQ CMT_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_Seconds_IRQHandler + IRQ PIT0_IRQHandler + IRQ PIT1_IRQHandler + IRQ PIT2_IRQHandler + IRQ PIT3_IRQHandler + IRQ PDB0_IRQHandler + IRQ USB0_IRQHandler + IRQ USBDCD_IRQHandler + IRQ DAC0_IRQHandler + IRQ LPTMR0_IRQHandler + IRQ PORTA_IRQHandler + IRQ PORTB_IRQHandler + IRQ PORTC_IRQHandler + IRQ PORTD_IRQHandler + IRQ PORTE_IRQHandler + IRQ SPI2_IRQHandler + IRQ UART4_RX_TX_IRQHandler + IRQ UART4_ERR_IRQHandler + IRQ CMP2_IRQHandler + IRQ FTM3_IRQHandler + IRQ DAC1_IRQHandler + IRQ ADC1_IRQHandler + IRQ I2C2_IRQHandler + IRQ CAN0_ORed_Message_buffer_IRQHandler + IRQ CAN0_Bus_Off_IRQHandler + IRQ CAN0_Error_IRQHandler + IRQ CAN0_Tx_Warning_IRQHandler + IRQ CAN0_Rx_Warning_IRQHandler + IRQ CAN0_Wake_Up_IRQHandler + IRQ SDHC_IRQHandler + IRQ ENET_1588_Timer_IRQHandler + IRQ ENET_Transmit_IRQHandler + IRQ ENET_Receive_IRQHandler + IRQ ENET_Error_IRQHandler + IRQ LPUART0_IRQHandler + IRQ TSI0_IRQHandler + IRQ TPM1_IRQHandler + IRQ TPM2_IRQHandler + IRQ USBHSDCD_IRQHandler + IRQ I2C3_IRQHandler + IRQ CMP3_IRQHandler + IRQ USBHS_IRQHandler + IRQ CAN1_ORed_Message_buffer_IRQHandler + IRQ CAN1_Bus_Off_IRQHandler + IRQ CAN1_Error_IRQHandler + IRQ CAN1_Tx_Warning_IRQHandler + IRQ CAN1_Rx_Warning_IRQHandler + IRQ CAN1_Wake_Up_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mk66f18.s b/targets/device/nxp/mk66f18.s new file mode 100644 index 00000000..4f5fa906 --- /dev/null +++ b/targets/device/nxp/mk66f18.s @@ -0,0 +1,261 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MK66F18.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MK66F18 NXP Microcontroller +*/ + +// Copyright 2016-2018 NXP SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_DMA16_IRQHandler + .long DMA1_DMA17_IRQHandler + .long DMA2_DMA18_IRQHandler + .long DMA3_DMA19_IRQHandler + .long DMA4_DMA20_IRQHandler + .long DMA5_DMA21_IRQHandler + .long DMA6_DMA22_IRQHandler + .long DMA7_DMA23_IRQHandler + .long DMA8_DMA24_IRQHandler + .long DMA9_DMA25_IRQHandler + .long DMA10_DMA26_IRQHandler + .long DMA11_DMA27_IRQHandler + .long DMA12_DMA28_IRQHandler + .long DMA13_DMA29_IRQHandler + .long DMA14_DMA30_IRQHandler + .long DMA15_DMA31_IRQHandler + .long DMA_Error_IRQHandler + .long MCM_IRQHandler + .long FTFE_IRQHandler + .long Read_Collision_IRQHandler + .long LVD_LVW_IRQHandler + .long LLWU_IRQHandler + .long WDOG_EWM_IRQHandler + .long RNG_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long I2S0_Tx_IRQHandler + .long I2S0_Rx_IRQHandler + .long 0 + .long UART0_RX_TX_IRQHandler + .long UART0_ERR_IRQHandler + .long UART1_RX_TX_IRQHandler + .long UART1_ERR_IRQHandler + .long UART2_RX_TX_IRQHandler + .long UART2_ERR_IRQHandler + .long UART3_RX_TX_IRQHandler + .long UART3_ERR_IRQHandler + .long ADC0_IRQHandler + .long CMP0_IRQHandler + .long CMP1_IRQHandler + .long FTM0_IRQHandler + .long FTM1_IRQHandler + .long FTM2_IRQHandler + .long CMT_IRQHandler + .long RTC_IRQHandler + .long RTC_Seconds_IRQHandler + .long PIT0_IRQHandler + .long PIT1_IRQHandler + .long PIT2_IRQHandler + .long PIT3_IRQHandler + .long PDB0_IRQHandler + .long USB0_IRQHandler + .long USBDCD_IRQHandler + .long 0 + .long DAC0_IRQHandler + .long 0 + .long LPTMR0_IRQHandler + .long PORTA_IRQHandler + .long PORTB_IRQHandler + .long PORTC_IRQHandler + .long PORTD_IRQHandler + .long PORTE_IRQHandler + .long 0 + .long SPI2_IRQHandler + .long UART4_RX_TX_IRQHandler + .long UART4_ERR_IRQHandler + .long 0 + .long 0 + .long CMP2_IRQHandler + .long FTM3_IRQHandler + .long DAC1_IRQHandler + .long ADC1_IRQHandler + .long I2C2_IRQHandler + .long CAN0_ORed_Message_buffer_IRQHandler + .long CAN0_Bus_Off_IRQHandler + .long CAN0_Error_IRQHandler + .long CAN0_Tx_Warning_IRQHandler + .long CAN0_Rx_Warning_IRQHandler + .long CAN0_Wake_Up_IRQHandler + .long SDHC_IRQHandler + .long ENET_1588_Timer_IRQHandler + .long ENET_Transmit_IRQHandler + .long ENET_Receive_IRQHandler + .long ENET_Error_IRQHandler + .long LPUART0_IRQHandler + .long TSI0_IRQHandler + .long TPM1_IRQHandler + .long TPM2_IRQHandler + .long USBHSDCD_IRQHandler + .long I2C3_IRQHandler + .long CMP3_IRQHandler + .long USBHS_IRQHandler + .long CAN1_ORed_Message_buffer_IRQHandler + .long CAN1_Bus_Off_IRQHandler + .long CAN1_Error_IRQHandler + .long CAN1_Tx_Warning_IRQHandler + .long CAN1_Rx_Warning_IRQHandler + .long CAN1_Wake_Up_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_DMA16_IRQHandler + IRQ DMA1_DMA17_IRQHandler + IRQ DMA2_DMA18_IRQHandler + IRQ DMA3_DMA19_IRQHandler + IRQ DMA4_DMA20_IRQHandler + IRQ DMA5_DMA21_IRQHandler + IRQ DMA6_DMA22_IRQHandler + IRQ DMA7_DMA23_IRQHandler + IRQ DMA8_DMA24_IRQHandler + IRQ DMA9_DMA25_IRQHandler + IRQ DMA10_DMA26_IRQHandler + IRQ DMA11_DMA27_IRQHandler + IRQ DMA12_DMA28_IRQHandler + IRQ DMA13_DMA29_IRQHandler + IRQ DMA14_DMA30_IRQHandler + IRQ DMA15_DMA31_IRQHandler + IRQ DMA_Error_IRQHandler + IRQ MCM_IRQHandler + IRQ FTFE_IRQHandler + IRQ Read_Collision_IRQHandler + IRQ LVD_LVW_IRQHandler + IRQ LLWU_IRQHandler + IRQ WDOG_EWM_IRQHandler + IRQ RNG_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ I2S0_Tx_IRQHandler + IRQ I2S0_Rx_IRQHandler + IRQ UART0_RX_TX_IRQHandler + IRQ UART0_ERR_IRQHandler + IRQ UART1_RX_TX_IRQHandler + IRQ UART1_ERR_IRQHandler + IRQ UART2_RX_TX_IRQHandler + IRQ UART2_ERR_IRQHandler + IRQ UART3_RX_TX_IRQHandler + IRQ UART3_ERR_IRQHandler + IRQ ADC0_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ FTM0_IRQHandler + IRQ FTM1_IRQHandler + IRQ FTM2_IRQHandler + IRQ CMT_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_Seconds_IRQHandler + IRQ PIT0_IRQHandler + IRQ PIT1_IRQHandler + IRQ PIT2_IRQHandler + IRQ PIT3_IRQHandler + IRQ PDB0_IRQHandler + IRQ USB0_IRQHandler + IRQ USBDCD_IRQHandler + IRQ DAC0_IRQHandler + IRQ LPTMR0_IRQHandler + IRQ PORTA_IRQHandler + IRQ PORTB_IRQHandler + IRQ PORTC_IRQHandler + IRQ PORTD_IRQHandler + IRQ PORTE_IRQHandler + IRQ SPI2_IRQHandler + IRQ UART4_RX_TX_IRQHandler + IRQ UART4_ERR_IRQHandler + IRQ CMP2_IRQHandler + IRQ FTM3_IRQHandler + IRQ DAC1_IRQHandler + IRQ ADC1_IRQHandler + IRQ I2C2_IRQHandler + IRQ CAN0_ORed_Message_buffer_IRQHandler + IRQ CAN0_Bus_Off_IRQHandler + IRQ CAN0_Error_IRQHandler + IRQ CAN0_Tx_Warning_IRQHandler + IRQ CAN0_Rx_Warning_IRQHandler + IRQ CAN0_Wake_Up_IRQHandler + IRQ SDHC_IRQHandler + IRQ ENET_1588_Timer_IRQHandler + IRQ ENET_Transmit_IRQHandler + IRQ ENET_Receive_IRQHandler + IRQ ENET_Error_IRQHandler + IRQ LPUART0_IRQHandler + IRQ TSI0_IRQHandler + IRQ TPM1_IRQHandler + IRQ TPM2_IRQHandler + IRQ USBHSDCD_IRQHandler + IRQ I2C3_IRQHandler + IRQ CMP3_IRQHandler + IRQ USBHS_IRQHandler + IRQ CAN1_ORed_Message_buffer_IRQHandler + IRQ CAN1_Bus_Off_IRQHandler + IRQ CAN1_Error_IRQHandler + IRQ CAN1_Tx_Warning_IRQHandler + IRQ CAN1_Rx_Warning_IRQHandler + IRQ CAN1_Wake_Up_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mkl26z4.s b/targets/device/nxp/mkl26z4.s new file mode 100644 index 00000000..86e29121 --- /dev/null +++ b/targets/device/nxp/mkl26z4.s @@ -0,0 +1,147 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MKL26Z4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MKL26Z4 NXP Microcontroller +*/ + +// Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met: +// o Redistributions of source code must retain the above copyright notice, this list +// of conditions and the following disclaimer. +// o Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// o Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_IRQHandler + .long DMA1_IRQHandler + .long DMA2_IRQHandler + .long DMA3_IRQHandler + .long 0 + .long FTFA_IRQHandler + .long LVD_LVW_IRQHandler + .long LLWU_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long UART2_IRQHandler + .long ADC0_IRQHandler + .long CMP0_IRQHandler + .long TPM0_IRQHandler + .long TPM1_IRQHandler + .long TPM2_IRQHandler + .long RTC_IRQHandler + .long RTC_Seconds_IRQHandler + .long PIT_IRQHandler + .long I2S0_IRQHandler + .long USB0_IRQHandler + .long DAC0_IRQHandler + .long TSI0_IRQHandler + .long MCG_IRQHandler + .long LPTMR0_IRQHandler + .long 0 + .long PORTA_IRQHandler + .long PORTC_PORTD_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_IRQHandler + IRQ DMA1_IRQHandler + IRQ DMA2_IRQHandler + IRQ DMA3_IRQHandler + IRQ FTFA_IRQHandler + IRQ LVD_LVW_IRQHandler + IRQ LLWU_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ ADC0_IRQHandler + IRQ CMP0_IRQHandler + IRQ TPM0_IRQHandler + IRQ TPM1_IRQHandler + IRQ TPM2_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_Seconds_IRQHandler + IRQ PIT_IRQHandler + IRQ I2S0_IRQHandler + IRQ USB0_IRQHandler + IRQ DAC0_IRQHandler + IRQ TSI0_IRQHandler + IRQ MCG_IRQHandler + IRQ LPTMR0_IRQHandler + IRQ PORTA_IRQHandler + IRQ PORTC_PORTD_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/mkw41z4.s b/targets/device/nxp/mkw41z4.s new file mode 100644 index 00000000..b14a74cd --- /dev/null +++ b/targets/device/nxp/mkw41z4.s @@ -0,0 +1,146 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from MKW41Z4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// MKW41Z4 NXP Microcontroller +*/ + +// Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met: +// o Redistributions of source code must retain the above copyright notice, this list +// of conditions and the following disclaimer. +// o Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// o Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long DMA0_IRQHandler + .long DMA1_IRQHandler + .long DMA2_IRQHandler + .long DMA3_IRQHandler + .long 0 + .long FTFA_IRQHandler + .long LVD_LVW_DCDC_IRQHandler + .long LLWU_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long SPI0_IRQHandler + .long TSI0_IRQHandler + .long LPUART0_IRQHandler + .long TRNG0_IRQHandler + .long CMT_IRQHandler + .long ADC0_IRQHandler + .long CMP0_IRQHandler + .long TPM0_IRQHandler + .long TPM1_IRQHandler + .long TPM2_IRQHandler + .long RTC_IRQHandler + .long RTC_Seconds_IRQHandler + .long PIT_IRQHandler + .long LTC0_IRQHandler + .long 0 + .long DAC0_IRQHandler + .long 0 + .long MCG_IRQHandler + .long LPTMR0_IRQHandler + .long SPI1_IRQHandler + .long PORTA_IRQHandler + .long PORTB_PORTC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ DMA0_IRQHandler + IRQ DMA1_IRQHandler + IRQ DMA2_IRQHandler + IRQ DMA3_IRQHandler + IRQ FTFA_IRQHandler + IRQ LVD_LVW_DCDC_IRQHandler + IRQ LLWU_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ TSI0_IRQHandler + IRQ LPUART0_IRQHandler + IRQ TRNG0_IRQHandler + IRQ CMT_IRQHandler + IRQ ADC0_IRQHandler + IRQ CMP0_IRQHandler + IRQ TPM0_IRQHandler + IRQ TPM1_IRQHandler + IRQ TPM2_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_Seconds_IRQHandler + IRQ PIT_IRQHandler + IRQ LTC0_IRQHandler + IRQ DAC0_IRQHandler + IRQ MCG_IRQHandler + IRQ LPTMR0_IRQHandler + IRQ SPI1_IRQHandler + IRQ PORTA_IRQHandler + IRQ PORTB_PORTC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/neom3.s b/targets/device/nxp/neom3.s new file mode 100644 index 00000000..bf363a61 --- /dev/null +++ b/targets/device/nxp/neom3.s @@ -0,0 +1,145 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from LPC178x_7x_v0.8.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// Neo M3 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDT_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long TIMER3_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long PWM1_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long 0 + .long SSP0_IRQHandler + .long SSP1_IRQHandler + .long 0 + .long RTC_IRQHandler + .long EINT0_IRQHandler + .long EINT1_IRQHandler + .long EINT2_IRQHandler + .long EINT3_IRQHandler + .long ADC_IRQHandler + .long BOD_IRQHandler + .long USB_IRQHandler + .long CAN_IRQHandler + .long GPDMA_IRQHandler + .long I2S_IRQHandler + .long ETHERNET_IRQHandler + .long SDMMC_IRQHandler + .long MCPWM_IRQHandler + .long QEI_IRQHandler + .long 0 + .long USB_NEED_CLK_IRQHandler + .long 0 + .long UART4_IRQHandler + .long SSP2_IRQHandler + .long LCD_IRQHandler + .long GPIOINT_IRQHandler + .long PWM0_IRQHandler + .long EEPROM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDT_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER3_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ PWM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SSP0_IRQHandler + IRQ SSP1_IRQHandler + IRQ RTC_IRQHandler + IRQ EINT0_IRQHandler + IRQ EINT1_IRQHandler + IRQ EINT2_IRQHandler + IRQ EINT3_IRQHandler + IRQ ADC_IRQHandler + IRQ BOD_IRQHandler + IRQ USB_IRQHandler + IRQ CAN_IRQHandler + IRQ GPDMA_IRQHandler + IRQ I2S_IRQHandler + IRQ ETHERNET_IRQHandler + IRQ SDMMC_IRQHandler + IRQ MCPWM_IRQHandler + IRQ QEI_IRQHandler + IRQ USB_NEED_CLK_IRQHandler + IRQ UART4_IRQHandler + IRQ SSP2_IRQHandler + IRQ LCD_IRQHandler + IRQ GPIOINT_IRQHandler + IRQ PWM0_IRQHandler + IRQ EEPROM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/nxp/qn908xc.s b/targets/device/nxp/qn908xc.s new file mode 100644 index 00000000..abcd7060 --- /dev/null +++ b/targets/device/nxp/qn908xc.s @@ -0,0 +1,67 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from QN908XC.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP + +/* +// QN9080C, QN9083C +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa2a1ab.s b/targets/device/renesas/r7fa2a1ab.s new file mode 100644 index 00000000..b93cf1cd --- /dev/null +++ b/targets/device/renesas/r7fa2a1ab.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA2A1AB.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// ARM 32-bit Cortex-M23 Microcontroller based device, CPU clock up to 48MHz, etc. +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa2e1a9.s b/targets/device/renesas/r7fa2e1a9.s new file mode 100644 index 00000000..17262dca --- /dev/null +++ b/targets/device/renesas/r7fa2e1a9.s @@ -0,0 +1,149 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA2E1A9.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M23 based Microcontroller RA2E1 device +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa2e2a7.s b/targets/device/renesas/r7fa2e2a7.s new file mode 100644 index 00000000..c9bb2437 --- /dev/null +++ b/targets/device/renesas/r7fa2e2a7.s @@ -0,0 +1,149 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA2E2A7.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M23 based Microcontroller RA2E2 device +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa2l1ab.s b/targets/device/renesas/r7fa2l1ab.s new file mode 100644 index 00000000..45e5a386 --- /dev/null +++ b/targets/device/renesas/r7fa2l1ab.s @@ -0,0 +1,149 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA2L1AB.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M23 based Microcontroller RA2L1 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa4e10d.s b/targets/device/renesas/r7fa4e10d.s new file mode 100644 index 00000000..ce8ca704 --- /dev/null +++ b/targets/device/renesas/r7fa4e10d.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA4E10D.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA4E1 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa4e2b9.s b/targets/device/renesas/r7fa4e2b9.s new file mode 100644 index 00000000..2dcb98e2 --- /dev/null +++ b/targets/device/renesas/r7fa4e2b9.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA4E2B9.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA4E2 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa4m1ab.s b/targets/device/renesas/r7fa4m1ab.s new file mode 100644 index 00000000..d079e6b8 --- /dev/null +++ b/targets/device/renesas/r7fa4m1ab.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA4M1AB.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 48MHz, etc. +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa4m2ad.s b/targets/device/renesas/r7fa4m2ad.s new file mode 100644 index 00000000..edae6989 --- /dev/null +++ b/targets/device/renesas/r7fa4m2ad.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA4M2AD.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA4M2 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa4m3af.s b/targets/device/renesas/r7fa4m3af.s new file mode 100644 index 00000000..26ec0536 --- /dev/null +++ b/targets/device/renesas/r7fa4m3af.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA4M3AF.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA4M3 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa4t1bb.s b/targets/device/renesas/r7fa4t1bb.s new file mode 100644 index 00000000..88287520 --- /dev/null +++ b/targets/device/renesas/r7fa4t1bb.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA4T1BB.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA4T1 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa4w1ad.s b/targets/device/renesas/r7fa4w1ad.s new file mode 100644 index 00000000..3296386c --- /dev/null +++ b/targets/device/renesas/r7fa4w1ad.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA4W1AD.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 48MHz, etc. +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6e10f.s b/targets/device/renesas/r7fa6e10f.s new file mode 100644 index 00000000..82eab9e9 --- /dev/null +++ b/targets/device/renesas/r7fa6e10f.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6E10F.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA6E1 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6e2bb.s b/targets/device/renesas/r7fa6e2bb.s new file mode 100644 index 00000000..c5037968 --- /dev/null +++ b/targets/device/renesas/r7fa6e2bb.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6E2BB.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA6E2 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6m1ad.s b/targets/device/renesas/r7fa6m1ad.s new file mode 100644 index 00000000..4e593061 --- /dev/null +++ b/targets/device/renesas/r7fa6m1ad.s @@ -0,0 +1,259 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6M1AD.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 120MHz, etc. +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6m2af.s b/targets/device/renesas/r7fa6m2af.s new file mode 100644 index 00000000..3a58e064 --- /dev/null +++ b/targets/device/renesas/r7fa6m2af.s @@ -0,0 +1,259 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6M2AF.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 120MHz, etc. +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6m3ah.s b/targets/device/renesas/r7fa6m3ah.s new file mode 100644 index 00000000..e8985a80 --- /dev/null +++ b/targets/device/renesas/r7fa6m3ah.s @@ -0,0 +1,259 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6M3AH.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 120MHz, etc. +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6m4af.s b/targets/device/renesas/r7fa6m4af.s new file mode 100644 index 00000000..ce4a87d0 --- /dev/null +++ b/targets/device/renesas/r7fa6m4af.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6M4AF.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA6M4 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6m5bh.s b/targets/device/renesas/r7fa6m5bh.s new file mode 100644 index 00000000..e637e827 --- /dev/null +++ b/targets/device/renesas/r7fa6m5bh.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6M5BH.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA6M5 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6t1ad.s b/targets/device/renesas/r7fa6t1ad.s new file mode 100644 index 00000000..24101f1f --- /dev/null +++ b/targets/device/renesas/r7fa6t1ad.s @@ -0,0 +1,259 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6T1AD.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 120MHz, etc. +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6t2bd.s b/targets/device/renesas/r7fa6t2bd.s new file mode 100644 index 00000000..de58f92e --- /dev/null +++ b/targets/device/renesas/r7fa6t2bd.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6T2BD.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA6T2 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/renesas/r7fa6t3bb.s b/targets/device/renesas/r7fa6t3bb.s new file mode 100644 index 00000000..25f915f0 --- /dev/null +++ b/targets/device/renesas/r7fa6t3bb.s @@ -0,0 +1,277 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from R7FA6T3BB.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas + +/* +// Arm Cortex-M33 based Microcontroller RA6T3 group +*/ + +// This software is supplied by Renesas Electronics Corporation and is only intended for +// use with Renesas products. No other uses are authorized. This software is owned by +// Renesas Electronics Corporation and is protected under all applicable laws, including +// copyright laws. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +// THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +// ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT +// PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED +// COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +// DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +// +// Renesas reserves the right, without notice, to make changes to this software and to +// discontinue the availability of this software. By using this software, you agree to +// the additional terms and conditions found by accessing the following link: +// http://www.renesas.com/disclaimer +// \n + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long IEL0_IRQHandler + .long IEL1_IRQHandler + .long IEL2_IRQHandler + .long IEL3_IRQHandler + .long IEL4_IRQHandler + .long IEL5_IRQHandler + .long IEL6_IRQHandler + .long IEL7_IRQHandler + .long IEL8_IRQHandler + .long IEL9_IRQHandler + .long IEL10_IRQHandler + .long IEL11_IRQHandler + .long IEL12_IRQHandler + .long IEL13_IRQHandler + .long IEL14_IRQHandler + .long IEL15_IRQHandler + .long IEL16_IRQHandler + .long IEL17_IRQHandler + .long IEL18_IRQHandler + .long IEL19_IRQHandler + .long IEL20_IRQHandler + .long IEL21_IRQHandler + .long IEL22_IRQHandler + .long IEL23_IRQHandler + .long IEL24_IRQHandler + .long IEL25_IRQHandler + .long IEL26_IRQHandler + .long IEL27_IRQHandler + .long IEL28_IRQHandler + .long IEL29_IRQHandler + .long IEL30_IRQHandler + .long IEL31_IRQHandler + .long IEL32_IRQHandler + .long IEL33_IRQHandler + .long IEL34_IRQHandler + .long IEL35_IRQHandler + .long IEL36_IRQHandler + .long IEL37_IRQHandler + .long IEL38_IRQHandler + .long IEL39_IRQHandler + .long IEL40_IRQHandler + .long IEL41_IRQHandler + .long IEL42_IRQHandler + .long IEL43_IRQHandler + .long IEL44_IRQHandler + .long IEL45_IRQHandler + .long IEL46_IRQHandler + .long IEL47_IRQHandler + .long IEL48_IRQHandler + .long IEL49_IRQHandler + .long IEL50_IRQHandler + .long IEL51_IRQHandler + .long IEL52_IRQHandler + .long IEL53_IRQHandler + .long IEL54_IRQHandler + .long IEL55_IRQHandler + .long IEL56_IRQHandler + .long IEL57_IRQHandler + .long IEL58_IRQHandler + .long IEL59_IRQHandler + .long IEL60_IRQHandler + .long IEL61_IRQHandler + .long IEL62_IRQHandler + .long IEL63_IRQHandler + .long IEL64_IRQHandler + .long IEL65_IRQHandler + .long IEL66_IRQHandler + .long IEL67_IRQHandler + .long IEL68_IRQHandler + .long IEL69_IRQHandler + .long IEL70_IRQHandler + .long IEL71_IRQHandler + .long IEL72_IRQHandler + .long IEL73_IRQHandler + .long IEL74_IRQHandler + .long IEL75_IRQHandler + .long IEL76_IRQHandler + .long IEL77_IRQHandler + .long IEL78_IRQHandler + .long IEL79_IRQHandler + .long IEL80_IRQHandler + .long IEL81_IRQHandler + .long IEL82_IRQHandler + .long IEL83_IRQHandler + .long IEL84_IRQHandler + .long IEL85_IRQHandler + .long IEL86_IRQHandler + .long IEL87_IRQHandler + .long IEL88_IRQHandler + .long IEL89_IRQHandler + .long IEL90_IRQHandler + .long IEL91_IRQHandler + .long IEL92_IRQHandler + .long IEL93_IRQHandler + .long IEL94_IRQHandler + .long IEL95_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ IEL0_IRQHandler + IRQ IEL1_IRQHandler + IRQ IEL2_IRQHandler + IRQ IEL3_IRQHandler + IRQ IEL4_IRQHandler + IRQ IEL5_IRQHandler + IRQ IEL6_IRQHandler + IRQ IEL7_IRQHandler + IRQ IEL8_IRQHandler + IRQ IEL9_IRQHandler + IRQ IEL10_IRQHandler + IRQ IEL11_IRQHandler + IRQ IEL12_IRQHandler + IRQ IEL13_IRQHandler + IRQ IEL14_IRQHandler + IRQ IEL15_IRQHandler + IRQ IEL16_IRQHandler + IRQ IEL17_IRQHandler + IRQ IEL18_IRQHandler + IRQ IEL19_IRQHandler + IRQ IEL20_IRQHandler + IRQ IEL21_IRQHandler + IRQ IEL22_IRQHandler + IRQ IEL23_IRQHandler + IRQ IEL24_IRQHandler + IRQ IEL25_IRQHandler + IRQ IEL26_IRQHandler + IRQ IEL27_IRQHandler + IRQ IEL28_IRQHandler + IRQ IEL29_IRQHandler + IRQ IEL30_IRQHandler + IRQ IEL31_IRQHandler + IRQ IEL32_IRQHandler + IRQ IEL33_IRQHandler + IRQ IEL34_IRQHandler + IRQ IEL35_IRQHandler + IRQ IEL36_IRQHandler + IRQ IEL37_IRQHandler + IRQ IEL38_IRQHandler + IRQ IEL39_IRQHandler + IRQ IEL40_IRQHandler + IRQ IEL41_IRQHandler + IRQ IEL42_IRQHandler + IRQ IEL43_IRQHandler + IRQ IEL44_IRQHandler + IRQ IEL45_IRQHandler + IRQ IEL46_IRQHandler + IRQ IEL47_IRQHandler + IRQ IEL48_IRQHandler + IRQ IEL49_IRQHandler + IRQ IEL50_IRQHandler + IRQ IEL51_IRQHandler + IRQ IEL52_IRQHandler + IRQ IEL53_IRQHandler + IRQ IEL54_IRQHandler + IRQ IEL55_IRQHandler + IRQ IEL56_IRQHandler + IRQ IEL57_IRQHandler + IRQ IEL58_IRQHandler + IRQ IEL59_IRQHandler + IRQ IEL60_IRQHandler + IRQ IEL61_IRQHandler + IRQ IEL62_IRQHandler + IRQ IEL63_IRQHandler + IRQ IEL64_IRQHandler + IRQ IEL65_IRQHandler + IRQ IEL66_IRQHandler + IRQ IEL67_IRQHandler + IRQ IEL68_IRQHandler + IRQ IEL69_IRQHandler + IRQ IEL70_IRQHandler + IRQ IEL71_IRQHandler + IRQ IEL72_IRQHandler + IRQ IEL73_IRQHandler + IRQ IEL74_IRQHandler + IRQ IEL75_IRQHandler + IRQ IEL76_IRQHandler + IRQ IEL77_IRQHandler + IRQ IEL78_IRQHandler + IRQ IEL79_IRQHandler + IRQ IEL80_IRQHandler + IRQ IEL81_IRQHandler + IRQ IEL82_IRQHandler + IRQ IEL83_IRQHandler + IRQ IEL84_IRQHandler + IRQ IEL85_IRQHandler + IRQ IEL86_IRQHandler + IRQ IEL87_IRQHandler + IRQ IEL88_IRQHandler + IRQ IEL89_IRQHandler + IRQ IEL90_IRQHandler + IRQ IEL91_IRQHandler + IRQ IEL92_IRQHandler + IRQ IEL93_IRQHandler + IRQ IEL94_IRQHandler + IRQ IEL95_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/riscv/handleinterrupt.S b/targets/device/riscv/handleinterrupt.S new file mode 100644 index 00000000..c206c015 --- /dev/null +++ b/targets/device/riscv/handleinterrupt.S @@ -0,0 +1,130 @@ +#ifdef __riscv_flen +#define NREG 48 +#define LFREG flw +#define SFREG fsw +#else +#define NREG 16 +#endif + +#if __riscv_xlen==64 +#define REGSIZE 8 +#define SREG sd +#define LREG ld +#else +#define REGSIZE 4 +#define SREG sw +#define LREG lw +#endif + +.section .text.handleInterruptASM +.global handleInterruptASM +.type handleInterruptASM,@function +handleInterruptASM: + // Save and restore all registers, because the hardware only saves/restores + // the pc. + // Note: we have to do this in assembly because the "interrupt"="machine" + // attribute is broken in LLVM: https://bugs.llvm.org/show_bug.cgi?id=42984 + addi sp, sp, -NREG*REGSIZE + SREG ra, 0*REGSIZE(sp) + SREG t0, 1*REGSIZE(sp) + SREG t1, 2*REGSIZE(sp) + SREG t2, 3*REGSIZE(sp) + SREG a0, 4*REGSIZE(sp) + SREG a1, 5*REGSIZE(sp) + SREG a2, 6*REGSIZE(sp) + SREG a3, 7*REGSIZE(sp) + SREG a4, 8*REGSIZE(sp) + SREG a5, 9*REGSIZE(sp) + SREG a6, 10*REGSIZE(sp) + SREG a7, 11*REGSIZE(sp) + SREG t3, 12*REGSIZE(sp) + SREG t4, 13*REGSIZE(sp) + SREG t5, 14*REGSIZE(sp) + SREG t6, 15*REGSIZE(sp) +#ifdef __riscv_flen + SFREG f0, (0 + 16)*REGSIZE(sp) + SFREG f1, (1 + 16)*REGSIZE(sp) + SFREG f2, (2 + 16)*REGSIZE(sp) + SFREG f3, (3 + 16)*REGSIZE(sp) + SFREG f4, (4 + 16)*REGSIZE(sp) + SFREG f5, (5 + 16)*REGSIZE(sp) + SFREG f6, (6 + 16)*REGSIZE(sp) + SFREG f7, (7 + 16)*REGSIZE(sp) + SFREG f8, (8 + 16)*REGSIZE(sp) + SFREG f9, (9 + 16)*REGSIZE(sp) + SFREG f10,(10 + 16)*REGSIZE(sp) + SFREG f11,(11 + 16)*REGSIZE(sp) + SFREG f12,(12 + 16)*REGSIZE(sp) + SFREG f13,(13 + 16)*REGSIZE(sp) + SFREG f14,(14 + 16)*REGSIZE(sp) + SFREG f15,(15 + 16)*REGSIZE(sp) + SFREG f16,(16 + 16)*REGSIZE(sp) + SFREG f17,(17 + 16)*REGSIZE(sp) + SFREG f18,(18 + 16)*REGSIZE(sp) + SFREG f19,(19 + 16)*REGSIZE(sp) + SFREG f20,(20 + 16)*REGSIZE(sp) + SFREG f21,(21 + 16)*REGSIZE(sp) + SFREG f22,(22 + 16)*REGSIZE(sp) + SFREG f23,(23 + 16)*REGSIZE(sp) + SFREG f24,(24 + 16)*REGSIZE(sp) + SFREG f25,(25 + 16)*REGSIZE(sp) + SFREG f26,(26 + 16)*REGSIZE(sp) + SFREG f27,(27 + 16)*REGSIZE(sp) + SFREG f28,(28 + 16)*REGSIZE(sp) + SFREG f29,(29 + 16)*REGSIZE(sp) + SFREG f30,(30 + 16)*REGSIZE(sp) + SFREG f31,(31 + 16)*REGSIZE(sp) +#endif + call handleInterrupt +#ifdef __riscv_flen + LFREG f0, (31 + 16)*REGSIZE(sp) + LFREG f1, (30 + 16)*REGSIZE(sp) + LFREG f2, (29 + 16)*REGSIZE(sp) + LFREG f3, (28 + 16)*REGSIZE(sp) + LFREG f4, (27 + 16)*REGSIZE(sp) + LFREG f5, (26 + 16)*REGSIZE(sp) + LFREG f6, (25 + 16)*REGSIZE(sp) + LFREG f7, (24 + 16)*REGSIZE(sp) + LFREG f8, (23 + 16)*REGSIZE(sp) + LFREG f9, (22 + 16)*REGSIZE(sp) + LFREG f10,(21 + 16)*REGSIZE(sp) + LFREG f11,(20 + 16)*REGSIZE(sp) + LFREG f12,(19 + 16)*REGSIZE(sp) + LFREG f13,(18 + 16)*REGSIZE(sp) + LFREG f14,(17 + 16)*REGSIZE(sp) + LFREG f15,(16 + 16)*REGSIZE(sp) + LFREG f16,(15 + 16)*REGSIZE(sp) + LFREG f17,(14 + 16)*REGSIZE(sp) + LFREG f18,(13 + 16)*REGSIZE(sp) + LFREG f19,(12 + 16)*REGSIZE(sp) + LFREG f20,(11 + 16)*REGSIZE(sp) + LFREG f21,(10 + 16)*REGSIZE(sp) + LFREG f22,(9 + 16)*REGSIZE(sp) + LFREG f23,(8 + 16)*REGSIZE(sp) + LFREG f24,(7 + 16)*REGSIZE(sp) + LFREG f25,(6 + 16)*REGSIZE(sp) + LFREG f26,(5 + 16)*REGSIZE(sp) + LFREG f27,(4 + 16)*REGSIZE(sp) + LFREG f28,(3 + 16)*REGSIZE(sp) + LFREG f29,(2 + 16)*REGSIZE(sp) + LFREG f30,(1 + 16)*REGSIZE(sp) + LFREG f31,(0 + 16)*REGSIZE(sp) +#endif + LREG t6, 15*REGSIZE(sp) + LREG t5, 14*REGSIZE(sp) + LREG t4, 13*REGSIZE(sp) + LREG t3, 12*REGSIZE(sp) + LREG a7, 11*REGSIZE(sp) + LREG a6, 10*REGSIZE(sp) + LREG a5, 9*REGSIZE(sp) + LREG a4, 8*REGSIZE(sp) + LREG a3, 7*REGSIZE(sp) + LREG a2, 6*REGSIZE(sp) + LREG a1, 5*REGSIZE(sp) + LREG a0, 4*REGSIZE(sp) + LREG t2, 3*REGSIZE(sp) + LREG t1, 2*REGSIZE(sp) + LREG t0, 1*REGSIZE(sp) + LREG ra, 0*REGSIZE(sp) + addi sp, sp, NREG*REGSIZE + mret diff --git a/targets/device/riscv/start.S b/targets/device/riscv/start.S new file mode 100644 index 00000000..d67d82dc --- /dev/null +++ b/targets/device/riscv/start.S @@ -0,0 +1,59 @@ +.section .init +.global _start +.type _start,@function + +_start: + // If we're on a multicore system, we need to wait for hart 0 to wake us up. +#if TINYGO_CORES > 1 + csrr a0, mhartid + + // Hart 0 stack + bnez a0, 1f + la sp, _stack_top + +1: + // Hart 1 stack + li a1, 1 + bne a0, a1, 2f + la sp, _stack1_top + +2: + // Hart 2 stack + #if TINYGO_CORES >= 3 + li a1, 2 + bne a0, a1, 3f + la sp, _stack2_top + #endif + +3: + // Hart 3 stack + #if TINYGO_CORES >= 4 + li a1, 3 + bne a0, a1, 4f + la sp, _stack3_top + #endif + +4: + // done + +#if TINYGO_CORES > 4 +#error only up to 4 cores are supported at the moment! +#endif + +#else + // Load the stack pointer. + la sp, _stack_top +#endif + + // Load the globals pointer. The program will load pointers relative to this + // register, so it must be set to the right value on startup. + // See: https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register + // Linker relaxations must be disabled to avoid the initialization beign + // relaxed with an uninitialized global pointer: mv gp, gp + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + // Jump to runtime.main + call main diff --git a/targets/device/rp/rp2040.s b/targets/device/rp/rp2040.s new file mode 100644 index 00000000..2063d7d1 --- /dev/null +++ b/targets/device/rp/rp2040.s @@ -0,0 +1,121 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from rp2040.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/RaspberryPi + +/* + +*/ + +// Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +// +// SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long TIMER_IRQ_0_IRQHandler + .long TIMER_IRQ_1_IRQHandler + .long TIMER_IRQ_2_IRQHandler + .long TIMER_IRQ_3_IRQHandler + .long PWM_IRQ_WRAP_IRQHandler + .long USBCTRL_IRQ_IRQHandler + .long XIP_IRQ_IRQHandler + .long PIO0_IRQ_0_IRQHandler + .long PIO0_IRQ_1_IRQHandler + .long PIO1_IRQ_0_IRQHandler + .long PIO1_IRQ_1_IRQHandler + .long DMA_IRQ_0_IRQHandler + .long DMA_IRQ_1_IRQHandler + .long IO_IRQ_BANK0_IRQHandler + .long IO_IRQ_QSPI_IRQHandler + .long SIO_IRQ_PROC0_IRQHandler + .long SIO_IRQ_PROC1_IRQHandler + .long CLOCKS_IRQ_IRQHandler + .long SPI0_IRQ_IRQHandler + .long SPI1_IRQ_IRQHandler + .long UART0_IRQ_IRQHandler + .long UART1_IRQ_IRQHandler + .long ADC_IRQ_FIFO_IRQHandler + .long I2C0_IRQ_IRQHandler + .long I2C1_IRQ_IRQHandler + .long RTC_IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ TIMER_IRQ_0_IRQHandler + IRQ TIMER_IRQ_1_IRQHandler + IRQ TIMER_IRQ_2_IRQHandler + IRQ TIMER_IRQ_3_IRQHandler + IRQ PWM_IRQ_WRAP_IRQHandler + IRQ USBCTRL_IRQ_IRQHandler + IRQ XIP_IRQ_IRQHandler + IRQ PIO0_IRQ_0_IRQHandler + IRQ PIO0_IRQ_1_IRQHandler + IRQ PIO1_IRQ_0_IRQHandler + IRQ PIO1_IRQ_1_IRQHandler + IRQ DMA_IRQ_0_IRQHandler + IRQ DMA_IRQ_1_IRQHandler + IRQ IO_IRQ_BANK0_IRQHandler + IRQ IO_IRQ_QSPI_IRQHandler + IRQ SIO_IRQ_PROC0_IRQHandler + IRQ SIO_IRQ_PROC1_IRQHandler + IRQ CLOCKS_IRQ_IRQHandler + IRQ SPI0_IRQ_IRQHandler + IRQ SPI1_IRQ_IRQHandler + IRQ UART0_IRQ_IRQHandler + IRQ UART1_IRQ_IRQHandler + IRQ ADC_IRQ_FIFO_IRQHandler + IRQ I2C0_IRQ_IRQHandler + IRQ I2C1_IRQ_IRQHandler + IRQ RTC_IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/rp/rp2350.s b/targets/device/rp/rp2350.s new file mode 100644 index 00000000..10279f24 --- /dev/null +++ b/targets/device/rp/rp2350.s @@ -0,0 +1,183 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from rp2350.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/RaspberryPi + +/* +// +// Dual Cortex-M33 or Hazard3 processors at 150MHz +// 520kB on-chip SRAM, in 10 independent banks +// Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD +// 8kB of one-time-programmable storage (OTP) +// Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus +// Additional 16MB flash/PSRAM accessible via optional second chip-select +// On-chip switched-mode power supply to generate core voltage +// Low-quiescent-current LDO mode can be enabled for sleep states +// 2x on-chip PLLs for internal or external clock generation +// GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) +// Security features: +// Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP +// Protected OTP storage for optional boot decryption key +// Global bus filtering based on Arm or RISC-V security/privilege levels +// Peripherals, GPIOs and DMA channels individually assignable to security domains +// Hardware mitigations for fault injection attacks +// Hardware SHA-256 accelerator +// Peripherals: +// 2x UARTs +// 2x SPI controllers +// 2x I2C controllers +// 24x PWM channels +// USB 1.1 controller and PHY, with host and device support +// 12x PIO state machines +// 1x HSTX peripheral +// +*/ + +// Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long TIMER0_IRQ_0_IRQHandler + .long TIMER0_IRQ_1_IRQHandler + .long TIMER0_IRQ_2_IRQHandler + .long TIMER0_IRQ_3_IRQHandler + .long TIMER1_IRQ_0_IRQHandler + .long TIMER1_IRQ_1_IRQHandler + .long TIMER1_IRQ_2_IRQHandler + .long TIMER1_IRQ_3_IRQHandler + .long PWM_IRQ_WRAP_0_IRQHandler + .long PWM_IRQ_WRAP_1_IRQHandler + .long DMA_IRQ_0_IRQHandler + .long DMA_IRQ_1_IRQHandler + .long DMA_IRQ_2_IRQHandler + .long DMA_IRQ_3_IRQHandler + .long USBCTRL_IRQ_IRQHandler + .long PIO0_IRQ_0_IRQHandler + .long PIO0_IRQ_1_IRQHandler + .long PIO1_IRQ_0_IRQHandler + .long PIO1_IRQ_1_IRQHandler + .long PIO2_IRQ_0_IRQHandler + .long PIO2_IRQ_1_IRQHandler + .long IO_IRQ_BANK0_IRQHandler + .long IO_IRQ_BANK0_NS_IRQHandler + .long IO_IRQ_QSPI_IRQHandler + .long IO_IRQ_QSPI_NS_IRQHandler + .long SIO_IRQ_FIFO_IRQHandler + .long SIO_IRQ_BELL_IRQHandler + .long SIO_IRQ_FIFO_NS_IRQHandler + .long SIO_IRQ_BELL_NS_IRQHandler + .long SIO_IRQ_MTIMECMP_IRQHandler + .long CLOCKS_IRQ_IRQHandler + .long SPI0_IRQ_IRQHandler + .long SPI1_IRQ_IRQHandler + .long UART0_IRQ_IRQHandler + .long UART1_IRQ_IRQHandler + .long ADC_IRQ_FIFO_IRQHandler + .long I2C0_IRQ_IRQHandler + .long I2C1_IRQ_IRQHandler + .long OTP_IRQ_IRQHandler + .long TRNG_IRQ_IRQHandler + .long 0 + .long 0 + .long PLL_SYS_IRQ_IRQHandler + .long PLL_USB_IRQ_IRQHandler + .long POWMAN_IRQ_POW_IRQHandler + .long POWMAN_IRQ_TIMER_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ TIMER0_IRQ_0_IRQHandler + IRQ TIMER0_IRQ_1_IRQHandler + IRQ TIMER0_IRQ_2_IRQHandler + IRQ TIMER0_IRQ_3_IRQHandler + IRQ TIMER1_IRQ_0_IRQHandler + IRQ TIMER1_IRQ_1_IRQHandler + IRQ TIMER1_IRQ_2_IRQHandler + IRQ TIMER1_IRQ_3_IRQHandler + IRQ PWM_IRQ_WRAP_0_IRQHandler + IRQ PWM_IRQ_WRAP_1_IRQHandler + IRQ DMA_IRQ_0_IRQHandler + IRQ DMA_IRQ_1_IRQHandler + IRQ DMA_IRQ_2_IRQHandler + IRQ DMA_IRQ_3_IRQHandler + IRQ USBCTRL_IRQ_IRQHandler + IRQ PIO0_IRQ_0_IRQHandler + IRQ PIO0_IRQ_1_IRQHandler + IRQ PIO1_IRQ_0_IRQHandler + IRQ PIO1_IRQ_1_IRQHandler + IRQ PIO2_IRQ_0_IRQHandler + IRQ PIO2_IRQ_1_IRQHandler + IRQ IO_IRQ_BANK0_IRQHandler + IRQ IO_IRQ_BANK0_NS_IRQHandler + IRQ IO_IRQ_QSPI_IRQHandler + IRQ IO_IRQ_QSPI_NS_IRQHandler + IRQ SIO_IRQ_FIFO_IRQHandler + IRQ SIO_IRQ_BELL_IRQHandler + IRQ SIO_IRQ_FIFO_NS_IRQHandler + IRQ SIO_IRQ_BELL_NS_IRQHandler + IRQ SIO_IRQ_MTIMECMP_IRQHandler + IRQ CLOCKS_IRQ_IRQHandler + IRQ SPI0_IRQ_IRQHandler + IRQ SPI1_IRQ_IRQHandler + IRQ UART0_IRQ_IRQHandler + IRQ UART1_IRQ_IRQHandler + IRQ ADC_IRQ_FIFO_IRQHandler + IRQ I2C0_IRQ_IRQHandler + IRQ I2C1_IRQ_IRQHandler + IRQ OTP_IRQ_IRQHandler + IRQ TRNG_IRQ_IRQHandler + IRQ PLL_SYS_IRQ_IRQHandler + IRQ PLL_USB_IRQ_IRQHandler + IRQ POWMAN_IRQ_POW_IRQHandler + IRQ POWMAN_IRQ_TIMER_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9cn11.s b/targets/device/sam/at91sam9cn11.s new file mode 100644 index 00000000..b87eb9f8 --- /dev/null +++ b/targets/device/sam/at91sam9cn11.s @@ -0,0 +1,126 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9CN11.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9CN11 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, Crypto engine, LCD, USB, LPDDR/DDR2/MLC NAND support, 217 Pins (refer to http://www.atmel.com/devices/SAM9CN11.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOC_IRQHandler + .long FUSE_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long 0 + .long UDP_IRQHandler + .long 0 + .long LCDC_IRQHandler + .long 0 + .long SHA_IRQHandler + .long SSC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOC_IRQHandler + IRQ FUSE_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDP_IRQHandler + IRQ LCDC_IRQHandler + IRQ SHA_IRQHandler + IRQ SSC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9cn12.s b/targets/device/sam/at91sam9cn12.s new file mode 100644 index 00000000..212c0f6b --- /dev/null +++ b/targets/device/sam/at91sam9cn12.s @@ -0,0 +1,126 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9CN12.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9CN12 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, Secure BootROM, Crypto engine, LCD, USB, LPDDR/DDR2/MLC NAND support, 217 Pins (refer to http://www.atmel.com/devices/SAM9CN12.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOC_IRQHandler + .long FUSE_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long 0 + .long UDP_IRQHandler + .long 0 + .long LCDC_IRQHandler + .long 0 + .long SHA_IRQHandler + .long SSC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOC_IRQHandler + IRQ FUSE_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDP_IRQHandler + IRQ LCDC_IRQHandler + IRQ SHA_IRQHandler + IRQ SSC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9g10.s b/targets/device/sam/at91sam9g10.s new file mode 100644 index 00000000..fcea0186 --- /dev/null +++ b/targets/device/sam/at91sam9g10.s @@ -0,0 +1,123 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9G10.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9G10 device: ARM926EJ Embedded Microprocessor Unit, 266MHz, LCD, USB, 217 Pins (refer to http://www.atmel.com/devices/SAM9G10.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long MCI_IRQHandler + .long UDP_IRQHandler + .long TWI_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long SSC0_IRQHandler + .long SSC1_IRQHandler + .long SSC2_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long UHP_IRQHandler + .long LCDC_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long IRQ0_IRQHandler + .long IRQ1_IRQHandler + .long IRQ2_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ MCI_IRQHandler + IRQ UDP_IRQHandler + IRQ TWI_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ SSC0_IRQHandler + IRQ SSC1_IRQHandler + IRQ SSC2_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ UHP_IRQHandler + IRQ LCDC_IRQHandler + IRQ IRQ0_IRQHandler + IRQ IRQ1_IRQHandler + IRQ IRQ2_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9g15.s b/targets/device/sam/at91sam9g15.s new file mode 100644 index 00000000..301a5312 --- /dev/null +++ b/targets/device/sam/at91sam9g15.s @@ -0,0 +1,125 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9G15.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9G15 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, LCD, Touchscreen, HS USB, LPDDR/DDR2/MLC NAND support, 217 Pins (refer to http://www.atmel.com/devices/SAM9G15.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOC_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long 0 + .long LCDC_IRQHandler + .long HSMCI1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long 0 + .long 0 + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOC_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ LCDC_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ SSC_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9g20.s b/targets/device/sam/at91sam9g20.s new file mode 100644 index 00000000..bfd6fb7f --- /dev/null +++ b/targets/device/sam/at91sam9g20.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9G20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9G20 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, USB, Ethernet, 217 and 247 Pins (refer to http://www.atmel.com/devices/SAM9G20.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long ADC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long MCI_IRQHandler + .long UDP_IRQHandler + .long TWI_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long SSC0_IRQHandler + .long 0 + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long UHP_IRQHandler + .long EMAC_IRQHandler + .long ISI_IRQHandler + .long USART3_IRQHandler + .long USART4_IRQHandler + .long USART5_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long IRQ0_IRQHandler + .long IRQ1_IRQHandler + .long IRQ2_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ ADC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ MCI_IRQHandler + IRQ UDP_IRQHandler + IRQ TWI_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ SSC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ UHP_IRQHandler + IRQ EMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ USART3_IRQHandler + IRQ USART4_IRQHandler + IRQ USART5_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ IRQ0_IRQHandler + IRQ IRQ1_IRQHandler + IRQ IRQ2_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9g25.s b/targets/device/sam/at91sam9g25.s new file mode 100644 index 00000000..41f0f77e --- /dev/null +++ b/targets/device/sam/at91sam9g25.s @@ -0,0 +1,127 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9G25.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9G25 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, Ethernet, HS USB, LPDDR/DDR2/MLC NAND support, 217 and 247 Pins (refer to http://www.atmel.com/devices/SAM9G25.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOC_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long EMAC_IRQHandler + .long ISI_IRQHandler + .long HSMCI1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long 0 + .long 0 + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOC_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ EMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ SSC_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9g35.s b/targets/device/sam/at91sam9g35.s new file mode 100644 index 00000000..0532fac5 --- /dev/null +++ b/targets/device/sam/at91sam9g35.s @@ -0,0 +1,126 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9G35.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9G35 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, LCD, Touchscreen, Ethernet, HS USB, LPDDR/DDR2/MLC NAND support, 217 Pins (refer to http://www.atmel.com/devices/SAM9G35.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOC_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long EMAC_IRQHandler + .long LCDC_IRQHandler + .long HSMCI1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long 0 + .long 0 + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOC_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ EMAC_IRQHandler + IRQ LCDC_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ SSC_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9m10.s b/targets/device/sam/at91sam9m10.s new file mode 100644 index 00000000..aa56484b --- /dev/null +++ b/targets/device/sam/at91sam9m10.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9M10.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9M10 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, DDR2/LPDDR, Video Decoder, LCD, HS USB, 10/100 Ethernet, Dual EBI, 324 Pins (refer to http://www.atmel.com/devices/SAM9M10.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long TRNG_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long HSMCI0_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long SSC0_IRQHandler + .long SSC1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long TSADCC_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long LCDC_IRQHandler + .long AC97C_IRQHandler + .long EMAC_IRQHandler + .long ISI_IRQHandler + .long UDPHS_IRQHandler + .long 0 + .long HSMCI1_IRQHandler + .long VDEC_IRQHandler + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ TRNG_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ SSC0_IRQHandler + IRQ SSC1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ TSADCC_IRQHandler + IRQ DMAC_IRQHandler + IRQ LCDC_IRQHandler + IRQ AC97C_IRQHandler + IRQ EMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ UDPHS_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ VDEC_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9m11.s b/targets/device/sam/at91sam9m11.s new file mode 100644 index 00000000..4df528e8 --- /dev/null +++ b/targets/device/sam/at91sam9m11.s @@ -0,0 +1,130 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9M11.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9M11 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, Hardware Encryption, Video Decoder, DDR2/LPDDR, Dual EBI, 324 Pins (refer to http://www.atmel.com/devices/SAM9M11.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DDRSDRC0_IRQHandler + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long TRNG_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long HSMCI0_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long SSC0_IRQHandler + .long SSC1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long TSADCC_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long LCDC_IRQHandler + .long AC97C_IRQHandler + .long EMAC_IRQHandler + .long ISI_IRQHandler + .long UDPHS_IRQHandler + .long AES_IRQHandler + .long HSMCI1_IRQHandler + .long VDEC_IRQHandler + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DDRSDRC0_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ TRNG_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ SSC0_IRQHandler + IRQ SSC1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ TSADCC_IRQHandler + IRQ DMAC_IRQHandler + IRQ LCDC_IRQHandler + IRQ AC97C_IRQHandler + IRQ EMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ UDPHS_IRQHandler + IRQ AES_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ VDEC_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9n12.s b/targets/device/sam/at91sam9n12.s new file mode 100644 index 00000000..fff7ab85 --- /dev/null +++ b/targets/device/sam/at91sam9n12.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9N12.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9N12 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, LCD, USB, LPDDR/DDR2/MLC NAND support, 217 Pins (refer to http://www.atmel.com/devices/SAM9N12.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOC_IRQHandler + .long FUSE_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long 0 + .long UDP_IRQHandler + .long 0 + .long LCDC_IRQHandler + .long 0 + .long 0 + .long SSC_IRQHandler + .long 0 + .long TRNG_IRQHandler + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOC_IRQHandler + IRQ FUSE_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDP_IRQHandler + IRQ LCDC_IRQHandler + IRQ SSC_IRQHandler + IRQ TRNG_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9x25.s b/targets/device/sam/at91sam9x25.s new file mode 100644 index 00000000..bc2a5194 --- /dev/null +++ b/targets/device/sam/at91sam9x25.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9X25.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9X25 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, Dual Ethernet and CAN, HS USB, LPDDR/DDR2/MLC NAND support, 217 Pins (refer to http://www.atmel.com/devices/SAM9X25.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOC_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long EMAC0_IRQHandler + .long 0 + .long HSMCI1_IRQHandler + .long EMAC1_IRQHandler + .long SSC_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOC_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ EMAC0_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ EMAC1_IRQHandler + IRQ SSC_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/at91sam9x35.s b/targets/device/sam/at91sam9x35.s new file mode 100644 index 00000000..0a812335 --- /dev/null +++ b/targets/device/sam/at91sam9x35.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from AT91SAM9X35.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel AT91SAM9X35 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, LCD, Touchscreen, Ethernet, Dual CAN, HS USB, LPDDR/DDR2/MLC NAND support, 217 Pins (refer to http://www.atmel.com/devices/SAM9X35.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long DBGU_IRQHandler + .long PIOA_IRQHandler + .long PIOC_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TC0_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long EMAC_IRQHandler + .long LCDC_IRQHandler + .long HSMCI1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long IRQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOC_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TC0_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ EMAC_IRQHandler + IRQ LCDC_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ SSC_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ IRQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3a4c.s b/targets/device/sam/atsam3a4c.s new file mode 100644 index 00000000..43352f69 --- /dev/null +++ b/targets/device/sam/atsam3a4c.s @@ -0,0 +1,140 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3A4C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3A4C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long 0 + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long DMAC_IRQHandler + .long UOTGHS_IRQHandler + .long TRNG_IRQHandler + .long 0 + .long CAN0_IRQHandler + .long CAN1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UOTGHS_IRQHandler + IRQ TRNG_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3a8c.s b/targets/device/sam/atsam3a8c.s new file mode 100644 index 00000000..f1f8f1e3 --- /dev/null +++ b/targets/device/sam/atsam3a8c.s @@ -0,0 +1,140 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3A8C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3A8C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long 0 + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long DMAC_IRQHandler + .long UOTGHS_IRQHandler + .long TRNG_IRQHandler + .long 0 + .long CAN0_IRQHandler + .long CAN1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UOTGHS_IRQHandler + IRQ TRNG_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n00a.s b/targets/device/sam/atsam3n00a.s new file mode 100644 index 00000000..57a3aded --- /dev/null +++ b/targets/device/sam/atsam3n00a.s @@ -0,0 +1,115 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N00A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N00A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n00b.s b/targets/device/sam/atsam3n00b.s new file mode 100644 index 00000000..9fd37144 --- /dev/null +++ b/targets/device/sam/atsam3n00b.s @@ -0,0 +1,116 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N00B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N00B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n0a.s b/targets/device/sam/atsam3n0a.s new file mode 100644 index 00000000..bde27144 --- /dev/null +++ b/targets/device/sam/atsam3n0a.s @@ -0,0 +1,115 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N0A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N0A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n0b.s b/targets/device/sam/atsam3n0b.s new file mode 100644 index 00000000..fe3fb2b2 --- /dev/null +++ b/targets/device/sam/atsam3n0b.s @@ -0,0 +1,116 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N0B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N0B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n0c.s b/targets/device/sam/atsam3n0c.s new file mode 100644 index 00000000..aea099a8 --- /dev/null +++ b/targets/device/sam/atsam3n0c.s @@ -0,0 +1,120 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N0C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N0C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n1a.s b/targets/device/sam/atsam3n1a.s new file mode 100644 index 00000000..2f75edcd --- /dev/null +++ b/targets/device/sam/atsam3n1a.s @@ -0,0 +1,115 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N1A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N1A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n1b.s b/targets/device/sam/atsam3n1b.s new file mode 100644 index 00000000..5f4806ba --- /dev/null +++ b/targets/device/sam/atsam3n1b.s @@ -0,0 +1,116 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N1B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N1B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n1c.s b/targets/device/sam/atsam3n1c.s new file mode 100644 index 00000000..7af68d17 --- /dev/null +++ b/targets/device/sam/atsam3n1c.s @@ -0,0 +1,120 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N1C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N1C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n2a.s b/targets/device/sam/atsam3n2a.s new file mode 100644 index 00000000..0c4c9507 --- /dev/null +++ b/targets/device/sam/atsam3n2a.s @@ -0,0 +1,115 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N2A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N2A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n2b.s b/targets/device/sam/atsam3n2b.s new file mode 100644 index 00000000..b02fdacf --- /dev/null +++ b/targets/device/sam/atsam3n2b.s @@ -0,0 +1,116 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N2B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N2B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n2c.s b/targets/device/sam/atsam3n2c.s new file mode 100644 index 00000000..b0e68ebd --- /dev/null +++ b/targets/device/sam/atsam3n2c.s @@ -0,0 +1,120 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N2C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N2C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n4a.s b/targets/device/sam/atsam3n4a.s new file mode 100644 index 00000000..c315d541 --- /dev/null +++ b/targets/device/sam/atsam3n4a.s @@ -0,0 +1,115 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N4A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N4A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n4b.s b/targets/device/sam/atsam3n4b.s new file mode 100644 index 00000000..ca40010d --- /dev/null +++ b/targets/device/sam/atsam3n4b.s @@ -0,0 +1,116 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N4B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N4B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3n4c.s b/targets/device/sam/atsam3n4c.s new file mode 100644 index 00000000..a98f74c9 --- /dev/null +++ b/targets/device/sam/atsam3n4c.s @@ -0,0 +1,120 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3N4C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3N4C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s1a.s b/targets/device/sam/atsam3s1a.s new file mode 100644 index 00000000..38010b82 --- /dev/null +++ b/targets/device/sam/atsam3s1a.s @@ -0,0 +1,122 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S1A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S1A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s1b.s b/targets/device/sam/atsam3s1b.s new file mode 100644 index 00000000..5ad973b8 --- /dev/null +++ b/targets/device/sam/atsam3s1b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S1B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S1B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s1c.s b/targets/device/sam/atsam3s1c.s new file mode 100644 index 00000000..dae79120 --- /dev/null +++ b/targets/device/sam/atsam3s1c.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S1C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S1C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s2a.s b/targets/device/sam/atsam3s2a.s new file mode 100644 index 00000000..22a3c056 --- /dev/null +++ b/targets/device/sam/atsam3s2a.s @@ -0,0 +1,122 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S2A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S2A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s2b.s b/targets/device/sam/atsam3s2b.s new file mode 100644 index 00000000..9b675877 --- /dev/null +++ b/targets/device/sam/atsam3s2b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S2B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S2B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s2c.s b/targets/device/sam/atsam3s2c.s new file mode 100644 index 00000000..7f93ef1e --- /dev/null +++ b/targets/device/sam/atsam3s2c.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S2C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S2C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s4a.s b/targets/device/sam/atsam3s4a.s new file mode 100644 index 00000000..bea1250d --- /dev/null +++ b/targets/device/sam/atsam3s4a.s @@ -0,0 +1,122 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S4A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S4A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s4b.s b/targets/device/sam/atsam3s4b.s new file mode 100644 index 00000000..7ac53430 --- /dev/null +++ b/targets/device/sam/atsam3s4b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S4B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S4B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s4c.s b/targets/device/sam/atsam3s4c.s new file mode 100644 index 00000000..dbd52179 --- /dev/null +++ b/targets/device/sam/atsam3s4c.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S4C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S4C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s8b.s b/targets/device/sam/atsam3s8b.s new file mode 100644 index 00000000..d3d92d45 --- /dev/null +++ b/targets/device/sam/atsam3s8b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S8B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S8B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3s8c.s b/targets/device/sam/atsam3s8c.s new file mode 100644 index 00000000..87687d17 --- /dev/null +++ b/targets/device/sam/atsam3s8c.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3S8C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3S8C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3sd8b.s b/targets/device/sam/atsam3sd8b.s new file mode 100644 index 00000000..7a3ab8ca --- /dev/null +++ b/targets/device/sam/atsam3sd8b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3SD8B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3SD8B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3sd8c.s b/targets/device/sam/atsam3sd8c.s new file mode 100644 index 00000000..9b8e826c --- /dev/null +++ b/targets/device/sam/atsam3sd8c.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3SD8C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3SD8C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3u1c.s b/targets/device/sam/atsam3u1c.s new file mode 100644 index 00000000..3c45b545 --- /dev/null +++ b/targets/device/sam/atsam3u1c.s @@ -0,0 +1,118 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3U1C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3U1C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long PWM_IRQHandler + .long ADC12B_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long UDPHS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC12B_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDPHS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3u1e.s b/targets/device/sam/atsam3u1e.s new file mode 100644 index 00000000..ece584b3 --- /dev/null +++ b/targets/device/sam/atsam3u1e.s @@ -0,0 +1,120 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3U1E.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3U1E Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long PWM_IRQHandler + .long ADC12B_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long UDPHS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC12B_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDPHS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3u2c.s b/targets/device/sam/atsam3u2c.s new file mode 100644 index 00000000..6dcfdf70 --- /dev/null +++ b/targets/device/sam/atsam3u2c.s @@ -0,0 +1,118 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3U2C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3U2C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long PWM_IRQHandler + .long ADC12B_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long UDPHS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC12B_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDPHS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3u2e.s b/targets/device/sam/atsam3u2e.s new file mode 100644 index 00000000..23f0519c --- /dev/null +++ b/targets/device/sam/atsam3u2e.s @@ -0,0 +1,120 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3U2E.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3U2E Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long PWM_IRQHandler + .long ADC12B_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long UDPHS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC12B_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDPHS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3u4c.s b/targets/device/sam/atsam3u4c.s new file mode 100644 index 00000000..1935c285 --- /dev/null +++ b/targets/device/sam/atsam3u4c.s @@ -0,0 +1,119 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3U4C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3U4C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long PWM_IRQHandler + .long ADC12B_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long UDPHS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC12B_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDPHS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3u4e.s b/targets/device/sam/atsam3u4e.s new file mode 100644 index 00000000..ce486257 --- /dev/null +++ b/targets/device/sam/atsam3u4e.s @@ -0,0 +1,121 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3U4E.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3U4E Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long PWM_IRQHandler + .long ADC12B_IRQHandler + .long ADC_IRQHandler + .long DMAC_IRQHandler + .long UDPHS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC12B_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UDPHS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3x4c.s b/targets/device/sam/atsam3x4c.s new file mode 100644 index 00000000..898cb45d --- /dev/null +++ b/targets/device/sam/atsam3x4c.s @@ -0,0 +1,141 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3X4C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3X4C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long 0 + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long DMAC_IRQHandler + .long UOTGHS_IRQHandler + .long TRNG_IRQHandler + .long EMAC_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UOTGHS_IRQHandler + IRQ TRNG_IRQHandler + IRQ EMAC_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3x4e.s b/targets/device/sam/atsam3x4e.s new file mode 100644 index 00000000..0a9ad298 --- /dev/null +++ b/targets/device/sam/atsam3x4e.s @@ -0,0 +1,147 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3X4E.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3X4E Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long DMAC_IRQHandler + .long UOTGHS_IRQHandler + .long TRNG_IRQHandler + .long EMAC_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UOTGHS_IRQHandler + IRQ TRNG_IRQHandler + IRQ EMAC_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3x8c.s b/targets/device/sam/atsam3x8c.s new file mode 100644 index 00000000..50ef5388 --- /dev/null +++ b/targets/device/sam/atsam3x8c.s @@ -0,0 +1,141 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3X8C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3X8C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long 0 + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long DMAC_IRQHandler + .long UOTGHS_IRQHandler + .long TRNG_IRQHandler + .long EMAC_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UOTGHS_IRQHandler + IRQ TRNG_IRQHandler + IRQ EMAC_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3x8e.s b/targets/device/sam/atsam3x8e.s new file mode 100644 index 00000000..1135079f --- /dev/null +++ b/targets/device/sam/atsam3x8e.s @@ -0,0 +1,147 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3X8E.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3X8E Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long DMAC_IRQHandler + .long UOTGHS_IRQHandler + .long TRNG_IRQHandler + .long EMAC_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UOTGHS_IRQHandler + IRQ TRNG_IRQHandler + IRQ EMAC_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam3x8h.s b/targets/device/sam/atsam3x8h.s new file mode 100644 index 00000000..8f28da63 --- /dev/null +++ b/targets/device/sam/atsam3x8h.s @@ -0,0 +1,151 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM3X8H.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM3X8H Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART_IRQHandler + .long 0 + .long SDRAMC_IRQHandler + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long PIOF_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long DMAC_IRQHandler + .long UOTGHS_IRQHandler + .long TRNG_IRQHandler + .long EMAC_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ PIOF_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ DMAC_IRQHandler + IRQ UOTGHS_IRQHandler + IRQ TRNG_IRQHandler + IRQ EMAC_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s16b.s b/targets/device/sam/atsam4s16b.s new file mode 100644 index 00000000..1190d217 --- /dev/null +++ b/targets/device/sam/atsam4s16b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S16B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S16B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s16c.s b/targets/device/sam/atsam4s16c.s new file mode 100644 index 00000000..c4ef7f8a --- /dev/null +++ b/targets/device/sam/atsam4s16c.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S16C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S16C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s2a.s b/targets/device/sam/atsam4s2a.s new file mode 100644 index 00000000..31172ee7 --- /dev/null +++ b/targets/device/sam/atsam4s2a.s @@ -0,0 +1,121 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S2A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S2A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long 0 + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s2b.s b/targets/device/sam/atsam4s2b.s new file mode 100644 index 00000000..b3e17c24 --- /dev/null +++ b/targets/device/sam/atsam4s2b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S2B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S2B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s2c.s b/targets/device/sam/atsam4s2c.s new file mode 100644 index 00000000..6f66fdc9 --- /dev/null +++ b/targets/device/sam/atsam4s2c.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S2C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S2C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s4a.s b/targets/device/sam/atsam4s4a.s new file mode 100644 index 00000000..a98383b7 --- /dev/null +++ b/targets/device/sam/atsam4s4a.s @@ -0,0 +1,121 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S4A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S4A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long 0 + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s4b.s b/targets/device/sam/atsam4s4b.s new file mode 100644 index 00000000..36a8ce1c --- /dev/null +++ b/targets/device/sam/atsam4s4b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S4B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S4B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s4c.s b/targets/device/sam/atsam4s4c.s new file mode 100644 index 00000000..90cff015 --- /dev/null +++ b/targets/device/sam/atsam4s4c.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S4C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S4C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s8b.s b/targets/device/sam/atsam4s8b.s new file mode 100644 index 00000000..e713b146 --- /dev/null +++ b/targets/device/sam/atsam4s8b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S8B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S8B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4s8c.s b/targets/device/sam/atsam4s8c.s new file mode 100644 index 00000000..170ed178 --- /dev/null +++ b/targets/device/sam/atsam4s8c.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4S8C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4S8C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4sa16b.s b/targets/device/sam/atsam4sa16b.s new file mode 100644 index 00000000..abd71709 --- /dev/null +++ b/targets/device/sam/atsam4sa16b.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4SA16B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4SA16B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4sa16c.s b/targets/device/sam/atsam4sa16c.s new file mode 100644 index 00000000..bf7ddf10 --- /dev/null +++ b/targets/device/sam/atsam4sa16c.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4SA16C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4SA16C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long 0 + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4sd16b.s b/targets/device/sam/atsam4sd16b.s new file mode 100644 index 00000000..f8970e4d --- /dev/null +++ b/targets/device/sam/atsam4sd16b.s @@ -0,0 +1,125 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4SD16B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4SD16B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4sd16c.s b/targets/device/sam/atsam4sd16c.s new file mode 100644 index 00000000..f1b388dd --- /dev/null +++ b/targets/device/sam/atsam4sd16c.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4SD16C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4SD16C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4sd32b.s b/targets/device/sam/atsam4sd32b.s new file mode 100644 index 00000000..6a6c449f --- /dev/null +++ b/targets/device/sam/atsam4sd32b.s @@ -0,0 +1,125 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4SD32B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4SD32B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4sd32c.s b/targets/device/sam/atsam4sd32c.s new file mode 100644 index 00000000..81711aa9 --- /dev/null +++ b/targets/device/sam/atsam4sd32c.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4SD32C.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4SD32C Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long HSMCI_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long SPI_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ SPI_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsam4sp32a.s b/targets/device/sam/atsam4sp32a.s new file mode 100644 index 00000000..17b81fcc --- /dev/null +++ b/targets/device/sam/atsam4sp32a.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAM4SP32A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAM4SP32A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long PMC_IRQHandler + .long EFC0_IRQHandler + .long EFC1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long PPLC_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long ADC_IRQHandler + .long DACC_IRQHandler + .long PWM_IRQHandler + .long CRCCU_IRQHandler + .long ACC_IRQHandler + .long UDP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PMC_IRQHandler + IRQ EFC0_IRQHandler + IRQ EFC1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ PPLC_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM_IRQHandler + IRQ CRCCU_IRQHandler + IRQ ACC_IRQHandler + IRQ UDP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsama5d31.s b/targets/device/sam/atsama5d31.s new file mode 100644 index 00000000..cc1bbcbf --- /dev/null +++ b/targets/device/sam/atsama5d31.s @@ -0,0 +1,154 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMA5D31.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMA5D31 device: ARM Cortex-A5 processor-based embedded MPU, 536MHz, Linux support, FPU, LCD controller, 10/100 Ethernet, security (refer to http://www.atmel.com/devices/SAMA5D31.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long PMC_IRQHandler + .long DBGU_IRQHandler + .long 0 + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long HSMCI1_IRQHandler + .long HSMCI2_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long 0 + .long EMAC_IRQHandler + .long LCDC_IRQHandler + .long ISI_IRQHandler + .long SSC0_IRQHandler + .long SSC1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TRNG_IRQHandler + .long 0 + .long IRQ_IRQHandler + .long FUSE_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ PMC_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ HSMCI2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ EMAC_IRQHandler + IRQ LCDC_IRQHandler + IRQ ISI_IRQHandler + IRQ SSC0_IRQHandler + IRQ SSC1_IRQHandler + IRQ TRNG_IRQHandler + IRQ IRQ_IRQHandler + IRQ FUSE_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsama5d33.s b/targets/device/sam/atsama5d33.s new file mode 100644 index 00000000..efaca5c5 --- /dev/null +++ b/targets/device/sam/atsama5d33.s @@ -0,0 +1,151 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMA5D33.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMA5D33 device: ARM Cortex-A5 processor-based embedded MPU, 536MHz, Linux support, FPU, LCD controller, gigabit Ethernet, security (refer to http://www.atmel.com/devices/SAMA5D33.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long PMC_IRQHandler + .long DBGU_IRQHandler + .long 0 + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long HSMCI1_IRQHandler + .long 0 + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long GMAC_IRQHandler + .long 0 + .long LCDC_IRQHandler + .long ISI_IRQHandler + .long SSC0_IRQHandler + .long SSC1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TRNG_IRQHandler + .long 0 + .long IRQ_IRQHandler + .long FUSE_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ PMC_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ GMAC_IRQHandler + IRQ LCDC_IRQHandler + IRQ ISI_IRQHandler + IRQ SSC0_IRQHandler + IRQ SSC1_IRQHandler + IRQ TRNG_IRQHandler + IRQ IRQ_IRQHandler + IRQ FUSE_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsama5d34.s b/targets/device/sam/atsama5d34.s new file mode 100644 index 00000000..a732e87b --- /dev/null +++ b/targets/device/sam/atsama5d34.s @@ -0,0 +1,154 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMA5D34.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMA5D34 device: ARM Cortex-A5 processor-based embedded MPU, 536MHz, Linux support, FPU, LCD controller, gigabit Ethernet, dual CAN, security (refer to http://www.atmel.com/devices/SAMA5D34.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long PMC_IRQHandler + .long DBGU_IRQHandler + .long 0 + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long 0 + .long 0 + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long HSMCI1_IRQHandler + .long HSMCI2_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long GMAC_IRQHandler + .long 0 + .long LCDC_IRQHandler + .long ISI_IRQHandler + .long SSC0_IRQHandler + .long SSC1_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TRNG_IRQHandler + .long 0 + .long IRQ_IRQHandler + .long FUSE_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ PMC_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ HSMCI2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ GMAC_IRQHandler + IRQ LCDC_IRQHandler + IRQ ISI_IRQHandler + IRQ SSC0_IRQHandler + IRQ SSC1_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ TRNG_IRQHandler + IRQ IRQ_IRQHandler + IRQ FUSE_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsama5d35.s b/targets/device/sam/atsama5d35.s new file mode 100644 index 00000000..71e9246b --- /dev/null +++ b/targets/device/sam/atsama5d35.s @@ -0,0 +1,156 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMA5D35.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMA5D35 device: ARM Cortex-A5 processor-based embedded MPU, 536MHz, Linux support, FPU, dual Ethernet, dual CAN, security (refer to http://www.atmel.com/devices/SAMA5D35.aspx for more) +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long FIQ_IRQHandler + .long PMC_IRQHandler + .long DBGU_IRQHandler + .long 0 + .long 0 + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long SMD_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long TWI0_IRQHandler + .long TWI1_IRQHandler + .long TWI2_IRQHandler + .long HSMCI0_IRQHandler + .long HSMCI1_IRQHandler + .long HSMCI2_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long PWM_IRQHandler + .long ADC_IRQHandler + .long DMAC0_IRQHandler + .long DMAC1_IRQHandler + .long 0 + .long UDPHS_IRQHandler + .long GMAC_IRQHandler + .long EMAC_IRQHandler + .long 0 + .long ISI_IRQHandler + .long SSC0_IRQHandler + .long SSC1_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long 0 + .long 0 + .long 0 + .long TRNG_IRQHandler + .long 0 + .long IRQ_IRQHandler + .long FUSE_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ FIQ_IRQHandler + IRQ PMC_IRQHandler + IRQ DBGU_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ SMD_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ TWI0_IRQHandler + IRQ TWI1_IRQHandler + IRQ TWI2_IRQHandler + IRQ HSMCI0_IRQHandler + IRQ HSMCI1_IRQHandler + IRQ HSMCI2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ PWM_IRQHandler + IRQ ADC_IRQHandler + IRQ DMAC0_IRQHandler + IRQ DMAC1_IRQHandler + IRQ UDPHS_IRQHandler + IRQ GMAC_IRQHandler + IRQ EMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ SSC0_IRQHandler + IRQ SSC1_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ TRNG_IRQHandler + IRQ IRQ_IRQHandler + IRQ FUSE_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e15a.s b/targets/device/sam/atsamd21e15a.s new file mode 100644 index 00000000..bfb436e0 --- /dev/null +++ b/targets/device/sam/atsamd21e15a.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E15A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E15A device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 32-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e15b.s b/targets/device/sam/atsamd21e15b.s new file mode 100644 index 00000000..65b6903c --- /dev/null +++ b/targets/device/sam/atsamd21e15b.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E15B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E15B device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 32-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e15bu.s b/targets/device/sam/atsamd21e15bu.s new file mode 100644 index 00000000..bb4612ec --- /dev/null +++ b/targets/device/sam/atsamd21e15bu.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E15BU.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E15BU device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 35-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e15cu.s b/targets/device/sam/atsamd21e15cu.s new file mode 100644 index 00000000..7be5612c --- /dev/null +++ b/targets/device/sam/atsamd21e15cu.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E15CU.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E15CU device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 35-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e15l.s b/targets/device/sam/atsamd21e15l.s new file mode 100644 index 00000000..ff7b4151 --- /dev/null +++ b/targets/device/sam/atsamd21e15l.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E15L.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E15L device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, QFN32_LIGHTING-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long 0 + .long AC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ AC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e16a.s b/targets/device/sam/atsamd21e16a.s new file mode 100644 index 00000000..4dde3271 --- /dev/null +++ b/targets/device/sam/atsamd21e16a.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 32-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e16b.s b/targets/device/sam/atsamd21e16b.s new file mode 100644 index 00000000..abab0b90 --- /dev/null +++ b/targets/device/sam/atsamd21e16b.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E16B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E16B device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 32-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e16bu.s b/targets/device/sam/atsamd21e16bu.s new file mode 100644 index 00000000..ba98344a --- /dev/null +++ b/targets/device/sam/atsamd21e16bu.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E16BU.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E16BU device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 35-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e16cu.s b/targets/device/sam/atsamd21e16cu.s new file mode 100644 index 00000000..d181fa27 --- /dev/null +++ b/targets/device/sam/atsamd21e16cu.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E16CU.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E16CU device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 35-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e16l.s b/targets/device/sam/atsamd21e16l.s new file mode 100644 index 00000000..f467050f --- /dev/null +++ b/targets/device/sam/atsamd21e16l.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E16L.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E16L device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, QFN32_LIGHTING-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long 0 + .long AC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ AC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e17a.s b/targets/device/sam/atsamd21e17a.s new file mode 100644 index 00000000..a8537528 --- /dev/null +++ b/targets/device/sam/atsamd21e17a.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E17A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 32-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e17d.s b/targets/device/sam/atsamd21e17d.s new file mode 100644 index 00000000..79438ab7 --- /dev/null +++ b/targets/device/sam/atsamd21e17d.s @@ -0,0 +1,135 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E17D.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E17D device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 32-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + .long 0 + .long TCC3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + IRQ TCC3_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e17du.s b/targets/device/sam/atsamd21e17du.s new file mode 100644 index 00000000..b302e82a --- /dev/null +++ b/targets/device/sam/atsamd21e17du.s @@ -0,0 +1,135 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E17DU.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E17DU device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 35-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + .long 0 + .long TCC3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + IRQ TCC3_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e17l.s b/targets/device/sam/atsamd21e17l.s new file mode 100644 index 00000000..c6b806d5 --- /dev/null +++ b/targets/device/sam/atsamd21e17l.s @@ -0,0 +1,134 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E17L.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E17L device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, QFN32_LIGHTING-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long 0 + .long AC1_IRQHandler + .long TCC3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ AC1_IRQHandler + IRQ TCC3_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21e18a.s b/targets/device/sam/atsamd21e18a.s new file mode 100644 index 00000000..866373c3 --- /dev/null +++ b/targets/device/sam/atsamd21e18a.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21E18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21E18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 32-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g15a.s b/targets/device/sam/atsamd21g15a.s new file mode 100644 index 00000000..7d882af3 --- /dev/null +++ b/targets/device/sam/atsamd21g15a.s @@ -0,0 +1,134 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G15A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G15A device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 48-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g15b.s b/targets/device/sam/atsamd21g15b.s new file mode 100644 index 00000000..a4a12178 --- /dev/null +++ b/targets/device/sam/atsamd21g15b.s @@ -0,0 +1,134 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G15B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G15B device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 48-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g15l.s b/targets/device/sam/atsamd21g15l.s new file mode 100644 index 00000000..86123150 --- /dev/null +++ b/targets/device/sam/atsamd21g15l.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G15L.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G15L device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, QFN48_LIGHTING-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long 0 + .long AC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ AC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g16a.s b/targets/device/sam/atsamd21g16a.s new file mode 100644 index 00000000..3d0a4675 --- /dev/null +++ b/targets/device/sam/atsamd21g16a.s @@ -0,0 +1,134 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 48-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g16b.s b/targets/device/sam/atsamd21g16b.s new file mode 100644 index 00000000..1b9067b3 --- /dev/null +++ b/targets/device/sam/atsamd21g16b.s @@ -0,0 +1,134 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G16B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G16B device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 48-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g16l.s b/targets/device/sam/atsamd21g16l.s new file mode 100644 index 00000000..e5b6da0e --- /dev/null +++ b/targets/device/sam/atsamd21g16l.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G16L.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G16L device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, QFN48_LIGHTING-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long 0 + .long AC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ AC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g17a.s b/targets/device/sam/atsamd21g17a.s new file mode 100644 index 00000000..06dab568 --- /dev/null +++ b/targets/device/sam/atsamd21g17a.s @@ -0,0 +1,134 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G17A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 48-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g17au.s b/targets/device/sam/atsamd21g17au.s new file mode 100644 index 00000000..f26c3501 --- /dev/null +++ b/targets/device/sam/atsamd21g17au.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G17AU.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G17AU device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 45-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g17d.s b/targets/device/sam/atsamd21g17d.s new file mode 100644 index 00000000..26540d47 --- /dev/null +++ b/targets/device/sam/atsamd21g17d.s @@ -0,0 +1,137 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G17D.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G17D device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 48-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + .long 0 + .long TCC3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + IRQ TCC3_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g17l.s b/targets/device/sam/atsamd21g17l.s new file mode 100644 index 00000000..47b8ea5f --- /dev/null +++ b/targets/device/sam/atsamd21g17l.s @@ -0,0 +1,138 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G17L.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G17L device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, QFN48_LIGHTING-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long 0 + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long 0 + .long AC1_IRQHandler + .long TCC3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ AC1_IRQHandler + IRQ TCC3_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g18a.s b/targets/device/sam/atsamd21g18a.s new file mode 100644 index 00000000..15112760 --- /dev/null +++ b/targets/device/sam/atsamd21g18a.s @@ -0,0 +1,134 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 48-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21g18au.s b/targets/device/sam/atsamd21g18au.s new file mode 100644 index 00000000..4a49b64e --- /dev/null +++ b/targets/device/sam/atsamd21g18au.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21G18AU.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21G18AU device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 45-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21j15a.s b/targets/device/sam/atsamd21j15a.s new file mode 100644 index 00000000..8cf77037 --- /dev/null +++ b/targets/device/sam/atsamd21j15a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21J15A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21J15A device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21j15b.s b/targets/device/sam/atsamd21j15b.s new file mode 100644 index 00000000..c71a7ef0 --- /dev/null +++ b/targets/device/sam/atsamd21j15b.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21J15B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21J15B device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21j16a.s b/targets/device/sam/atsamd21j16a.s new file mode 100644 index 00000000..a7ec475a --- /dev/null +++ b/targets/device/sam/atsamd21j16a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21J16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21J16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21j16b.s b/targets/device/sam/atsamd21j16b.s new file mode 100644 index 00000000..786027e5 --- /dev/null +++ b/targets/device/sam/atsamd21j16b.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21J16B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21J16B device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21j17a.s b/targets/device/sam/atsamd21j17a.s new file mode 100644 index 00000000..49fcdb06 --- /dev/null +++ b/targets/device/sam/atsamd21j17a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21J17A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21J17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21j17d.s b/targets/device/sam/atsamd21j17d.s new file mode 100644 index 00000000..ae4a3e75 --- /dev/null +++ b/targets/device/sam/atsamd21j17d.s @@ -0,0 +1,139 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21J17D.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21J17D device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + .long 0 + .long TCC3_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + IRQ TCC3_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd21j18a.s b/targets/device/sam/atsamd21j18a.s new file mode 100644 index 00000000..5b38f7d2 --- /dev/null +++ b/targets/device/sam/atsamd21j18a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD21J18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD21J18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long SYSCTRL_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long USB_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TCC1_IRQHandler + .long TCC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long I2S_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ SYSCTRL_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ USB_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TCC1_IRQHandler + IRQ TCC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_IRQHandler + IRQ I2S_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51g18a.s b/targets/device/sam/atsamd51g18a.s new file mode 100644 index 00000000..78be7e0c --- /dev/null +++ b/targets/device/sam/atsamd51g18a.s @@ -0,0 +1,313 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51G18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51G18A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long 0 + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51g19a.s b/targets/device/sam/atsamd51g19a.s new file mode 100644 index 00000000..7e7cd236 --- /dev/null +++ b/targets/device/sam/atsamd51g19a.s @@ -0,0 +1,313 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51G19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51G19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long 0 + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51j18a.s b/targets/device/sam/atsamd51j18a.s new file mode 100644 index 00000000..19a9c09a --- /dev/null +++ b/targets/device/sam/atsamd51j18a.s @@ -0,0 +1,322 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51J18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51J18A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51j19a.s b/targets/device/sam/atsamd51j19a.s new file mode 100644 index 00000000..89de955d --- /dev/null +++ b/targets/device/sam/atsamd51j19a.s @@ -0,0 +1,322 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51J19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51J19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51j20a.s b/targets/device/sam/atsamd51j20a.s new file mode 100644 index 00000000..9e566b60 --- /dev/null +++ b/targets/device/sam/atsamd51j20a.s @@ -0,0 +1,322 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51J20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51J20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51n19a.s b/targets/device/sam/atsamd51n19a.s new file mode 100644 index 00000000..678955fb --- /dev/null +++ b/targets/device/sam/atsamd51n19a.s @@ -0,0 +1,334 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51N19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51N19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51n20a.s b/targets/device/sam/atsamd51n20a.s new file mode 100644 index 00000000..2d3efaf9 --- /dev/null +++ b/targets/device/sam/atsamd51n20a.s @@ -0,0 +1,334 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51N20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51N20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51p19a.s b/targets/device/sam/atsamd51p19a.s new file mode 100644 index 00000000..70d1eba0 --- /dev/null +++ b/targets/device/sam/atsamd51p19a.s @@ -0,0 +1,334 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51P19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51P19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamd51p20a.s b/targets/device/sam/atsamd51p20a.s new file mode 100644 index 00000000..b3dcaec2 --- /dev/null +++ b/targets/device/sam/atsamd51p20a.s @@ -0,0 +1,334 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMD51P20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMD51P20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame51g18a.s b/targets/device/sam/atsame51g18a.s new file mode 100644 index 00000000..e5e213eb --- /dev/null +++ b/targets/device/sam/atsame51g18a.s @@ -0,0 +1,314 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME51G18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME51G18A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CAN0_IRQHandler + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long 0 + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame51g19a.s b/targets/device/sam/atsame51g19a.s new file mode 100644 index 00000000..3a528c2e --- /dev/null +++ b/targets/device/sam/atsame51g19a.s @@ -0,0 +1,314 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME51G19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME51G19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CAN0_IRQHandler + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long 0 + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame51j18a.s b/targets/device/sam/atsame51j18a.s new file mode 100644 index 00000000..2c6435f0 --- /dev/null +++ b/targets/device/sam/atsame51j18a.s @@ -0,0 +1,324 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME51J18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME51J18A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame51j19a.s b/targets/device/sam/atsame51j19a.s new file mode 100644 index 00000000..13952c3c --- /dev/null +++ b/targets/device/sam/atsame51j19a.s @@ -0,0 +1,324 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME51J19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME51J19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame51j20a.s b/targets/device/sam/atsame51j20a.s new file mode 100644 index 00000000..d1c3bcbe --- /dev/null +++ b/targets/device/sam/atsame51j20a.s @@ -0,0 +1,324 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME51J20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME51J20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame51n19a.s b/targets/device/sam/atsame51n19a.s new file mode 100644 index 00000000..ef23720f --- /dev/null +++ b/targets/device/sam/atsame51n19a.s @@ -0,0 +1,334 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME51N19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME51N19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame51n20a.s b/targets/device/sam/atsame51n20a.s new file mode 100644 index 00000000..221eff9f --- /dev/null +++ b/targets/device/sam/atsame51n20a.s @@ -0,0 +1,334 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME51N20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME51N20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long 0 + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame53j18a.s b/targets/device/sam/atsame53j18a.s new file mode 100644 index 00000000..d18d8014 --- /dev/null +++ b/targets/device/sam/atsame53j18a.s @@ -0,0 +1,323 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME53J18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME53J18A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame53j19a.s b/targets/device/sam/atsame53j19a.s new file mode 100644 index 00000000..5cb76c65 --- /dev/null +++ b/targets/device/sam/atsame53j19a.s @@ -0,0 +1,323 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME53J19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME53J19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame53j20a.s b/targets/device/sam/atsame53j20a.s new file mode 100644 index 00000000..c380d8f9 --- /dev/null +++ b/targets/device/sam/atsame53j20a.s @@ -0,0 +1,323 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME53J20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME53J20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long 0 + .long 0 + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame53n19a.s b/targets/device/sam/atsame53n19a.s new file mode 100644 index 00000000..e9518b4f --- /dev/null +++ b/targets/device/sam/atsame53n19a.s @@ -0,0 +1,335 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME53N19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME53N19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame53n20a.s b/targets/device/sam/atsame53n20a.s new file mode 100644 index 00000000..ee85b1d3 --- /dev/null +++ b/targets/device/sam/atsame53n20a.s @@ -0,0 +1,335 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME53N20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME53N20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long 0 + .long 0 + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame54n19a.s b/targets/device/sam/atsame54n19a.s new file mode 100644 index 00000000..da30a829 --- /dev/null +++ b/targets/device/sam/atsame54n19a.s @@ -0,0 +1,337 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME54N19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME54N19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame54n20a.s b/targets/device/sam/atsame54n20a.s new file mode 100644 index 00000000..f1e2209a --- /dev/null +++ b/targets/device/sam/atsame54n20a.s @@ -0,0 +1,337 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME54N20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME54N20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame54p19a.s b/targets/device/sam/atsame54p19a.s new file mode 100644 index 00000000..26bfe873 --- /dev/null +++ b/targets/device/sam/atsame54p19a.s @@ -0,0 +1,337 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME54P19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME54P19A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame54p20a.s b/targets/device/sam/atsame54p20a.s new file mode 100644 index 00000000..6c91ec1c --- /dev/null +++ b/targets/device/sam/atsame54p20a.s @@ -0,0 +1,337 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME54P20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME54P20A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_IRQHandler + .long MCLK_IRQHandler + .long OSCCTRL_XOSC0_IRQHandler + .long OSCCTRL_XOSC1_IRQHandler + .long OSCCTRL_DFLL_IRQHandler + .long OSCCTRL_DPLL0_IRQHandler + .long OSCCTRL_DPLL1_IRQHandler + .long OSC32KCTRL_IRQHandler + .long SUPC_OTHER_IRQHandler + .long SUPC_BODDET_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_EXTINT_0_IRQHandler + .long EIC_EXTINT_1_IRQHandler + .long EIC_EXTINT_2_IRQHandler + .long EIC_EXTINT_3_IRQHandler + .long EIC_EXTINT_4_IRQHandler + .long EIC_EXTINT_5_IRQHandler + .long EIC_EXTINT_6_IRQHandler + .long EIC_EXTINT_7_IRQHandler + .long EIC_EXTINT_8_IRQHandler + .long EIC_EXTINT_9_IRQHandler + .long EIC_EXTINT_10_IRQHandler + .long EIC_EXTINT_11_IRQHandler + .long EIC_EXTINT_12_IRQHandler + .long EIC_EXTINT_13_IRQHandler + .long EIC_EXTINT_14_IRQHandler + .long EIC_EXTINT_15_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_0_IRQHandler + .long NVMCTRL_1_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_OTHER_IRQHandler + .long PAC_IRQHandler + .long 0 + .long 0 + .long 0 + .long RAMECC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long SERCOM3_0_IRQHandler + .long SERCOM3_1_IRQHandler + .long SERCOM3_2_IRQHandler + .long SERCOM3_OTHER_IRQHandler + .long SERCOM4_0_IRQHandler + .long SERCOM4_1_IRQHandler + .long SERCOM4_2_IRQHandler + .long SERCOM4_OTHER_IRQHandler + .long SERCOM5_0_IRQHandler + .long SERCOM5_1_IRQHandler + .long SERCOM5_2_IRQHandler + .long SERCOM5_OTHER_IRQHandler + .long SERCOM6_0_IRQHandler + .long SERCOM6_1_IRQHandler + .long SERCOM6_2_IRQHandler + .long SERCOM6_OTHER_IRQHandler + .long SERCOM7_0_IRQHandler + .long SERCOM7_1_IRQHandler + .long SERCOM7_2_IRQHandler + .long SERCOM7_OTHER_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long USB_OTHER_IRQHandler + .long USB_SOF_HSOF_IRQHandler + .long USB_TRCPT0_IRQHandler + .long USB_TRCPT1_IRQHandler + .long GMAC_IRQHandler + .long TCC0_OTHER_IRQHandler + .long TCC0_MC0_IRQHandler + .long TCC0_MC1_IRQHandler + .long TCC0_MC2_IRQHandler + .long TCC0_MC3_IRQHandler + .long TCC0_MC4_IRQHandler + .long TCC0_MC5_IRQHandler + .long TCC1_OTHER_IRQHandler + .long TCC1_MC0_IRQHandler + .long TCC1_MC1_IRQHandler + .long TCC1_MC2_IRQHandler + .long TCC1_MC3_IRQHandler + .long TCC2_OTHER_IRQHandler + .long TCC2_MC0_IRQHandler + .long TCC2_MC1_IRQHandler + .long TCC2_MC2_IRQHandler + .long TCC3_OTHER_IRQHandler + .long TCC3_MC0_IRQHandler + .long TCC3_MC1_IRQHandler + .long TCC4_OTHER_IRQHandler + .long TCC4_MC0_IRQHandler + .long TCC4_MC1_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long PDEC_OTHER_IRQHandler + .long PDEC_MC0_IRQHandler + .long PDEC_MC1_IRQHandler + .long ADC0_OTHER_IRQHandler + .long ADC0_RESRDY_IRQHandler + .long ADC1_OTHER_IRQHandler + .long ADC1_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_OTHER_IRQHandler + .long DAC_EMPTY_0_IRQHandler + .long DAC_EMPTY_1_IRQHandler + .long DAC_RESRDY_0_IRQHandler + .long DAC_RESRDY_1_IRQHandler + .long I2S_IRQHandler + .long PCC_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + .long ICM_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long SDHC0_IRQHandler + .long SDHC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_IRQHandler + IRQ MCLK_IRQHandler + IRQ OSCCTRL_XOSC0_IRQHandler + IRQ OSCCTRL_XOSC1_IRQHandler + IRQ OSCCTRL_DFLL_IRQHandler + IRQ OSCCTRL_DPLL0_IRQHandler + IRQ OSCCTRL_DPLL1_IRQHandler + IRQ OSC32KCTRL_IRQHandler + IRQ SUPC_OTHER_IRQHandler + IRQ SUPC_BODDET_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_EXTINT_0_IRQHandler + IRQ EIC_EXTINT_1_IRQHandler + IRQ EIC_EXTINT_2_IRQHandler + IRQ EIC_EXTINT_3_IRQHandler + IRQ EIC_EXTINT_4_IRQHandler + IRQ EIC_EXTINT_5_IRQHandler + IRQ EIC_EXTINT_6_IRQHandler + IRQ EIC_EXTINT_7_IRQHandler + IRQ EIC_EXTINT_8_IRQHandler + IRQ EIC_EXTINT_9_IRQHandler + IRQ EIC_EXTINT_10_IRQHandler + IRQ EIC_EXTINT_11_IRQHandler + IRQ EIC_EXTINT_12_IRQHandler + IRQ EIC_EXTINT_13_IRQHandler + IRQ EIC_EXTINT_14_IRQHandler + IRQ EIC_EXTINT_15_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_0_IRQHandler + IRQ NVMCTRL_1_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_OTHER_IRQHandler + IRQ PAC_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ SERCOM3_0_IRQHandler + IRQ SERCOM3_1_IRQHandler + IRQ SERCOM3_2_IRQHandler + IRQ SERCOM3_OTHER_IRQHandler + IRQ SERCOM4_0_IRQHandler + IRQ SERCOM4_1_IRQHandler + IRQ SERCOM4_2_IRQHandler + IRQ SERCOM4_OTHER_IRQHandler + IRQ SERCOM5_0_IRQHandler + IRQ SERCOM5_1_IRQHandler + IRQ SERCOM5_2_IRQHandler + IRQ SERCOM5_OTHER_IRQHandler + IRQ SERCOM6_0_IRQHandler + IRQ SERCOM6_1_IRQHandler + IRQ SERCOM6_2_IRQHandler + IRQ SERCOM6_OTHER_IRQHandler + IRQ SERCOM7_0_IRQHandler + IRQ SERCOM7_1_IRQHandler + IRQ SERCOM7_2_IRQHandler + IRQ SERCOM7_OTHER_IRQHandler + IRQ CAN0_IRQHandler + IRQ CAN1_IRQHandler + IRQ USB_OTHER_IRQHandler + IRQ USB_SOF_HSOF_IRQHandler + IRQ USB_TRCPT0_IRQHandler + IRQ USB_TRCPT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ TCC0_OTHER_IRQHandler + IRQ TCC0_MC0_IRQHandler + IRQ TCC0_MC1_IRQHandler + IRQ TCC0_MC2_IRQHandler + IRQ TCC0_MC3_IRQHandler + IRQ TCC0_MC4_IRQHandler + IRQ TCC0_MC5_IRQHandler + IRQ TCC1_OTHER_IRQHandler + IRQ TCC1_MC0_IRQHandler + IRQ TCC1_MC1_IRQHandler + IRQ TCC1_MC2_IRQHandler + IRQ TCC1_MC3_IRQHandler + IRQ TCC2_OTHER_IRQHandler + IRQ TCC2_MC0_IRQHandler + IRQ TCC2_MC1_IRQHandler + IRQ TCC2_MC2_IRQHandler + IRQ TCC3_OTHER_IRQHandler + IRQ TCC3_MC0_IRQHandler + IRQ TCC3_MC1_IRQHandler + IRQ TCC4_OTHER_IRQHandler + IRQ TCC4_MC0_IRQHandler + IRQ TCC4_MC1_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ PDEC_OTHER_IRQHandler + IRQ PDEC_MC0_IRQHandler + IRQ PDEC_MC1_IRQHandler + IRQ ADC0_OTHER_IRQHandler + IRQ ADC0_RESRDY_IRQHandler + IRQ ADC1_OTHER_IRQHandler + IRQ ADC1_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_OTHER_IRQHandler + IRQ DAC_EMPTY_0_IRQHandler + IRQ DAC_EMPTY_1_IRQHandler + IRQ DAC_RESRDY_0_IRQHandler + IRQ DAC_RESRDY_1_IRQHandler + IRQ I2S_IRQHandler + IRQ PCC_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ ICM_IRQHandler + IRQ QSPI_IRQHandler + IRQ SDHC0_IRQHandler + IRQ SDHC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70j19.s b/targets/device/sam/atsame70j19.s new file mode 100644 index 00000000..ea7c8b03 --- /dev/null +++ b/targets/device/sam/atsame70j19.s @@ -0,0 +1,187 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70J19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70J19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70j19b.s b/targets/device/sam/atsame70j19b.s new file mode 100644 index 00000000..b2248b42 --- /dev/null +++ b/targets/device/sam/atsame70j19b.s @@ -0,0 +1,197 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70J19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70J19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long 0 + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70j20.s b/targets/device/sam/atsame70j20.s new file mode 100644 index 00000000..e49edf3d --- /dev/null +++ b/targets/device/sam/atsame70j20.s @@ -0,0 +1,187 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70J20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70J20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70j20b.s b/targets/device/sam/atsame70j20b.s new file mode 100644 index 00000000..10c57eef --- /dev/null +++ b/targets/device/sam/atsame70j20b.s @@ -0,0 +1,197 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70J20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70J20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long 0 + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70j21.s b/targets/device/sam/atsame70j21.s new file mode 100644 index 00000000..0b6e4c23 --- /dev/null +++ b/targets/device/sam/atsame70j21.s @@ -0,0 +1,187 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70J21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70J21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70j21b.s b/targets/device/sam/atsame70j21b.s new file mode 100644 index 00000000..a9009436 --- /dev/null +++ b/targets/device/sam/atsame70j21b.s @@ -0,0 +1,197 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70J21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70J21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long 0 + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70n19.s b/targets/device/sam/atsame70n19.s new file mode 100644 index 00000000..6679359d --- /dev/null +++ b/targets/device/sam/atsame70n19.s @@ -0,0 +1,195 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70N19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70N19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70n19b.s b/targets/device/sam/atsame70n19b.s new file mode 100644 index 00000000..8ad8d605 --- /dev/null +++ b/targets/device/sam/atsame70n19b.s @@ -0,0 +1,206 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70N19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70N19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70n20.s b/targets/device/sam/atsame70n20.s new file mode 100644 index 00000000..ae346186 --- /dev/null +++ b/targets/device/sam/atsame70n20.s @@ -0,0 +1,195 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70N20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70N20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70n20b.s b/targets/device/sam/atsame70n20b.s new file mode 100644 index 00000000..04995ea9 --- /dev/null +++ b/targets/device/sam/atsame70n20b.s @@ -0,0 +1,206 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70N20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70N20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70n21.s b/targets/device/sam/atsame70n21.s new file mode 100644 index 00000000..a91e3ce6 --- /dev/null +++ b/targets/device/sam/atsame70n21.s @@ -0,0 +1,195 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70N21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70N21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70n21b.s b/targets/device/sam/atsame70n21b.s new file mode 100644 index 00000000..28044c82 --- /dev/null +++ b/targets/device/sam/atsame70n21b.s @@ -0,0 +1,206 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70N21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70N21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70q19.s b/targets/device/sam/atsame70q19.s new file mode 100644 index 00000000..76c8840b --- /dev/null +++ b/targets/device/sam/atsame70q19.s @@ -0,0 +1,199 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70Q19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70Q19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70q19b.s b/targets/device/sam/atsame70q19b.s new file mode 100644 index 00000000..c542a611 --- /dev/null +++ b/targets/device/sam/atsame70q19b.s @@ -0,0 +1,211 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70Q19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70Q19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70q20.s b/targets/device/sam/atsame70q20.s new file mode 100644 index 00000000..438a0d13 --- /dev/null +++ b/targets/device/sam/atsame70q20.s @@ -0,0 +1,199 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70Q20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70Q20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70q20b.s b/targets/device/sam/atsame70q20b.s new file mode 100644 index 00000000..95675cdc --- /dev/null +++ b/targets/device/sam/atsame70q20b.s @@ -0,0 +1,211 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70Q20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70Q20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70q21.s b/targets/device/sam/atsame70q21.s new file mode 100644 index 00000000..cc5b6748 --- /dev/null +++ b/targets/device/sam/atsame70q21.s @@ -0,0 +1,199 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70Q21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70Q21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsame70q21b.s b/targets/device/sam/atsame70q21b.s new file mode 100644 index 00000000..159f0687 --- /dev/null +++ b/targets/device/sam/atsame70q21b.s @@ -0,0 +1,211 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAME70Q21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAME70Q21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml11d14a.s b/targets/device/sam/atsaml11d14a.s new file mode 100644 index 00000000..0058ab12 --- /dev/null +++ b/targets/device/sam/atsaml11d14a.s @@ -0,0 +1,152 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML11D14A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML11D14A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_0_IRQHandler + .long EIC_1_IRQHandler + .long EIC_2_IRQHandler + .long EIC_3_IRQHandler + .long EIC_OTHER_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_IRQHandler + .long PORT_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_NSCHK_IRQHandler + .long PAC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long ADC_OTHER_IRQHandler + .long ADC_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_UNDERRUN_A_IRQHandler + .long DAC_EMPTY_IRQHandler + .long PTC_IRQHandler + .long TRNG_IRQHandler + .long TRAM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_0_IRQHandler + IRQ EIC_1_IRQHandler + IRQ EIC_2_IRQHandler + IRQ EIC_3_IRQHandler + IRQ EIC_OTHER_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ PORT_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_NSCHK_IRQHandler + IRQ PAC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_OTHER_IRQHandler + IRQ ADC_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_UNDERRUN_A_IRQHandler + IRQ DAC_EMPTY_IRQHandler + IRQ PTC_IRQHandler + IRQ TRNG_IRQHandler + IRQ TRAM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml11d15a.s b/targets/device/sam/atsaml11d15a.s new file mode 100644 index 00000000..a6dfde56 --- /dev/null +++ b/targets/device/sam/atsaml11d15a.s @@ -0,0 +1,152 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML11D15A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML11D15A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_0_IRQHandler + .long EIC_1_IRQHandler + .long EIC_2_IRQHandler + .long EIC_3_IRQHandler + .long EIC_OTHER_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_IRQHandler + .long PORT_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_NSCHK_IRQHandler + .long PAC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long ADC_OTHER_IRQHandler + .long ADC_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_UNDERRUN_A_IRQHandler + .long DAC_EMPTY_IRQHandler + .long PTC_IRQHandler + .long TRNG_IRQHandler + .long TRAM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_0_IRQHandler + IRQ EIC_1_IRQHandler + IRQ EIC_2_IRQHandler + IRQ EIC_3_IRQHandler + IRQ EIC_OTHER_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ PORT_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_NSCHK_IRQHandler + IRQ PAC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_OTHER_IRQHandler + IRQ ADC_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_UNDERRUN_A_IRQHandler + IRQ DAC_EMPTY_IRQHandler + IRQ PTC_IRQHandler + IRQ TRNG_IRQHandler + IRQ TRAM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml11d16a.s b/targets/device/sam/atsaml11d16a.s new file mode 100644 index 00000000..ee71b813 --- /dev/null +++ b/targets/device/sam/atsaml11d16a.s @@ -0,0 +1,152 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML11D16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML11D16A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_0_IRQHandler + .long EIC_1_IRQHandler + .long EIC_2_IRQHandler + .long EIC_3_IRQHandler + .long EIC_OTHER_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_IRQHandler + .long PORT_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_NSCHK_IRQHandler + .long PAC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long ADC_OTHER_IRQHandler + .long ADC_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_UNDERRUN_A_IRQHandler + .long DAC_EMPTY_IRQHandler + .long PTC_IRQHandler + .long TRNG_IRQHandler + .long TRAM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_0_IRQHandler + IRQ EIC_1_IRQHandler + IRQ EIC_2_IRQHandler + IRQ EIC_3_IRQHandler + IRQ EIC_OTHER_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ PORT_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_NSCHK_IRQHandler + IRQ PAC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_OTHER_IRQHandler + IRQ ADC_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_UNDERRUN_A_IRQHandler + IRQ DAC_EMPTY_IRQHandler + IRQ PTC_IRQHandler + IRQ TRNG_IRQHandler + IRQ TRAM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml11e14a.s b/targets/device/sam/atsaml11e14a.s new file mode 100644 index 00000000..46cb4cc4 --- /dev/null +++ b/targets/device/sam/atsaml11e14a.s @@ -0,0 +1,156 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML11E14A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML11E14A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_0_IRQHandler + .long EIC_1_IRQHandler + .long EIC_2_IRQHandler + .long EIC_3_IRQHandler + .long EIC_OTHER_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_IRQHandler + .long PORT_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_NSCHK_IRQHandler + .long PAC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long ADC_OTHER_IRQHandler + .long ADC_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_UNDERRUN_A_IRQHandler + .long DAC_EMPTY_IRQHandler + .long PTC_IRQHandler + .long TRNG_IRQHandler + .long TRAM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_0_IRQHandler + IRQ EIC_1_IRQHandler + IRQ EIC_2_IRQHandler + IRQ EIC_3_IRQHandler + IRQ EIC_OTHER_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ PORT_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_NSCHK_IRQHandler + IRQ PAC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_OTHER_IRQHandler + IRQ ADC_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_UNDERRUN_A_IRQHandler + IRQ DAC_EMPTY_IRQHandler + IRQ PTC_IRQHandler + IRQ TRNG_IRQHandler + IRQ TRAM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml11e15a.s b/targets/device/sam/atsaml11e15a.s new file mode 100644 index 00000000..2f58e367 --- /dev/null +++ b/targets/device/sam/atsaml11e15a.s @@ -0,0 +1,156 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML11E15A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML11E15A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_0_IRQHandler + .long EIC_1_IRQHandler + .long EIC_2_IRQHandler + .long EIC_3_IRQHandler + .long EIC_OTHER_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_IRQHandler + .long PORT_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_NSCHK_IRQHandler + .long PAC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long ADC_OTHER_IRQHandler + .long ADC_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_UNDERRUN_A_IRQHandler + .long DAC_EMPTY_IRQHandler + .long PTC_IRQHandler + .long TRNG_IRQHandler + .long TRAM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_0_IRQHandler + IRQ EIC_1_IRQHandler + IRQ EIC_2_IRQHandler + IRQ EIC_3_IRQHandler + IRQ EIC_OTHER_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ PORT_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_NSCHK_IRQHandler + IRQ PAC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_OTHER_IRQHandler + IRQ ADC_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_UNDERRUN_A_IRQHandler + IRQ DAC_EMPTY_IRQHandler + IRQ PTC_IRQHandler + IRQ TRNG_IRQHandler + IRQ TRAM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml11e16a.s b/targets/device/sam/atsaml11e16a.s new file mode 100644 index 00000000..c154f51c --- /dev/null +++ b/targets/device/sam/atsaml11e16a.s @@ -0,0 +1,156 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML11E16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML11E16A Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_0_IRQHandler + .long EIC_1_IRQHandler + .long EIC_2_IRQHandler + .long EIC_3_IRQHandler + .long EIC_OTHER_IRQHandler + .long FREQM_IRQHandler + .long NVMCTRL_IRQHandler + .long PORT_IRQHandler + .long DMAC_0_IRQHandler + .long DMAC_1_IRQHandler + .long DMAC_2_IRQHandler + .long DMAC_3_IRQHandler + .long DMAC_OTHER_IRQHandler + .long EVSYS_0_IRQHandler + .long EVSYS_1_IRQHandler + .long EVSYS_2_IRQHandler + .long EVSYS_3_IRQHandler + .long EVSYS_NSCHK_IRQHandler + .long PAC_IRQHandler + .long SERCOM0_0_IRQHandler + .long SERCOM0_1_IRQHandler + .long SERCOM0_2_IRQHandler + .long SERCOM0_OTHER_IRQHandler + .long SERCOM1_0_IRQHandler + .long SERCOM1_1_IRQHandler + .long SERCOM1_2_IRQHandler + .long SERCOM1_OTHER_IRQHandler + .long SERCOM2_0_IRQHandler + .long SERCOM2_1_IRQHandler + .long SERCOM2_2_IRQHandler + .long SERCOM2_OTHER_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long ADC_OTHER_IRQHandler + .long ADC_RESRDY_IRQHandler + .long AC_IRQHandler + .long DAC_UNDERRUN_A_IRQHandler + .long DAC_EMPTY_IRQHandler + .long PTC_IRQHandler + .long TRNG_IRQHandler + .long TRAM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_0_IRQHandler + IRQ EIC_1_IRQHandler + IRQ EIC_2_IRQHandler + IRQ EIC_3_IRQHandler + IRQ EIC_OTHER_IRQHandler + IRQ FREQM_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ PORT_IRQHandler + IRQ DMAC_0_IRQHandler + IRQ DMAC_1_IRQHandler + IRQ DMAC_2_IRQHandler + IRQ DMAC_3_IRQHandler + IRQ DMAC_OTHER_IRQHandler + IRQ EVSYS_0_IRQHandler + IRQ EVSYS_1_IRQHandler + IRQ EVSYS_2_IRQHandler + IRQ EVSYS_3_IRQHandler + IRQ EVSYS_NSCHK_IRQHandler + IRQ PAC_IRQHandler + IRQ SERCOM0_0_IRQHandler + IRQ SERCOM0_1_IRQHandler + IRQ SERCOM0_2_IRQHandler + IRQ SERCOM0_OTHER_IRQHandler + IRQ SERCOM1_0_IRQHandler + IRQ SERCOM1_1_IRQHandler + IRQ SERCOM1_2_IRQHandler + IRQ SERCOM1_OTHER_IRQHandler + IRQ SERCOM2_0_IRQHandler + IRQ SERCOM2_1_IRQHandler + IRQ SERCOM2_2_IRQHandler + IRQ SERCOM2_OTHER_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ ADC_OTHER_IRQHandler + IRQ ADC_RESRDY_IRQHandler + IRQ AC_IRQHandler + IRQ DAC_UNDERRUN_A_IRQHandler + IRQ DAC_EMPTY_IRQHandler + IRQ PTC_IRQHandler + IRQ TRNG_IRQHandler + IRQ TRAM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22g16a.s b/targets/device/sam/atsaml22g16a.s new file mode 100644 index 00000000..710419da --- /dev/null +++ b/targets/device/sam/atsaml22g16a.s @@ -0,0 +1,130 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22G16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22G16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 48-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22g17a.s b/targets/device/sam/atsaml22g17a.s new file mode 100644 index 00000000..7150340c --- /dev/null +++ b/targets/device/sam/atsaml22g17a.s @@ -0,0 +1,130 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22G17A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22G17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 49-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22g18a.s b/targets/device/sam/atsaml22g18a.s new file mode 100644 index 00000000..274fb2c2 --- /dev/null +++ b/targets/device/sam/atsaml22g18a.s @@ -0,0 +1,130 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22G18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22G18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 49-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22j16a.s b/targets/device/sam/atsaml22j16a.s new file mode 100644 index 00000000..bc18d0b3 --- /dev/null +++ b/targets/device/sam/atsaml22j16a.s @@ -0,0 +1,130 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22J16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22J16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22j17a.s b/targets/device/sam/atsaml22j17a.s new file mode 100644 index 00000000..4b29eff6 --- /dev/null +++ b/targets/device/sam/atsaml22j17a.s @@ -0,0 +1,130 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22J17A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22J17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22j18a.s b/targets/device/sam/atsaml22j18a.s new file mode 100644 index 00000000..1fb6a083 --- /dev/null +++ b/targets/device/sam/atsaml22j18a.s @@ -0,0 +1,130 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22J18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22J18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 64-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long 0 + .long 0 + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22n16a.s b/targets/device/sam/atsaml22n16a.s new file mode 100644 index 00000000..74584d43 --- /dev/null +++ b/targets/device/sam/atsaml22n16a.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22N16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22N16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 100-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22n17a.s b/targets/device/sam/atsaml22n17a.s new file mode 100644 index 00000000..0aa39757 --- /dev/null +++ b/targets/device/sam/atsaml22n17a.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22N17A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22N17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 100-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsaml22n18a.s b/targets/device/sam/atsaml22n18a.s new file mode 100644 index 00000000..58b12b2e --- /dev/null +++ b/targets/device/sam/atsaml22n18a.s @@ -0,0 +1,132 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAML22N18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAML22N18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 100-pin package +*/ + +// Copyright (c) 2018 Microchip Technology Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SYSTEM_IRQHandler + .long WDT_IRQHandler + .long RTC_IRQHandler + .long EIC_IRQHandler + .long FREQM_IRQHandler + .long USB_IRQHandler + .long NVMCTRL_IRQHandler + .long DMAC_IRQHandler + .long EVSYS_IRQHandler + .long SERCOM0_IRQHandler + .long SERCOM1_IRQHandler + .long SERCOM2_IRQHandler + .long SERCOM3_IRQHandler + .long SERCOM4_IRQHandler + .long SERCOM5_IRQHandler + .long TCC0_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long ADC_IRQHandler + .long AC_IRQHandler + .long 0 + .long SLCD_IRQHandler + .long AES_IRQHandler + .long TRNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SYSTEM_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ EIC_IRQHandler + IRQ FREQM_IRQHandler + IRQ USB_IRQHandler + IRQ NVMCTRL_IRQHandler + IRQ DMAC_IRQHandler + IRQ EVSYS_IRQHandler + IRQ SERCOM0_IRQHandler + IRQ SERCOM1_IRQHandler + IRQ SERCOM2_IRQHandler + IRQ SERCOM3_IRQHandler + IRQ SERCOM4_IRQHandler + IRQ SERCOM5_IRQHandler + IRQ TCC0_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ ADC_IRQHandler + IRQ AC_IRQHandler + IRQ SLCD_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamr21e16a.s b/targets/device/sam/atsamr21e16a.s new file mode 100644 index 00000000..e25fc318 --- /dev/null +++ b/targets/device/sam/atsamr21e16a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMR21E16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMR21E16A device: Cortex-M0+ Microcontroller with 64KB Flash, 16KB SRAM, 233-pin package (refer to http://www.atmel.com/devices/SAMR21E16A.aspx for more) +*/ + +// ============================================================================ +// Atmel Microcontroller Software Support +// ============================================================================ +// Copyright (c) 2016 Atmel Corporation, +// a wholly owned subsidiary of Microchip Technology Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the Licence at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_INTREQ_IRQHandler + .long SYSCTRL_INTREQ_IRQHandler + .long WDT_INTREQ_IRQHandler + .long RTC_INTREQ_IRQHandler + .long EIC_INTREQ_IRQHandler + .long NVMCTRL_INTREQ_IRQHandler + .long DMAC_INTREQ_IRQHandler + .long USB_INTREQ_IRQHandler + .long EVSYS_INTREQ_IRQHandler + .long SERCOM0_INTREQ_IRQHandler + .long SERCOM1_INTREQ_IRQHandler + .long SERCOM2_INTREQ_IRQHandler + .long SERCOM3_INTREQ_IRQHandler + .long SERCOM4_INTREQ_IRQHandler + .long SERCOM5_INTREQ_IRQHandler + .long TCC0_INTREQ_IRQHandler + .long TCC1_INTREQ_IRQHandler + .long TCC2_INTREQ_IRQHandler + .long TC3_INTREQ_IRQHandler + .long TC4_INTREQ_IRQHandler + .long TC5_INTREQ_IRQHandler + .long TC6_INTREQ_IRQHandler + .long TC7_INTREQ_IRQHandler + .long ADC_INTREQ_IRQHandler + .long AC_INTREQ_IRQHandler + .long DAC_INTREQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_INTREQ_IRQHandler + IRQ SYSCTRL_INTREQ_IRQHandler + IRQ WDT_INTREQ_IRQHandler + IRQ RTC_INTREQ_IRQHandler + IRQ EIC_INTREQ_IRQHandler + IRQ NVMCTRL_INTREQ_IRQHandler + IRQ DMAC_INTREQ_IRQHandler + IRQ USB_INTREQ_IRQHandler + IRQ EVSYS_INTREQ_IRQHandler + IRQ SERCOM0_INTREQ_IRQHandler + IRQ SERCOM1_INTREQ_IRQHandler + IRQ SERCOM2_INTREQ_IRQHandler + IRQ SERCOM3_INTREQ_IRQHandler + IRQ SERCOM4_INTREQ_IRQHandler + IRQ SERCOM5_INTREQ_IRQHandler + IRQ TCC0_INTREQ_IRQHandler + IRQ TCC1_INTREQ_IRQHandler + IRQ TCC2_INTREQ_IRQHandler + IRQ TC3_INTREQ_IRQHandler + IRQ TC4_INTREQ_IRQHandler + IRQ TC5_INTREQ_IRQHandler + IRQ TC6_INTREQ_IRQHandler + IRQ TC7_INTREQ_IRQHandler + IRQ ADC_INTREQ_IRQHandler + IRQ AC_INTREQ_IRQHandler + IRQ DAC_INTREQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamr21e17a.s b/targets/device/sam/atsamr21e17a.s new file mode 100644 index 00000000..66c56538 --- /dev/null +++ b/targets/device/sam/atsamr21e17a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMR21E17A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMR21E17A device: Cortex-M0+ Microcontroller with 128KB Flash, 32KB SRAM, 233-pin package (refer to http://www.atmel.com/devices/SAMR21E17A.aspx for more) +*/ + +// ============================================================================ +// Atmel Microcontroller Software Support +// ============================================================================ +// Copyright (c) 2016 Atmel Corporation, +// a wholly owned subsidiary of Microchip Technology Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the Licence at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_INTREQ_IRQHandler + .long SYSCTRL_INTREQ_IRQHandler + .long WDT_INTREQ_IRQHandler + .long RTC_INTREQ_IRQHandler + .long EIC_INTREQ_IRQHandler + .long NVMCTRL_INTREQ_IRQHandler + .long DMAC_INTREQ_IRQHandler + .long USB_INTREQ_IRQHandler + .long EVSYS_INTREQ_IRQHandler + .long SERCOM0_INTREQ_IRQHandler + .long SERCOM1_INTREQ_IRQHandler + .long SERCOM2_INTREQ_IRQHandler + .long SERCOM3_INTREQ_IRQHandler + .long SERCOM4_INTREQ_IRQHandler + .long SERCOM5_INTREQ_IRQHandler + .long TCC0_INTREQ_IRQHandler + .long TCC1_INTREQ_IRQHandler + .long TCC2_INTREQ_IRQHandler + .long TC3_INTREQ_IRQHandler + .long TC4_INTREQ_IRQHandler + .long TC5_INTREQ_IRQHandler + .long TC6_INTREQ_IRQHandler + .long TC7_INTREQ_IRQHandler + .long ADC_INTREQ_IRQHandler + .long AC_INTREQ_IRQHandler + .long DAC_INTREQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_INTREQ_IRQHandler + IRQ SYSCTRL_INTREQ_IRQHandler + IRQ WDT_INTREQ_IRQHandler + IRQ RTC_INTREQ_IRQHandler + IRQ EIC_INTREQ_IRQHandler + IRQ NVMCTRL_INTREQ_IRQHandler + IRQ DMAC_INTREQ_IRQHandler + IRQ USB_INTREQ_IRQHandler + IRQ EVSYS_INTREQ_IRQHandler + IRQ SERCOM0_INTREQ_IRQHandler + IRQ SERCOM1_INTREQ_IRQHandler + IRQ SERCOM2_INTREQ_IRQHandler + IRQ SERCOM3_INTREQ_IRQHandler + IRQ SERCOM4_INTREQ_IRQHandler + IRQ SERCOM5_INTREQ_IRQHandler + IRQ TCC0_INTREQ_IRQHandler + IRQ TCC1_INTREQ_IRQHandler + IRQ TCC2_INTREQ_IRQHandler + IRQ TC3_INTREQ_IRQHandler + IRQ TC4_INTREQ_IRQHandler + IRQ TC5_INTREQ_IRQHandler + IRQ TC6_INTREQ_IRQHandler + IRQ TC7_INTREQ_IRQHandler + IRQ ADC_INTREQ_IRQHandler + IRQ AC_INTREQ_IRQHandler + IRQ DAC_INTREQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamr21e18a.s b/targets/device/sam/atsamr21e18a.s new file mode 100644 index 00000000..6a633133 --- /dev/null +++ b/targets/device/sam/atsamr21e18a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMR21E18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMR21E18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 233-pin package (refer to http://www.atmel.com/devices/SAMR21E18A.aspx for more) +*/ + +// ============================================================================ +// Atmel Microcontroller Software Support +// ============================================================================ +// Copyright (c) 2016 Atmel Corporation, +// a wholly owned subsidiary of Microchip Technology Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the Licence at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_INTREQ_IRQHandler + .long SYSCTRL_INTREQ_IRQHandler + .long WDT_INTREQ_IRQHandler + .long RTC_INTREQ_IRQHandler + .long EIC_INTREQ_IRQHandler + .long NVMCTRL_INTREQ_IRQHandler + .long DMAC_INTREQ_IRQHandler + .long USB_INTREQ_IRQHandler + .long EVSYS_INTREQ_IRQHandler + .long SERCOM0_INTREQ_IRQHandler + .long SERCOM1_INTREQ_IRQHandler + .long SERCOM2_INTREQ_IRQHandler + .long SERCOM3_INTREQ_IRQHandler + .long SERCOM4_INTREQ_IRQHandler + .long SERCOM5_INTREQ_IRQHandler + .long TCC0_INTREQ_IRQHandler + .long TCC1_INTREQ_IRQHandler + .long TCC2_INTREQ_IRQHandler + .long TC3_INTREQ_IRQHandler + .long TC4_INTREQ_IRQHandler + .long TC5_INTREQ_IRQHandler + .long TC6_INTREQ_IRQHandler + .long TC7_INTREQ_IRQHandler + .long ADC_INTREQ_IRQHandler + .long AC_INTREQ_IRQHandler + .long DAC_INTREQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_INTREQ_IRQHandler + IRQ SYSCTRL_INTREQ_IRQHandler + IRQ WDT_INTREQ_IRQHandler + IRQ RTC_INTREQ_IRQHandler + IRQ EIC_INTREQ_IRQHandler + IRQ NVMCTRL_INTREQ_IRQHandler + IRQ DMAC_INTREQ_IRQHandler + IRQ USB_INTREQ_IRQHandler + IRQ EVSYS_INTREQ_IRQHandler + IRQ SERCOM0_INTREQ_IRQHandler + IRQ SERCOM1_INTREQ_IRQHandler + IRQ SERCOM2_INTREQ_IRQHandler + IRQ SERCOM3_INTREQ_IRQHandler + IRQ SERCOM4_INTREQ_IRQHandler + IRQ SERCOM5_INTREQ_IRQHandler + IRQ TCC0_INTREQ_IRQHandler + IRQ TCC1_INTREQ_IRQHandler + IRQ TCC2_INTREQ_IRQHandler + IRQ TC3_INTREQ_IRQHandler + IRQ TC4_INTREQ_IRQHandler + IRQ TC5_INTREQ_IRQHandler + IRQ TC6_INTREQ_IRQHandler + IRQ TC7_INTREQ_IRQHandler + IRQ ADC_INTREQ_IRQHandler + IRQ AC_INTREQ_IRQHandler + IRQ DAC_INTREQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamr21e19a.s b/targets/device/sam/atsamr21e19a.s new file mode 100644 index 00000000..faf90711 --- /dev/null +++ b/targets/device/sam/atsamr21e19a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMR21E19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMR21E19A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, SIP48_RF233_FL512KB-pin package (refer to http://www.atmel.com/devices/SAMR21E19A.aspx for more) +*/ + +// ============================================================================ +// Atmel Microcontroller Software Support +// ============================================================================ +// Copyright (c) 2016 Atmel Corporation, +// a wholly owned subsidiary of Microchip Technology Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the Licence at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_INTREQ_IRQHandler + .long SYSCTRL_INTREQ_IRQHandler + .long WDT_INTREQ_IRQHandler + .long RTC_INTREQ_IRQHandler + .long EIC_INTREQ_IRQHandler + .long NVMCTRL_INTREQ_IRQHandler + .long DMAC_INTREQ_IRQHandler + .long USB_INTREQ_IRQHandler + .long EVSYS_INTREQ_IRQHandler + .long SERCOM0_INTREQ_IRQHandler + .long SERCOM1_INTREQ_IRQHandler + .long SERCOM2_INTREQ_IRQHandler + .long SERCOM3_INTREQ_IRQHandler + .long SERCOM4_INTREQ_IRQHandler + .long SERCOM5_INTREQ_IRQHandler + .long TCC0_INTREQ_IRQHandler + .long TCC1_INTREQ_IRQHandler + .long TCC2_INTREQ_IRQHandler + .long TC3_INTREQ_IRQHandler + .long TC4_INTREQ_IRQHandler + .long TC5_INTREQ_IRQHandler + .long TC6_INTREQ_IRQHandler + .long TC7_INTREQ_IRQHandler + .long ADC_INTREQ_IRQHandler + .long AC_INTREQ_IRQHandler + .long DAC_INTREQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_INTREQ_IRQHandler + IRQ SYSCTRL_INTREQ_IRQHandler + IRQ WDT_INTREQ_IRQHandler + IRQ RTC_INTREQ_IRQHandler + IRQ EIC_INTREQ_IRQHandler + IRQ NVMCTRL_INTREQ_IRQHandler + IRQ DMAC_INTREQ_IRQHandler + IRQ USB_INTREQ_IRQHandler + IRQ EVSYS_INTREQ_IRQHandler + IRQ SERCOM0_INTREQ_IRQHandler + IRQ SERCOM1_INTREQ_IRQHandler + IRQ SERCOM2_INTREQ_IRQHandler + IRQ SERCOM3_INTREQ_IRQHandler + IRQ SERCOM4_INTREQ_IRQHandler + IRQ SERCOM5_INTREQ_IRQHandler + IRQ TCC0_INTREQ_IRQHandler + IRQ TCC1_INTREQ_IRQHandler + IRQ TCC2_INTREQ_IRQHandler + IRQ TC3_INTREQ_IRQHandler + IRQ TC4_INTREQ_IRQHandler + IRQ TC5_INTREQ_IRQHandler + IRQ TC6_INTREQ_IRQHandler + IRQ TC7_INTREQ_IRQHandler + IRQ ADC_INTREQ_IRQHandler + IRQ AC_INTREQ_IRQHandler + IRQ DAC_INTREQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamr21g16a.s b/targets/device/sam/atsamr21g16a.s new file mode 100644 index 00000000..e0a815ab --- /dev/null +++ b/targets/device/sam/atsamr21g16a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMR21G16A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMR21G16A device: Cortex-M0+ Microcontroller with 64KB Flash, 16KB SRAM, 233-pin package (refer to http://www.atmel.com/devices/SAMR21G16A.aspx for more) +*/ + +// ============================================================================ +// Atmel Microcontroller Software Support +// ============================================================================ +// Copyright (c) 2016 Atmel Corporation, +// a wholly owned subsidiary of Microchip Technology Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the Licence at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_INTREQ_IRQHandler + .long SYSCTRL_INTREQ_IRQHandler + .long WDT_INTREQ_IRQHandler + .long RTC_INTREQ_IRQHandler + .long EIC_INTREQ_IRQHandler + .long NVMCTRL_INTREQ_IRQHandler + .long DMAC_INTREQ_IRQHandler + .long USB_INTREQ_IRQHandler + .long EVSYS_INTREQ_IRQHandler + .long SERCOM0_INTREQ_IRQHandler + .long SERCOM1_INTREQ_IRQHandler + .long SERCOM2_INTREQ_IRQHandler + .long SERCOM3_INTREQ_IRQHandler + .long SERCOM4_INTREQ_IRQHandler + .long SERCOM5_INTREQ_IRQHandler + .long TCC0_INTREQ_IRQHandler + .long TCC1_INTREQ_IRQHandler + .long TCC2_INTREQ_IRQHandler + .long TC3_INTREQ_IRQHandler + .long TC4_INTREQ_IRQHandler + .long TC5_INTREQ_IRQHandler + .long TC6_INTREQ_IRQHandler + .long TC7_INTREQ_IRQHandler + .long ADC_INTREQ_IRQHandler + .long AC_INTREQ_IRQHandler + .long DAC_INTREQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_INTREQ_IRQHandler + IRQ SYSCTRL_INTREQ_IRQHandler + IRQ WDT_INTREQ_IRQHandler + IRQ RTC_INTREQ_IRQHandler + IRQ EIC_INTREQ_IRQHandler + IRQ NVMCTRL_INTREQ_IRQHandler + IRQ DMAC_INTREQ_IRQHandler + IRQ USB_INTREQ_IRQHandler + IRQ EVSYS_INTREQ_IRQHandler + IRQ SERCOM0_INTREQ_IRQHandler + IRQ SERCOM1_INTREQ_IRQHandler + IRQ SERCOM2_INTREQ_IRQHandler + IRQ SERCOM3_INTREQ_IRQHandler + IRQ SERCOM4_INTREQ_IRQHandler + IRQ SERCOM5_INTREQ_IRQHandler + IRQ TCC0_INTREQ_IRQHandler + IRQ TCC1_INTREQ_IRQHandler + IRQ TCC2_INTREQ_IRQHandler + IRQ TC3_INTREQ_IRQHandler + IRQ TC4_INTREQ_IRQHandler + IRQ TC5_INTREQ_IRQHandler + IRQ TC6_INTREQ_IRQHandler + IRQ TC7_INTREQ_IRQHandler + IRQ ADC_INTREQ_IRQHandler + IRQ AC_INTREQ_IRQHandler + IRQ DAC_INTREQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamr21g17a.s b/targets/device/sam/atsamr21g17a.s new file mode 100644 index 00000000..87be1fc9 --- /dev/null +++ b/targets/device/sam/atsamr21g17a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMR21G17A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMR21G17A device: Cortex-M0+ Microcontroller with 128KB Flash, 32KB SRAM, 233-pin package (refer to http://www.atmel.com/devices/SAMR21G17A.aspx for more) +*/ + +// ============================================================================ +// Atmel Microcontroller Software Support +// ============================================================================ +// Copyright (c) 2016 Atmel Corporation, +// a wholly owned subsidiary of Microchip Technology Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the Licence at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_INTREQ_IRQHandler + .long SYSCTRL_INTREQ_IRQHandler + .long WDT_INTREQ_IRQHandler + .long RTC_INTREQ_IRQHandler + .long EIC_INTREQ_IRQHandler + .long NVMCTRL_INTREQ_IRQHandler + .long DMAC_INTREQ_IRQHandler + .long USB_INTREQ_IRQHandler + .long EVSYS_INTREQ_IRQHandler + .long SERCOM0_INTREQ_IRQHandler + .long SERCOM1_INTREQ_IRQHandler + .long SERCOM2_INTREQ_IRQHandler + .long SERCOM3_INTREQ_IRQHandler + .long SERCOM4_INTREQ_IRQHandler + .long SERCOM5_INTREQ_IRQHandler + .long TCC0_INTREQ_IRQHandler + .long TCC1_INTREQ_IRQHandler + .long TCC2_INTREQ_IRQHandler + .long TC3_INTREQ_IRQHandler + .long TC4_INTREQ_IRQHandler + .long TC5_INTREQ_IRQHandler + .long TC6_INTREQ_IRQHandler + .long TC7_INTREQ_IRQHandler + .long ADC_INTREQ_IRQHandler + .long AC_INTREQ_IRQHandler + .long DAC_INTREQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_INTREQ_IRQHandler + IRQ SYSCTRL_INTREQ_IRQHandler + IRQ WDT_INTREQ_IRQHandler + IRQ RTC_INTREQ_IRQHandler + IRQ EIC_INTREQ_IRQHandler + IRQ NVMCTRL_INTREQ_IRQHandler + IRQ DMAC_INTREQ_IRQHandler + IRQ USB_INTREQ_IRQHandler + IRQ EVSYS_INTREQ_IRQHandler + IRQ SERCOM0_INTREQ_IRQHandler + IRQ SERCOM1_INTREQ_IRQHandler + IRQ SERCOM2_INTREQ_IRQHandler + IRQ SERCOM3_INTREQ_IRQHandler + IRQ SERCOM4_INTREQ_IRQHandler + IRQ SERCOM5_INTREQ_IRQHandler + IRQ TCC0_INTREQ_IRQHandler + IRQ TCC1_INTREQ_IRQHandler + IRQ TCC2_INTREQ_IRQHandler + IRQ TC3_INTREQ_IRQHandler + IRQ TC4_INTREQ_IRQHandler + IRQ TC5_INTREQ_IRQHandler + IRQ TC6_INTREQ_IRQHandler + IRQ TC7_INTREQ_IRQHandler + IRQ ADC_INTREQ_IRQHandler + IRQ AC_INTREQ_IRQHandler + IRQ DAC_INTREQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamr21g18a.s b/targets/device/sam/atsamr21g18a.s new file mode 100644 index 00000000..51c2980d --- /dev/null +++ b/targets/device/sam/atsamr21g18a.s @@ -0,0 +1,136 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMR21G18A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Atmel ATSAMR21G18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 233-pin package (refer to http://www.atmel.com/devices/SAMR21G18A.aspx for more) +*/ + +// ============================================================================ +// Atmel Microcontroller Software Support +// ============================================================================ +// Copyright (c) 2016 Atmel Corporation, +// a wholly owned subsidiary of Microchip Technology Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the Licence at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long PM_INTREQ_IRQHandler + .long SYSCTRL_INTREQ_IRQHandler + .long WDT_INTREQ_IRQHandler + .long RTC_INTREQ_IRQHandler + .long EIC_INTREQ_IRQHandler + .long NVMCTRL_INTREQ_IRQHandler + .long DMAC_INTREQ_IRQHandler + .long USB_INTREQ_IRQHandler + .long EVSYS_INTREQ_IRQHandler + .long SERCOM0_INTREQ_IRQHandler + .long SERCOM1_INTREQ_IRQHandler + .long SERCOM2_INTREQ_IRQHandler + .long SERCOM3_INTREQ_IRQHandler + .long SERCOM4_INTREQ_IRQHandler + .long SERCOM5_INTREQ_IRQHandler + .long TCC0_INTREQ_IRQHandler + .long TCC1_INTREQ_IRQHandler + .long TCC2_INTREQ_IRQHandler + .long TC3_INTREQ_IRQHandler + .long TC4_INTREQ_IRQHandler + .long TC5_INTREQ_IRQHandler + .long TC6_INTREQ_IRQHandler + .long TC7_INTREQ_IRQHandler + .long ADC_INTREQ_IRQHandler + .long AC_INTREQ_IRQHandler + .long DAC_INTREQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PM_INTREQ_IRQHandler + IRQ SYSCTRL_INTREQ_IRQHandler + IRQ WDT_INTREQ_IRQHandler + IRQ RTC_INTREQ_IRQHandler + IRQ EIC_INTREQ_IRQHandler + IRQ NVMCTRL_INTREQ_IRQHandler + IRQ DMAC_INTREQ_IRQHandler + IRQ USB_INTREQ_IRQHandler + IRQ EVSYS_INTREQ_IRQHandler + IRQ SERCOM0_INTREQ_IRQHandler + IRQ SERCOM1_INTREQ_IRQHandler + IRQ SERCOM2_INTREQ_IRQHandler + IRQ SERCOM3_INTREQ_IRQHandler + IRQ SERCOM4_INTREQ_IRQHandler + IRQ SERCOM5_INTREQ_IRQHandler + IRQ TCC0_INTREQ_IRQHandler + IRQ TCC1_INTREQ_IRQHandler + IRQ TCC2_INTREQ_IRQHandler + IRQ TC3_INTREQ_IRQHandler + IRQ TC4_INTREQ_IRQHandler + IRQ TC5_INTREQ_IRQHandler + IRQ TC6_INTREQ_IRQHandler + IRQ TC7_INTREQ_IRQHandler + IRQ ADC_INTREQ_IRQHandler + IRQ AC_INTREQ_IRQHandler + IRQ DAC_INTREQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70j19.s b/targets/device/sam/atsams70j19.s new file mode 100644 index 00000000..33bad3a6 --- /dev/null +++ b/targets/device/sam/atsams70j19.s @@ -0,0 +1,182 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70J19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70J19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70j19b.s b/targets/device/sam/atsams70j19b.s new file mode 100644 index 00000000..b61a52a6 --- /dev/null +++ b/targets/device/sam/atsams70j19b.s @@ -0,0 +1,184 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70J19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70J19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70j20.s b/targets/device/sam/atsams70j20.s new file mode 100644 index 00000000..4bdc9c7e --- /dev/null +++ b/targets/device/sam/atsams70j20.s @@ -0,0 +1,182 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70J20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70J20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70j20b.s b/targets/device/sam/atsams70j20b.s new file mode 100644 index 00000000..99e1e644 --- /dev/null +++ b/targets/device/sam/atsams70j20b.s @@ -0,0 +1,184 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70J20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70J20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70j21.s b/targets/device/sam/atsams70j21.s new file mode 100644 index 00000000..b1d62e9e --- /dev/null +++ b/targets/device/sam/atsams70j21.s @@ -0,0 +1,182 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70J21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70J21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70j21b.s b/targets/device/sam/atsams70j21b.s new file mode 100644 index 00000000..3bff36db --- /dev/null +++ b/targets/device/sam/atsams70j21b.s @@ -0,0 +1,184 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70J21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70J21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70n19.s b/targets/device/sam/atsams70n19.s new file mode 100644 index 00000000..1c82b1d5 --- /dev/null +++ b/targets/device/sam/atsams70n19.s @@ -0,0 +1,188 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70N19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70N19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70n19b.s b/targets/device/sam/atsams70n19b.s new file mode 100644 index 00000000..4a365d99 --- /dev/null +++ b/targets/device/sam/atsams70n19b.s @@ -0,0 +1,192 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70N19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70N19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70n20.s b/targets/device/sam/atsams70n20.s new file mode 100644 index 00000000..62f1ef36 --- /dev/null +++ b/targets/device/sam/atsams70n20.s @@ -0,0 +1,188 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70N20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70N20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70n20b.s b/targets/device/sam/atsams70n20b.s new file mode 100644 index 00000000..9af368d7 --- /dev/null +++ b/targets/device/sam/atsams70n20b.s @@ -0,0 +1,192 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70N20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70N20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70n21.s b/targets/device/sam/atsams70n21.s new file mode 100644 index 00000000..e3d1ff61 --- /dev/null +++ b/targets/device/sam/atsams70n21.s @@ -0,0 +1,188 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70N21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70N21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70n21b.s b/targets/device/sam/atsams70n21b.s new file mode 100644 index 00000000..1a8aef52 --- /dev/null +++ b/targets/device/sam/atsams70n21b.s @@ -0,0 +1,192 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70N21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70N21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70q19.s b/targets/device/sam/atsams70q19.s new file mode 100644 index 00000000..381ef7b5 --- /dev/null +++ b/targets/device/sam/atsams70q19.s @@ -0,0 +1,192 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70Q19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70Q19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70q19b.s b/targets/device/sam/atsams70q19b.s new file mode 100644 index 00000000..b8f953a6 --- /dev/null +++ b/targets/device/sam/atsams70q19b.s @@ -0,0 +1,198 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70Q19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70Q19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70q20.s b/targets/device/sam/atsams70q20.s new file mode 100644 index 00000000..5effa0e7 --- /dev/null +++ b/targets/device/sam/atsams70q20.s @@ -0,0 +1,192 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70Q20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70Q20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70q20b.s b/targets/device/sam/atsams70q20b.s new file mode 100644 index 00000000..f9471b5d --- /dev/null +++ b/targets/device/sam/atsams70q20b.s @@ -0,0 +1,198 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70Q20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70Q20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70q21.s b/targets/device/sam/atsams70q21.s new file mode 100644 index 00000000..f1da7857 --- /dev/null +++ b/targets/device/sam/atsams70q21.s @@ -0,0 +1,192 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70Q21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70Q21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsams70q21b.s b/targets/device/sam/atsams70q21b.s new file mode 100644 index 00000000..b5c39e53 --- /dev/null +++ b/targets/device/sam/atsams70q21b.s @@ -0,0 +1,198 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMS70Q21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMS70Q21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70j19.s b/targets/device/sam/atsamv70j19.s new file mode 100644 index 00000000..f5e3a728 --- /dev/null +++ b/targets/device/sam/atsamv70j19.s @@ -0,0 +1,188 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70J19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70J19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70j19b.s b/targets/device/sam/atsamv70j19b.s new file mode 100644 index 00000000..c971cca2 --- /dev/null +++ b/targets/device/sam/atsamv70j19b.s @@ -0,0 +1,187 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70J19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70J19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70j20.s b/targets/device/sam/atsamv70j20.s new file mode 100644 index 00000000..0a7fde04 --- /dev/null +++ b/targets/device/sam/atsamv70j20.s @@ -0,0 +1,186 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70J20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70J20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70j20b.s b/targets/device/sam/atsamv70j20b.s new file mode 100644 index 00000000..f147b658 --- /dev/null +++ b/targets/device/sam/atsamv70j20b.s @@ -0,0 +1,187 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70J20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70J20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70n19.s b/targets/device/sam/atsamv70n19.s new file mode 100644 index 00000000..6b1d02f7 --- /dev/null +++ b/targets/device/sam/atsamv70n19.s @@ -0,0 +1,191 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70N19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70N19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70n19b.s b/targets/device/sam/atsamv70n19b.s new file mode 100644 index 00000000..f34f1fc9 --- /dev/null +++ b/targets/device/sam/atsamv70n19b.s @@ -0,0 +1,197 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70N19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70N19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70n20.s b/targets/device/sam/atsamv70n20.s new file mode 100644 index 00000000..931e4c60 --- /dev/null +++ b/targets/device/sam/atsamv70n20.s @@ -0,0 +1,193 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70N20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70N20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70n20b.s b/targets/device/sam/atsamv70n20b.s new file mode 100644 index 00000000..578232fb --- /dev/null +++ b/targets/device/sam/atsamv70n20b.s @@ -0,0 +1,197 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70N20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70N20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70q19.s b/targets/device/sam/atsamv70q19.s new file mode 100644 index 00000000..1609d136 --- /dev/null +++ b/targets/device/sam/atsamv70q19.s @@ -0,0 +1,197 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70Q19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70Q19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70q19b.s b/targets/device/sam/atsamv70q19b.s new file mode 100644 index 00000000..c861ec1e --- /dev/null +++ b/targets/device/sam/atsamv70q19b.s @@ -0,0 +1,203 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70Q19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70Q19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70q20.s b/targets/device/sam/atsamv70q20.s new file mode 100644 index 00000000..efb0497b --- /dev/null +++ b/targets/device/sam/atsamv70q20.s @@ -0,0 +1,197 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70Q20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70Q20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv70q20b.s b/targets/device/sam/atsamv70q20b.s new file mode 100644 index 00000000..a7094d18 --- /dev/null +++ b/targets/device/sam/atsamv70q20b.s @@ -0,0 +1,203 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV70Q20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV70Q20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long 0 + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long 0 + .long 0 + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71j19.s b/targets/device/sam/atsamv71j19.s new file mode 100644 index 00000000..daa8401d --- /dev/null +++ b/targets/device/sam/atsamv71j19.s @@ -0,0 +1,188 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71J19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71J19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long 0 + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71j19b.s b/targets/device/sam/atsamv71j19b.s new file mode 100644 index 00000000..b5fc90de --- /dev/null +++ b/targets/device/sam/atsamv71j19b.s @@ -0,0 +1,198 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71J19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71J19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long 0 + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71j20.s b/targets/device/sam/atsamv71j20.s new file mode 100644 index 00000000..1329fb91 --- /dev/null +++ b/targets/device/sam/atsamv71j20.s @@ -0,0 +1,189 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71J20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71J20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71j20b.s b/targets/device/sam/atsamv71j20b.s new file mode 100644 index 00000000..6d6b7470 --- /dev/null +++ b/targets/device/sam/atsamv71j20b.s @@ -0,0 +1,198 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71J20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71J20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long 0 + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71j21.s b/targets/device/sam/atsamv71j21.s new file mode 100644 index 00000000..d886ec1b --- /dev/null +++ b/targets/device/sam/atsamv71j21.s @@ -0,0 +1,189 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71J21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71J21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71j21b.s b/targets/device/sam/atsamv71j21b.s new file mode 100644 index 00000000..9c8d4870 --- /dev/null +++ b/targets/device/sam/atsamv71j21b.s @@ -0,0 +1,198 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71J21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71J21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long 0 + .long PIOD_IRQHandler + .long 0 + .long 0 + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long 0 + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long 0 + .long 0 + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long 0 + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long 0 + .long 0 + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long 0 + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ PIOD_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71n19.s b/targets/device/sam/atsamv71n19.s new file mode 100644 index 00000000..770388da --- /dev/null +++ b/targets/device/sam/atsamv71n19.s @@ -0,0 +1,196 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71N19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71N19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71n19b.s b/targets/device/sam/atsamv71n19b.s new file mode 100644 index 00000000..1a075a95 --- /dev/null +++ b/targets/device/sam/atsamv71n19b.s @@ -0,0 +1,207 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71N19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71N19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71n20.s b/targets/device/sam/atsamv71n20.s new file mode 100644 index 00000000..cf5bbed1 --- /dev/null +++ b/targets/device/sam/atsamv71n20.s @@ -0,0 +1,195 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71N20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71N20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long 0 + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71n20b.s b/targets/device/sam/atsamv71n20b.s new file mode 100644 index 00000000..225f66f2 --- /dev/null +++ b/targets/device/sam/atsamv71n20b.s @@ -0,0 +1,207 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71N20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71N20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71n21.s b/targets/device/sam/atsamv71n21.s new file mode 100644 index 00000000..ee535cb9 --- /dev/null +++ b/targets/device/sam/atsamv71n21.s @@ -0,0 +1,195 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71N21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71N21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long 0 + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71n21b.s b/targets/device/sam/atsamv71n21b.s new file mode 100644 index 00000000..22bf0f38 --- /dev/null +++ b/targets/device/sam/atsamv71n21b.s @@ -0,0 +1,207 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71N21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71N21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long 0 + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long 0 + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long 0 + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long 0 + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long 0 + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71q19.s b/targets/device/sam/atsamv71q19.s new file mode 100644 index 00000000..38a8db17 --- /dev/null +++ b/targets/device/sam/atsamv71q19.s @@ -0,0 +1,200 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71Q19.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71Q19 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71q19b.s b/targets/device/sam/atsamv71q19b.s new file mode 100644 index 00000000..b2198727 --- /dev/null +++ b/targets/device/sam/atsamv71q19b.s @@ -0,0 +1,212 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71Q19B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71Q19B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71q20.s b/targets/device/sam/atsamv71q20.s new file mode 100644 index 00000000..2c351933 --- /dev/null +++ b/targets/device/sam/atsamv71q20.s @@ -0,0 +1,200 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71Q20.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71Q20 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71q20b.s b/targets/device/sam/atsamv71q20b.s new file mode 100644 index 00000000..1ac41214 --- /dev/null +++ b/targets/device/sam/atsamv71q20b.s @@ -0,0 +1,212 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71Q20B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71Q20B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71q21.s b/targets/device/sam/atsamv71q21.s new file mode 100644 index 00000000..85068d3b --- /dev/null +++ b/targets/device/sam/atsamv71q21.s @@ -0,0 +1,200 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71Q21.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71Q21 Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long 0 + .long 0 + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/sam/atsamv71q21b.s b/targets/device/sam/atsamv71q21b.s new file mode 100644 index 00000000..c0db6235 --- /dev/null +++ b/targets/device/sam/atsamv71q21b.s @@ -0,0 +1,212 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from ATSAMV71Q21B.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel + +/* +// Microchip ATSAMV71Q21B Microcontroller +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long SUPC_IRQHandler + .long RSTC_IRQHandler + .long RTC_IRQHandler + .long RTT_IRQHandler + .long WDT_IRQHandler + .long PMC_IRQHandler + .long EFC_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long 0 + .long PIOA_IRQHandler + .long PIOB_IRQHandler + .long PIOC_IRQHandler + .long USART0_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long PIOD_IRQHandler + .long PIOE_IRQHandler + .long HSMCI_IRQHandler + .long TWIHS0_IRQHandler + .long TWIHS1_IRQHandler + .long SPI0_IRQHandler + .long SSC_IRQHandler + .long TC0_IRQHandler + .long TC1_IRQHandler + .long TC2_IRQHandler + .long TC3_IRQHandler + .long TC4_IRQHandler + .long TC5_IRQHandler + .long AFEC0_IRQHandler + .long DACC_IRQHandler + .long PWM0_IRQHandler + .long ICM_IRQHandler + .long ACC_IRQHandler + .long USBHS_IRQHandler + .long MCAN0_INT0_IRQHandler + .long MCAN0_INT1_IRQHandler + .long MCAN1_INT0_IRQHandler + .long MCAN1_INT1_IRQHandler + .long GMAC_IRQHandler + .long AFEC1_IRQHandler + .long TWIHS2_IRQHandler + .long SPI1_IRQHandler + .long QSPI_IRQHandler + .long UART2_IRQHandler + .long UART3_IRQHandler + .long UART4_IRQHandler + .long TC6_IRQHandler + .long TC7_IRQHandler + .long TC8_IRQHandler + .long TC9_IRQHandler + .long TC10_IRQHandler + .long TC11_IRQHandler + .long MLB_IRQHandler + .long 0 + .long 0 + .long AES_IRQHandler + .long TRNG_IRQHandler + .long XDMAC_IRQHandler + .long ISI_IRQHandler + .long PWM1_IRQHandler + .long FPU_IRQHandler + .long SDRAMC_IRQHandler + .long RSWDT_IRQHandler + .long CCW_IRQHandler + .long CCF_IRQHandler + .long GMAC_Q1_IRQHandler + .long GMAC_Q2_IRQHandler + .long IXC_IRQHandler + .long I2SC0_IRQHandler + .long I2SC1_IRQHandler + .long GMAC_Q3_IRQHandler + .long GMAC_Q4_IRQHandler + .long GMAC_Q5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ SUPC_IRQHandler + IRQ RSTC_IRQHandler + IRQ RTC_IRQHandler + IRQ RTT_IRQHandler + IRQ WDT_IRQHandler + IRQ PMC_IRQHandler + IRQ EFC_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PIOA_IRQHandler + IRQ PIOB_IRQHandler + IRQ PIOC_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ PIOD_IRQHandler + IRQ PIOE_IRQHandler + IRQ HSMCI_IRQHandler + IRQ TWIHS0_IRQHandler + IRQ TWIHS1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SSC_IRQHandler + IRQ TC0_IRQHandler + IRQ TC1_IRQHandler + IRQ TC2_IRQHandler + IRQ TC3_IRQHandler + IRQ TC4_IRQHandler + IRQ TC5_IRQHandler + IRQ AFEC0_IRQHandler + IRQ DACC_IRQHandler + IRQ PWM0_IRQHandler + IRQ ICM_IRQHandler + IRQ ACC_IRQHandler + IRQ USBHS_IRQHandler + IRQ MCAN0_INT0_IRQHandler + IRQ MCAN0_INT1_IRQHandler + IRQ MCAN1_INT0_IRQHandler + IRQ MCAN1_INT1_IRQHandler + IRQ GMAC_IRQHandler + IRQ AFEC1_IRQHandler + IRQ TWIHS2_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ UART4_IRQHandler + IRQ TC6_IRQHandler + IRQ TC7_IRQHandler + IRQ TC8_IRQHandler + IRQ TC9_IRQHandler + IRQ TC10_IRQHandler + IRQ TC11_IRQHandler + IRQ MLB_IRQHandler + IRQ AES_IRQHandler + IRQ TRNG_IRQHandler + IRQ XDMAC_IRQHandler + IRQ ISI_IRQHandler + IRQ PWM1_IRQHandler + IRQ FPU_IRQHandler + IRQ SDRAMC_IRQHandler + IRQ RSWDT_IRQHandler + IRQ CCW_IRQHandler + IRQ CCF_IRQHandler + IRQ GMAC_Q1_IRQHandler + IRQ GMAC_Q2_IRQHandler + IRQ IXC_IRQHandler + IRQ I2SC0_IRQHandler + IRQ I2SC1_IRQHandler + IRQ GMAC_Q3_IRQHandler + IRQ GMAC_Q4_IRQHandler + IRQ GMAC_Q5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f0x0.s b/targets/device/stm32/stm32f0x0.s new file mode 100644 index 00000000..bb10c645 --- /dev/null +++ b/targets/device/stm32/stm32f0x0.s @@ -0,0 +1,127 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f0x0.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F0x0 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long 0 + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_3_IRQHandler + .long DMA1_CH4_5_IRQHandler + .long ADC_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long 0 + .long TIM3_IRQHandler + .long TIM6_IRQHandler + .long 0 + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_4_5_6_IRQHandler + .long 0 + .long USB_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_3_IRQHandler + IRQ DMA1_CH4_5_IRQHandler + IRQ ADC_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_4_5_6_IRQHandler + IRQ USB_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f0x1.s b/targets/device/stm32/stm32f0x1.s new file mode 100644 index 00000000..ffa61c08 --- /dev/null +++ b/targets/device/stm32/stm32f0x1.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f0x1.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F0x1 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_CRS_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long TSC_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_3_DMA2_CH1_2_IRQHandler + .long DMA1_CH4_5_6_7_DMA2_CH3_4_5_IRQHandler + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_4_5_6_7_8_IRQHandler + .long CEC_CAN_IRQHandler + .long USB_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_CRS_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ TSC_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_3_DMA2_CH1_2_IRQHandler + IRQ DMA1_CH4_5_6_7_DMA2_CH3_4_5_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_4_5_6_7_8_IRQHandler + IRQ CEC_CAN_IRQHandler + IRQ USB_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f0x2.s b/targets/device/stm32/stm32f0x2.s new file mode 100644 index 00000000..41471852 --- /dev/null +++ b/targets/device/stm32/stm32f0x2.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f0x2.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F0x2 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_CRS_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long TSC_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_3_IRQHandler + .long DMA1_CH4_5_6_7_IRQHandler + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_4_IRQHandler + .long CEC_CAN_IRQHandler + .long USB_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_CRS_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ TSC_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_3_IRQHandler + IRQ DMA1_CH4_5_6_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_4_IRQHandler + IRQ CEC_CAN_IRQHandler + IRQ USB_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f0x8.s b/targets/device/stm32/stm32f0x8.s new file mode 100644 index 00000000..89638503 --- /dev/null +++ b/targets/device/stm32/stm32f0x8.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f0x8.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F0x8 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_CRS_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long TSC_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_3_DMA2_CH1_2_IRQHandler + .long DMA1_CH4_5_6_7_DMA2_CH3_4_5_IRQHandler + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_4_5_6_7_8_IRQHandler + .long CEC_CAN_IRQHandler + .long USB_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_CRS_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ TSC_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_3_DMA2_CH1_2_IRQHandler + IRQ DMA1_CH4_5_6_7_DMA2_CH3_4_5_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_4_5_6_7_8_IRQHandler + IRQ CEC_CAN_IRQHandler + IRQ USB_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f100.s b/targets/device/stm32/stm32f100.s new file mode 100644 index 00000000..4f9a95b0 --- /dev/null +++ b/targets/device/stm32/stm32f100.s @@ -0,0 +1,180 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f100.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F100 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMPER_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_TIM17_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTCAlarm_IRQHandler + .long CEC_IRQHandler + .long TIM12_IRQHandler + .long TIM13_IRQHandler + .long TIM14_IRQHandler + .long 0 + .long 0 + .long FSMC_IRQHandler + .long 0 + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Channel1_IRQHandler + .long DMA2_Channel2_IRQHandler + .long DMA2_Channel3_IRQHandler + .long DMA2_Channel4_5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_TIM17_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ CEC_IRQHandler + IRQ TIM12_IRQHandler + IRQ TIM13_IRQHandler + IRQ TIM14_IRQHandler + IRQ FSMC_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Channel1_IRQHandler + IRQ DMA2_Channel2_IRQHandler + IRQ DMA2_Channel3_IRQHandler + IRQ DMA2_Channel4_5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f101.s b/targets/device/stm32/stm32f101.s new file mode 100644 index 00000000..92a1218a --- /dev/null +++ b/targets/device/stm32/stm32f101.s @@ -0,0 +1,187 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f101.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F101 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMPER_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_CAN_TX_IRQHandler + .long USB_LP_CAN_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long USBWakeup_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_Channel4_5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_CAN_TX_IRQHandler + IRQ USB_LP_CAN_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ USBWakeup_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_Channel4_5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f102.s b/targets/device/stm32/stm32f102.s new file mode 100644 index 00000000..59c12cac --- /dev/null +++ b/targets/device/stm32/stm32f102.s @@ -0,0 +1,187 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f102.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F102 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMPER_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_CAN_TX_IRQHandler + .long USB_LP_CAN_RX0_IRQHandler + .long CAN_RX1_IRQHandler + .long CAN_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTCAlarm_IRQHandler + .long USBWakeup_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Channel1_IRQHandler + .long DMA2_Channel2_IRQHandler + .long DMA2_Channel3_IRQHandler + .long DMA2_Channel4_5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_CAN_TX_IRQHandler + IRQ USB_LP_CAN_RX0_IRQHandler + IRQ CAN_RX1_IRQHandler + IRQ CAN_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ USBWakeup_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Channel1_IRQHandler + IRQ DMA2_Channel2_IRQHandler + IRQ DMA2_Channel3_IRQHandler + IRQ DMA2_Channel4_5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f103.s b/targets/device/stm32/stm32f103.s new file mode 100644 index 00000000..a99aacab --- /dev/null +++ b/targets/device/stm32/stm32f103.s @@ -0,0 +1,186 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f103.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F103 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMPER_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_CAN_TX_IRQHandler + .long USB_LP_CAN_RX0_IRQHandler + .long CAN_RX1_IRQHandler + .long CAN_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTCAlarm_IRQHandler + .long 0 + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Channel1_IRQHandler + .long DMA2_Channel2_IRQHandler + .long DMA2_Channel3_IRQHandler + .long DMA2_Channel4_5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_CAN_TX_IRQHandler + IRQ USB_LP_CAN_RX0_IRQHandler + IRQ CAN_RX1_IRQHandler + IRQ CAN_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Channel1_IRQHandler + IRQ DMA2_Channel2_IRQHandler + IRQ DMA2_Channel3_IRQHandler + IRQ DMA2_Channel4_5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f107.s b/targets/device/stm32/stm32f107.s new file mode 100644 index 00000000..e4821bdd --- /dev/null +++ b/targets/device/stm32/stm32f107.s @@ -0,0 +1,203 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f107.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F107 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMPER_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_CAN_TX_IRQHandler + .long USB_LP_CAN_RX0_IRQHandler + .long CAN_RX1_IRQHandler + .long CAN_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTCAlarm_IRQHandler + .long USBWakeup_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Channel1_IRQHandler + .long DMA2_Channel2_IRQHandler + .long DMA2_Channel3_IRQHandler + .long DMA2_Channel4_IRQHandler + .long DMA2_Channel5_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_CAN_TX_IRQHandler + IRQ USB_LP_CAN_RX0_IRQHandler + IRQ CAN_RX1_IRQHandler + IRQ CAN_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ USBWakeup_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Channel1_IRQHandler + IRQ DMA2_Channel2_IRQHandler + IRQ DMA2_Channel3_IRQHandler + IRQ DMA2_Channel4_IRQHandler + IRQ DMA2_Channel5_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f215.s b/targets/device/stm32/stm32f215.s new file mode 100644 index 00000000..f11ed7af --- /dev/null +++ b/targets/device/stm32/stm32f215.s @@ -0,0 +1,229 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f215.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F215 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f217.s b/targets/device/stm32/stm32f217.s new file mode 100644 index 00000000..e88e0823 --- /dev/null +++ b/targets/device/stm32/stm32f217.s @@ -0,0 +1,229 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f217.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F217 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f301.s b/targets/device/stm32/stm32f301.s new file mode 100644 index 00000000..2c791fb7 --- /dev/null +++ b/targets/device/stm32/stm32f301.s @@ -0,0 +1,213 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f301.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F301 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQ_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQ_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_TSC_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_IRQ_IRQHandler + .long CAN_TX_IRQ_IRQHandler + .long CAN_RXD_IRQ_IRQHandler + .long CAN_RXI_IRQ_IRQHandler + .long CAN_SCE_IRQ_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM15_IRQ_IRQHandler + .long TIM16_IRQ_IRQHandler + .long TIM17_IRQ_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long 0 + .long 0 + .long I2C1_EV_IRQ_IRQHandler + .long I2C1_ER_IRQ_IRQHandler + .long I2C2_EV_IRQ_IRQHandler + .long I2C2_ER_IRQ_IRQHandler + .long SPI1_IRQ_IRQHandler + .long SPI2_IRQ_IRQHandler + .long USART1_IRQ_IRQHandler + .long USART2_EXTI26_IRQHandler + .long USART3_EXTI28_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IT_IRQ_IRQHandler + .long CEC_IRQ_IRQHandler + .long TIM12_IRQ_IRQHandler + .long TIM13_IRQ_IRQHandler + .long TIM14_IRQ_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SPI3_IRQ_IRQHandler + .long 0 + .long 0 + .long TIM6_DAC1_IRQHandler + .long TIM7_IRQ_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long ADC_SD1_IRQ_IRQHandler + .long ADC_SD2_IRQ_IRQHandler + .long ADC_SD3_IRQ_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_5_6_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long I2C3_EV_IRQ_IRQHandler + .long I2C3_ER_IRQ_IRQHandler + .long USB_HP_IRQ_IRQHandler + .long USB_LP_IRQ_IRQHandler + .long USB_WAKEUP_IRQ_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQ_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQ_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_TSC_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_IRQ_IRQHandler + IRQ CAN_TX_IRQ_IRQHandler + IRQ CAN_RXD_IRQ_IRQHandler + IRQ CAN_RXI_IRQ_IRQHandler + IRQ CAN_SCE_IRQ_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM15_IRQ_IRQHandler + IRQ TIM16_IRQ_IRQHandler + IRQ TIM17_IRQ_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM18_DAC3_IRQ_IRQHandler + IRQ TIM2_IRQHandler + IRQ I2C1_EV_IRQ_IRQHandler + IRQ I2C1_EV_EXTI23_IRQHandler + IRQ I2C1_ER_IRQ_IRQHandler + IRQ I2C2_EV_IRQ_IRQHandler + IRQ I2C2_ER_IRQ_IRQHandler + IRQ SPI1_IRQ_IRQHandler + IRQ SPI2_IRQ_IRQHandler + IRQ USART1_IRQ_IRQHandler + IRQ USART1_EXTI25_IRQHandler + IRQ USART2_EXTI26_IRQHandler + IRQ USART2_IRQ_IRQHandler + IRQ USART3_EXTI28_IRQHandler + IRQ USART3_IRQ_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IT_IRQ_IRQHandler + IRQ CEC_IRQ_IRQHandler + IRQ TIM12_IRQ_IRQHandler + IRQ TIM13_IRQ_IRQHandler + IRQ TIM14_IRQ_IRQHandler + IRQ SPI3_IRQ_IRQHandler + IRQ TIM6_DAC1_IRQHandler + IRQ TIM7_IRQ_IRQHandler + IRQ ADC_SD1_IRQ_IRQHandler + IRQ ADC_SD2_IRQ_IRQHandler + IRQ ADC_SD3_IRQ_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_5_6_IRQHandler + IRQ I2C3_EV_IRQ_IRQHandler + IRQ I2C3_ER_IRQ_IRQHandler + IRQ USB_HP_IRQ_IRQHandler + IRQ USB_LP_IRQ_IRQHandler + IRQ USB_WAKEUP_IRQ_IRQHandler + IRQ USB_WKUP_EXTI_IRQHandler + IRQ FPU_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f302.s b/targets/device/stm32/stm32f302.s new file mode 100644 index 00000000..921e16de --- /dev/null +++ b/targets/device/stm32/stm32f302.s @@ -0,0 +1,213 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f302.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F302 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_TSC_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_CAN_TX_IRQHandler + .long USB_LP_CAN_RX0_IRQHandler + .long CAN_RX1_IRQHandler + .long CAN_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_TIM17_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_EXTI23_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_EXTI24_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_EXTI25_IRQHandler + .long USART2_EXTI26_IRQHandler + .long USART3_EXTI28_IRQHandler + .long EXTI15_10_IRQHandler + .long RTCAlarm_IRQHandler + .long USB_WKUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long 0 + .long FMC_IRQHandler + .long 0 + .long 0 + .long SPI3_IRQHandler + .long UART4_EXTI34_IRQHandler + .long UART5_EXTI35_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long 0 + .long 0 + .long 0 + .long COMP1_2_3_IRQHandler + .long COMP4_5_6_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long USB_WKUP_EXTI_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_TSC_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_CAN_TX_IRQHandler + IRQ USB_LP_CAN_RX0_IRQHandler + IRQ CAN_RX1_IRQHandler + IRQ CAN_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_TIM17_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_EXTI23_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_EXTI24_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_EXTI25_IRQHandler + IRQ USART2_EXTI26_IRQHandler + IRQ USART3_EXTI28_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ USB_WKUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ FMC_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_EXTI34_IRQHandler + IRQ UART5_EXTI35_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_5_6_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ USB_WKUP_EXTI_IRQHandler + IRQ FPU_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f303.s b/targets/device/stm32/stm32f303.s new file mode 100644 index 00000000..053436dd --- /dev/null +++ b/targets/device/stm32/stm32f303.s @@ -0,0 +1,228 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f303.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F303 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_TSC_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_CAN_TX_IRQHandler + .long USB_LP_CAN_RX0_IRQHandler + .long CAN_RX1_IRQHandler + .long CAN_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_TIM17_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_EXTI23_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_EXTI24_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_EXTI25_IRQHandler + .long USART2_EXTI26_IRQHandler + .long USART3_EXTI28_IRQHandler + .long EXTI15_10_IRQHandler + .long RTCAlarm_IRQHandler + .long USB_WKUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FMC_IRQHandler + .long 0 + .long 0 + .long SPI3_IRQHandler + .long UART4_EXTI34_IRQHandler + .long UART5_EXTI35_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long ADC4_IRQHandler + .long 0 + .long 0 + .long COMP123_IRQHandler + .long COMP456_IRQHandler + .long COMP7_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long USB_WKUP_EXTI_IRQHandler + .long TIM20_BRK_IRQHandler + .long TIM20_UP_IRQHandler + .long TIM20_TRG_COM_IRQHandler + .long TIM20_CC_IRQHandler + .long FPU_IRQHandler + .long 0 + .long 0 + .long SPI4_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_TSC_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_CAN_TX_IRQHandler + IRQ USB_LP_CAN_RX0_IRQHandler + IRQ CAN_RX1_IRQHandler + IRQ CAN_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_TIM17_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_EXTI23_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_EXTI24_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_EXTI25_IRQHandler + IRQ USART2_EXTI26_IRQHandler + IRQ USART3_EXTI28_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ USB_WKUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FMC_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_EXTI34_IRQHandler + IRQ UART5_EXTI35_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ ADC4_IRQHandler + IRQ COMP123_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP456_IRQHandler + IRQ COMP4_5_6_IRQHandler + IRQ COMP7_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ USB_WKUP_EXTI_IRQHandler + IRQ TIM20_BRK_IRQHandler + IRQ TIM20_UP_IRQHandler + IRQ TIM20_TRG_COM_IRQHandler + IRQ TIM20_CC_IRQHandler + IRQ FPU_IRQHandler + IRQ SPI4_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f373.s b/targets/device/stm32/stm32f373.s new file mode 100644 index 00000000..48d7f90a --- /dev/null +++ b/targets/device/stm32/stm32f373.s @@ -0,0 +1,213 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f373.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F373 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_TS_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_IRQHandler + .long CAN_TX_IRQHandler + .long CAN_RXD_IRQHandler + .long CAN_RXI_IRQHandler + .long CAN_SCE_IRQHandler + .long EXTI5_9_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long TIM18_DAC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long CEC_IRQHandler + .long TIM12_IRQHandler + .long TIM13_IRQHandler + .long TIM14_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long 0 + .long 0 + .long TIM6_DAC1_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long SDADC1_IRQHandler + .long SDADC2_IRQHandler + .long SDADC3_IRQHandler + .long COMP1_2_3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long USB_WAKEUP_IRQHandler + .long 0 + .long TIM19_IRQHandler + .long 0 + .long 0 + .long FPU_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_TS_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_IRQHandler + IRQ CAN_TX_IRQHandler + IRQ CAN_RXD_IRQHandler + IRQ CAN_RXI_IRQHandler + IRQ CAN_SCE_IRQHandler + IRQ EXTI5_9_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ TIM18_DAC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ CEC_IRQHandler + IRQ TIM12_IRQHandler + IRQ TIM13_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ TIM6_DAC1_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ SDADC1_IRQHandler + IRQ SDADC2_IRQHandler + IRQ SDADC3_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ USB_WAKEUP_IRQHandler + IRQ TIM19_IRQHandler + IRQ FPU_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f3x4.s b/targets/device/stm32/stm32f3x4.s new file mode 100644 index 00000000..0a79510b --- /dev/null +++ b/targets/device/stm32/stm32f3x4.s @@ -0,0 +1,199 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f3x4.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F3x4 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_TSC_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_CAN_TX_IRQHandler + .long USB_LP_CAN_RX0_IRQHandler + .long CAN_RX1_IRQHandler + .long CAN_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_TIM17_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQ_IRQHandler + .long 0 + .long I2C1_EV_EXTI23_IRQHandler + .long I2C1_ER_IRQHandler + .long 0 + .long 0 + .long SPI1_IRQHandler + .long 0 + .long USART1_EXTI25_IRQHandler + .long USART2_EXTI26_IRQHandler + .long USART3_EXTI28_IRQHandler + .long EXTI15_10_IRQHandler + .long RTCAlarm_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TIM6_DAC1_IRQHandler + .long TIM7_DAC2_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long COMP1_2_3_IRQHandler + .long COMP4_5_6_IRQHandler + .long 0 + .long HRTIM_MST_IRQHandler + .long HRTIM_TIMA_IRQHandler + .long HRTIM_TIMB_IRQHandler + .long HRTIM_TIMC_IRQHandler + .long HRTIM_TIMD_IRQHandler + .long HRTIM_TIME_IRQHandler + .long HRTIM_FLT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_TSC_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_CAN_TX_IRQHandler + IRQ USB_LP_CAN_RX0_IRQHandler + IRQ CAN_RX1_IRQHandler + IRQ CAN_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_TIM17_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQ_IRQHandler + IRQ I2C1_EV_EXTI23_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART1_EXTI25_IRQHandler + IRQ USART2_EXTI26_IRQHandler + IRQ USART3_EXTI28_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ TIM6_DAC1_IRQHandler + IRQ TIM7_DAC2_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_5_6_IRQHandler + IRQ HRTIM_MST_IRQHandler + IRQ HRTIM_TIMA_IRQHandler + IRQ HRTIM_TIMB_IRQHandler + IRQ HRTIM_TIMC_IRQHandler + IRQ HRTIM_TIMD_IRQHandler + IRQ HRTIM_TIME_IRQHandler + IRQ HRTIM_FLT_IRQHandler + IRQ FPU_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f401.s b/targets/device/stm32/stm32f401.s new file mode 100644 index 00000000..80c9d383 --- /dev/null +++ b/targets/device/stm32/stm32f401.s @@ -0,0 +1,207 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f401.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F401 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_STREAM0_IRQHandler + .long DMA1_STREAM1_IRQHandler + .long DMA1_STREAM2_IRQHandler + .long DMA1_STREAM3_IRQHandler + .long DMA1_STREAM4_IRQHandler + .long DMA1_STREAM5_IRQHandler + .long DMA1_STREAM6_IRQHandler + .long ADC_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA1_STREAM7_IRQHandler + .long 0 + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA2_STREAM0_IRQHandler + .long DMA2_STREAM1_IRQHandler + .long DMA2_STREAM2_IRQHandler + .long DMA2_STREAM3_IRQHandler + .long DMA2_STREAM4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long OTG_FS_IRQHandler + .long DMA2_STREAM5_IRQHandler + .long DMA2_STREAM6_IRQHandler + .long DMA2_STREAM7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + .long 0 + .long 0 + .long SPI4_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_STREAM0_IRQHandler + IRQ DMA1_STREAM1_IRQHandler + IRQ DMA1_STREAM2_IRQHandler + IRQ DMA1_STREAM3_IRQHandler + IRQ DMA1_STREAM4_IRQHandler + IRQ DMA1_STREAM5_IRQHandler + IRQ DMA1_STREAM6_IRQHandler + IRQ ADC_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ DMA1_STREAM7_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ DMA2_STREAM0_IRQHandler + IRQ DMA2_STREAM1_IRQHandler + IRQ DMA2_STREAM2_IRQHandler + IRQ DMA2_STREAM3_IRQHandler + IRQ DMA2_STREAM4_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_STREAM5_IRQHandler + IRQ DMA2_STREAM6_IRQHandler + IRQ DMA2_STREAM7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ FPU_IRQHandler + IRQ SPI4_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f405.s b/targets/device/stm32/stm32f405.s new file mode 100644 index 00000000..17f9dd08 --- /dev/null +++ b/targets/device/stm32/stm32f405.s @@ -0,0 +1,240 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f405.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F405 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long 0 + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f407.s b/targets/device/stm32/stm32f407.s new file mode 100644 index 00000000..87bcaefe --- /dev/null +++ b/targets/device/stm32/stm32f407.s @@ -0,0 +1,240 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f407.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F407 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long 0 + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long LCD_TFT_IRQHandler + .long LCD_TFT_1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ LCD_TFT_IRQHandler + IRQ LCD_TFT_1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f410.s b/targets/device/stm32/stm32f410.s new file mode 100644 index 00000000..62a0c7bc --- /dev/null +++ b/targets/device/stm32/stm32f410.s @@ -0,0 +1,219 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f410.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F410 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long PWM1_UP_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long 0 + .long 0 + .long 0 + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA1_Stream7_IRQHandler + .long 0 + .long 0 + .long TIM5_IRQHandler + .long 0 + .long 0 + .long 0 + .long TIM6_DAC1_IRQHandler + .long 0 + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long 0 + .long EXTI19_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long EXTI20_IRQHandler + .long 0 + .long 0 + .long 0 + .long RNG_IRQHandler + .long FPU_IRQHandler + .long 0 + .long 0 + .long 0 + .long SPI5_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long LPTIM1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ PWM1_UP_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ TIM5_IRQHandler + IRQ TIM6_DAC1_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ EXTI19_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ EXTI20_IRQHandler + IRQ RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ SPI5_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ LPTIM1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f411.s b/targets/device/stm32/stm32f411.s new file mode 100644 index 00000000..2700796b --- /dev/null +++ b/targets/device/stm32/stm32f411.s @@ -0,0 +1,210 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f411.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F411 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA1_Stream7_IRQHandler + .long 0 + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + .long 0 + .long 0 + .long SPI4_IRQHandler + .long SPI5_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ FPU_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f412.s b/targets/device/stm32/stm32f412.s new file mode 100644 index 00000000..693d0bed --- /dev/null +++ b/targets/device/stm32/stm32f412.s @@ -0,0 +1,243 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f412.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F412 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM12_IRQHandler + .long TIM13_IRQHandler + .long TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long 0 + .long 0 + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long 0 + .long 0 + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long Quad_SPI_IRQHandler + .long 0 + .long 0 + .long I2CFMP1_event_IRQHandler + .long I2CFMP1_error_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM12_IRQHandler + IRQ TIM13_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ Quad_SPI_IRQHandler + IRQ I2CFMP1_event_IRQHandler + IRQ I2CFMP1_error_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f413.s b/targets/device/stm32/stm32f413.s new file mode 100644 index 00000000..c665489f --- /dev/null +++ b/targets/device/stm32/stm32f413.s @@ -0,0 +1,263 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f413.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F413 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long 0 + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EVT_IRQHandler + .long I2C1_ERR_IRQHandler + .long I2C2_EVT_IRQHandler + .long I2C2_ERR_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long EXTI17_RTC_Alarm_IRQHandler + .long 0 + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long USART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_GLB_IT_DAC1_DAC2_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long CAN3_TX_IRQHandler + .long CAN3_RX0_IRQHandler + .long CAN3_RX1_IRQHandler + .long CAN3_SCE_IRQHandler + .long 0 + .long CRYPTO_IRQHandler + .long RNG_IRQHandler + .long FPU_IRQHandler + .long USART7_IRQHandler + .long USART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long 0 + .long SAI1_IRQHandler + .long UART9_IRQHandler + .long UART10_IRQHandler + .long 0 + .long 0 + .long QuadSPI_IRQHandler + .long 0 + .long 0 + .long I2CFMP1event_IRQHandler + .long I2CFMP1error_IRQHandler + .long lptim1_OR_it_eit_23_IRQHandler + .long DFSDM2_FILTER1_IRQHandler + .long DFSDM2_FILTER2_IRQHandler + .long DFSDM2_FILTER3_IRQHandler + .long DFSDM2_FILTER4_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EVT_IRQHandler + IRQ I2C1_ERR_IRQHandler + IRQ I2C2_EVT_IRQHandler + IRQ I2C2_ERR_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ EXTI17_RTC_Alarm_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ USART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_GLB_IT_DAC1_DAC2_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ CAN3_TX_IRQHandler + IRQ CAN3_RX0_IRQHandler + IRQ CAN3_RX1_IRQHandler + IRQ CAN3_SCE_IRQHandler + IRQ CRYPTO_IRQHandler + IRQ RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ USART7_IRQHandler + IRQ USART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SAI1_IRQHandler + IRQ UART9_IRQHandler + IRQ UART10_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ I2CFMP1event_IRQHandler + IRQ I2CFMP1error_IRQHandler + IRQ lptim1_OR_it_eit_23_IRQHandler + IRQ DFSDM2_FILTER1_IRQHandler + IRQ DFSDM2_FILTER2_IRQHandler + IRQ DFSDM2_FILTER3_IRQHandler + IRQ DFSDM2_FILTER4_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f427.s b/targets/device/stm32/stm32f427.s new file mode 100644 index 00000000..aa78ac4e --- /dev/null +++ b/targets/device/stm32/stm32f427.s @@ -0,0 +1,246 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f427.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F427 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long 0 + .long LCD_TFT_IRQHandler + .long LCD_TFT_1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ LCD_TFT_IRQHandler + IRQ LCD_TFT_1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f429.s b/targets/device/stm32/stm32f429.s new file mode 100644 index 00000000..6a6db368 --- /dev/null +++ b/targets/device/stm32/stm32f429.s @@ -0,0 +1,249 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f429.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F429 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LCD_TFT_IRQHandler + .long LCD_TFT_1_IRQHandler + .long DMA2D_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LCD_TFT_IRQHandler + IRQ LCD_TFT_1_IRQHandler + IRQ DMA2D_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f446.s b/targets/device/stm32/stm32f446.s new file mode 100644 index 00000000..2c735f67 --- /dev/null +++ b/targets/device/stm32/stm32f446.s @@ -0,0 +1,237 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f446.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F446 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long 0 + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DCMI_IRQHandler + .long 0 + .long 0 + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long 0 + .long 0 + .long 0 + .long LCD_TFT_IRQHandler + .long LCD_TFT_1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DCMI_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ LCD_TFT_IRQHandler + IRQ LCD_TFT_1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f469.s b/targets/device/stm32/stm32f469.s new file mode 100644 index 00000000..9be2bf06 --- /dev/null +++ b/targets/device/stm32/stm32f469.s @@ -0,0 +1,253 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f469.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F469 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LCD_TFT_IRQHandler + .long LCD_TFT_1_IRQHandler + .long DMA2D_IRQHandler + .long QUADSPI_IRQHandler + .long DSIHOST_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LCD_TFT_IRQHandler + IRQ LCD_TFT_1_IRQHandler + IRQ DMA2D_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ DSIHOST_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f730.s b/targets/device/stm32/stm32f730.s new file mode 100644 index 00000000..2f1fa16b --- /dev/null +++ b/targets/device/stm32/stm32f730.s @@ -0,0 +1,255 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f730.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F730 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long 0 + .long AES_IRQHandler + .long RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long 0 + .long SAI1_IRQHandler + .long 0 + .long 0 + .long 0 + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LP_Timer1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SDMMC2_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LP_Timer1_IRQHandler + IRQ SDMMC2_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f745.s b/targets/device/stm32/stm32f745.s new file mode 100644 index 00000000..69bd1500 --- /dev/null +++ b/targets/device/stm32/stm32f745.s @@ -0,0 +1,264 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f745.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F745 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LPTimer1_IRQHandler + .long HDMI_CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIFRX_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LPTimer1_IRQHandler + IRQ LP_Timer1_IRQHandler + IRQ HDMI_CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIFRX_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f750.s b/targets/device/stm32/stm32f750.s new file mode 100644 index 00000000..c4c3f4d9 --- /dev/null +++ b/targets/device/stm32/stm32f750.s @@ -0,0 +1,263 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f750.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F750 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LPTIMER1_IRQHandler + .long HDMI_CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIFRX_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LPTIMER1_IRQHandler + IRQ HDMI_CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIFRX_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f765.s b/targets/device/stm32/stm32f765.s new file mode 100644 index 00000000..34b60f80 --- /dev/null +++ b/targets/device/stm32/stm32f765.s @@ -0,0 +1,288 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f765.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F765 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LPTimer1_IRQHandler + .long HDMI_CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIFRX_IRQHandler + .long DSIHOST_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SDMMC2_IRQHandler + .long CAN3_TX_IRQHandler + .long CAN3_RX0_IRQHandler + .long CAN3_RX1_IRQHandler + .long CAN3_SCE_IRQHandler + .long JPEG_IRQHandler + .long MDIOS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LPTimer1_IRQHandler + IRQ LP_Timer1_IRQHandler + IRQ HDMI_CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIFRX_IRQHandler + IRQ DSIHOST_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SDMMC2_IRQHandler + IRQ CAN3_TX_IRQHandler + IRQ CAN3_RX0_IRQHandler + IRQ CAN3_RX1_IRQHandler + IRQ CAN3_SCE_IRQHandler + IRQ JPEG_IRQHandler + IRQ MDIOS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f7x2.s b/targets/device/stm32/stm32f7x2.s new file mode 100644 index 00000000..714c98fb --- /dev/null +++ b/targets/device/stm32/stm32f7x2.s @@ -0,0 +1,255 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f7x2.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F7x2 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long 0 + .long AES_IRQHandler + .long RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long 0 + .long SAI1_IRQHandler + .long 0 + .long 0 + .long 0 + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LP_Timer1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SDMMC2_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LP_Timer1_IRQHandler + IRQ SDMMC2_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f7x3.s b/targets/device/stm32/stm32f7x3.s new file mode 100644 index 00000000..c183f24f --- /dev/null +++ b/targets/device/stm32/stm32f7x3.s @@ -0,0 +1,255 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f7x3.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F7x3 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FSMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long 0 + .long AES_IRQHandler + .long RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long 0 + .long SAI1_IRQHandler + .long 0 + .long 0 + .long 0 + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LP_Timer1_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SDMMC2_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FSMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LP_Timer1_IRQHandler + IRQ SDMMC2_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f7x6.s b/targets/device/stm32/stm32f7x6.s new file mode 100644 index 00000000..1317b9d4 --- /dev/null +++ b/targets/device/stm32/stm32f7x6.s @@ -0,0 +1,264 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f7x6.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F7x6 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LPTimer1_IRQHandler + .long HDMI_CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIFRX_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LPTimer1_IRQHandler + IRQ LP_Timer1_IRQHandler + IRQ HDMI_CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIFRX_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f7x7.s b/targets/device/stm32/stm32f7x7.s new file mode 100644 index 00000000..79500261 --- /dev/null +++ b/targets/device/stm32/stm32f7x7.s @@ -0,0 +1,287 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f7x7.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F7x7 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LP_Timer1_IRQHandler + .long HDMI_CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIFRX_IRQHandler + .long DSIHOST_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SDMMC2_IRQHandler + .long CAN3_TX_IRQHandler + .long CAN3_RX0_IRQHandler + .long CAN3_RX1_IRQHandler + .long CAN3_SCE_IRQHandler + .long JPEG_IRQHandler + .long MDIOS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LP_Timer1_IRQHandler + IRQ HDMI_CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIFRX_IRQHandler + IRQ DSIHOST_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SDMMC2_IRQHandler + IRQ CAN3_TX_IRQHandler + IRQ CAN3_RX0_IRQHandler + IRQ CAN3_RX1_IRQHandler + IRQ CAN3_SCE_IRQHandler + IRQ JPEG_IRQHandler + IRQ MDIOS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32f7x9.s b/targets/device/stm32/stm32f7x9.s new file mode 100644 index 00000000..af9b4cc6 --- /dev/null +++ b/targets/device/stm32/stm32f7x9.s @@ -0,0 +1,289 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32f7x9.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32F7x9 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Stream0_IRQHandler + .long DMA1_Stream1_IRQHandler + .long DMA1_Stream2_IRQHandler + .long DMA1_Stream3_IRQHandler + .long DMA1_Stream4_IRQHandler + .long DMA1_Stream5_IRQHandler + .long DMA1_Stream6_IRQHandler + .long ADC_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM9_IRQHandler + .long TIM1_UP_TIM10_IRQHandler + .long TIM1_TRG_COM_TIM11_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_Stream7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_Stream0_IRQHandler + .long DMA2_Stream1_IRQHandler + .long DMA2_Stream2_IRQHandler + .long DMA2_Stream3_IRQHandler + .long DMA2_Stream4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_Stream5_IRQHandler + .long DMA2_Stream6_IRQHandler + .long DMA2_Stream7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LCD_TFT_1_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QuadSPI_IRQHandler + .long LPTimer1_IRQHandler + .long HDMI_CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIFRX_IRQHandler + .long DSIHOST_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SDMMC2_IRQHandler + .long CAN3_TX_IRQHandler + .long CAN3_RX0_IRQHandler + .long CAN3_RX1_IRQHandler + .long CAN3_SCE_IRQHandler + .long JPEG_IRQHandler + .long MDIOS_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Stream0_IRQHandler + IRQ DMA1_Stream1_IRQHandler + IRQ DMA1_Stream2_IRQHandler + IRQ DMA1_Stream3_IRQHandler + IRQ DMA1_Stream4_IRQHandler + IRQ DMA1_Stream5_IRQHandler + IRQ DMA1_Stream6_IRQHandler + IRQ ADC_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM9_IRQHandler + IRQ TIM1_UP_TIM10_IRQHandler + IRQ TIM1_TRG_COM_TIM11_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_Stream7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_Stream0_IRQHandler + IRQ DMA2_Stream1_IRQHandler + IRQ DMA2_Stream2_IRQHandler + IRQ DMA2_Stream3_IRQHandler + IRQ DMA2_Stream4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_Stream5_IRQHandler + IRQ DMA2_Stream6_IRQHandler + IRQ DMA2_Stream7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LCD_TFT_1_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QuadSPI_IRQHandler + IRQ LPTimer1_IRQHandler + IRQ LP_Timer1_IRQHandler + IRQ HDMI_CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIFRX_IRQHandler + IRQ DSIHOST_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SDMMC2_IRQHandler + IRQ CAN3_TX_IRQHandler + IRQ CAN3_RX0_IRQHandler + IRQ CAN3_RX1_IRQHandler + IRQ CAN3_SCE_IRQHandler + IRQ JPEG_IRQHandler + IRQ MDIOS_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g030.s b/targets/device/stm32/stm32g030.s new file mode 100644 index 00000000..8dec651a --- /dev/null +++ b/targets/device/stm32/stm32g030.s @@ -0,0 +1,124 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g030.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G030 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_TAMP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long 0 + .long DMA_Channel1_IRQHandler + .long DMA_Channel2_3_IRQHandler + .long DMA_Channel4_5_6_7_IRQHandler + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long 0 + .long 0 + .long TIM14_IRQHandler + .long 0 + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long CEC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_TAMP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DMA_Channel1_IRQHandler + IRQ DMA_Channel2_3_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ CEC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g031.s b/targets/device/stm32/stm32g031.s new file mode 100644 index 00000000..f573775a --- /dev/null +++ b/targets/device/stm32/stm32g031.s @@ -0,0 +1,125 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g031.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G031 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_TAMP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long 0 + .long DMA_Channel1_IRQHandler + .long DMA_Channel2_3_IRQHandler + .long DMA_Channel4_5_6_7_IRQHandler + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long 0 + .long 0 + .long TIM14_IRQHandler + .long 0 + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_USART4_LPUART1_IRQHandler + .long CEC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_TAMP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DMA_Channel1_IRQHandler + IRQ DMA_Channel2_3_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_USART4_LPUART1_IRQHandler + IRQ CEC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g041.s b/targets/device/stm32/stm32g041.s new file mode 100644 index 00000000..7231762d --- /dev/null +++ b/targets/device/stm32/stm32g041.s @@ -0,0 +1,127 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g041.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G041 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_TAMP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long 0 + .long DMA_Channel1_IRQHandler + .long DMA_Channel2_3_IRQHandler + .long DMA_Channel4_5_6_7_IRQHandler + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long 0 + .long 0 + .long TIM14_IRQHandler + .long 0 + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_USART4_LPUART1_IRQHandler + .long CEC_IRQHandler + .long AES_RNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_TAMP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DMA_Channel1_IRQHandler + IRQ DMA_Channel2_3_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_USART4_LPUART1_IRQHandler + IRQ CEC_IRQHandler + IRQ AES_RNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g050.s b/targets/device/stm32/stm32g050.s new file mode 100644 index 00000000..62fbc004 --- /dev/null +++ b/targets/device/stm32/stm32g050.s @@ -0,0 +1,112 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g050.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G050 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5_IRQHandler + .long ADC_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long 0 + .long TIM3_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long 0 + .long 0 + .long USART1_IRQHandler + .long USART2_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5_IRQHandler + IRQ ADC_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g051.s b/targets/device/stm32/stm32g051.s new file mode 100644 index 00000000..5a88ca07 --- /dev/null +++ b/targets/device/stm32/stm32g051.s @@ -0,0 +1,115 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g051.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G051 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA_Channel4_5_6_7_IRQHandler + .long 0 + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long 0 + .long 0 + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long CEC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ CEC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g061.s b/targets/device/stm32/stm32g061.s new file mode 100644 index 00000000..4b6f151a --- /dev/null +++ b/targets/device/stm32/stm32g061.s @@ -0,0 +1,115 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g061.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G061 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA_Channel4_5_6_7_IRQHandler + .long 0 + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long 0 + .long 0 + .long USART1_IRQHandler + .long USART2_IRQHandler + .long 0 + .long CEC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ CEC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g070.s b/targets/device/stm32/stm32g070.s new file mode 100644 index 00000000..af6a12fd --- /dev/null +++ b/targets/device/stm32/stm32g070.s @@ -0,0 +1,127 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g070.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G070 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_STAMP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long 0 + .long DMA_Channel1_IRQHandler + .long DMA_Channel2_3_IRQHandler + .long DMA_Channel4_5_6_7_IRQHandler + .long ADC_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long 0 + .long TIM3_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_USART4_IRQHandler + .long CEC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_STAMP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DMA_Channel1_IRQHandler + IRQ DMA_Channel2_3_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ ADC_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_USART4_IRQHandler + IRQ CEC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g071.s b/targets/device/stm32/stm32g071.s new file mode 100644 index 00000000..b23dfa23 --- /dev/null +++ b/targets/device/stm32/stm32g071.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g071.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G071 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_STAMP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long UCPD1_UCPD2_IRQHandler + .long DMA_Channel1_IRQHandler + .long DMA_Channel2_3_IRQHandler + .long DMA_Channel4_5_6_7_IRQHandler + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_LPTIM1_IRQHandler + .long TIM7_LPTIM2_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_USART4_LPUART1_IRQHandler + .long CEC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_STAMP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ UCPD1_UCPD2_IRQHandler + IRQ DMA_Channel1_IRQHandler + IRQ DMA_Channel2_3_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_LPTIM1_IRQHandler + IRQ TIM7_LPTIM2_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_USART4_LPUART1_IRQHandler + IRQ CEC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g081.s b/targets/device/stm32/stm32g081.s new file mode 100644 index 00000000..09769362 --- /dev/null +++ b/targets/device/stm32/stm32g081.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g081.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G081 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_STAMP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long UCPD1_UCPD2_IRQHandler + .long DMA_Channel1_IRQHandler + .long DMA_Channel2_3_IRQHandler + .long DMA_Channel4_5_6_7_IRQHandler + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_LPTIM1_IRQHandler + .long TIM7_LPTIM2_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_USART4_LPUART1_IRQHandler + .long CEC_IRQHandler + .long AES_RNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_STAMP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ UCPD1_UCPD2_IRQHandler + IRQ DMA_Channel1_IRQHandler + IRQ DMA_Channel2_3_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_LPTIM1_IRQHandler + IRQ TIM7_LPTIM2_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_USART4_LPUART1_IRQHandler + IRQ CEC_IRQHandler + IRQ AES_RNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g0b0.s b/targets/device/stm32/stm32g0b0.s new file mode 100644 index 00000000..57b45cd9 --- /dev/null +++ b/targets/device/stm32/stm32g0b0.s @@ -0,0 +1,113 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g0b0.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G0B0 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA_Channel4_5_6_7_IRQHandler + .long 0 + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long 0 + .long TIM3_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long 0 + .long 0 + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_USART4_USART5_USART6_LPUART1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ DMA_Channel4_5_6_7_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_USART4_USART5_USART6_LPUART1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g0b1.s b/targets/device/stm32/stm32g0b1.s new file mode 100644 index 00000000..c18273c1 --- /dev/null +++ b/targets/device/stm32/stm32g0b1.s @@ -0,0 +1,126 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g0b1.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G0B1 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_TAMP_IRQHandler + .long FLASH_IRQHandler + .long RCC_CRS_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long UCPD1_UCPD2_USB_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_TIM4_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_I2C3_IRQHandler + .long SPI1_IRQHandler + .long SPI2_SPI3_IRQHandler + .long USART1_IRQHandler + .long USART2_LPUART2_IRQHandler + .long USART3_USART4_USART5_USART6_LPUART1_IRQHandler + .long CEC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_TAMP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_CRS_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ UCPD1_UCPD2_USB_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_TIM4_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_I2C3_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_SPI3_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_LPUART2_IRQHandler + IRQ USART3_USART4_USART5_USART6_LPUART1_IRQHandler + IRQ CEC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g0c1.s b/targets/device/stm32/stm32g0c1.s new file mode 100644 index 00000000..d3daf52f --- /dev/null +++ b/targets/device/stm32/stm32g0c1.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g0c1.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G0C1 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_TAMP_IRQHandler + .long FLASH_IRQHandler + .long RCC_CRS_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long UCPD1_UCPD2_USB_IRQHandler + .long 0 + .long 0 + .long 0 + .long ADC_COMP_IRQHandler + .long TIM1_BRK_UP_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_TIM4_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long TIM14_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_IRQHandler + .long I2C2_I2C3_IRQHandler + .long SPI1_IRQHandler + .long SPI2_SPI3_IRQHandler + .long USART1_IRQHandler + .long USART2_LPUART2_IRQHandler + .long USART3_USART4_USART5_USART6_LPUART1_IRQHandler + .long CEC_IRQHandler + .long AES_RNG_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_TAMP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_CRS_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ UCPD1_UCPD2_USB_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ TIM1_BRK_UP_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_TIM4_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM14_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_I2C3_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_SPI3_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_LPUART2_IRQHandler + IRQ USART3_USART4_USART5_USART6_LPUART1_IRQHandler + IRQ CEC_IRQHandler + IRQ AES_RNG_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g431xx.s b/targets/device/stm32/stm32g431xx.s new file mode 100644 index 00000000..fcab0bbb --- /dev/null +++ b/targets/device/stm32/stm32g431xx.s @@ -0,0 +1,240 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g431.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G431xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long 0 + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long 0 + .long 0 + .long LPTIM1_IRQHandler + .long 0 + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long 0 + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long 0 + .long 0 + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRS_IRQHandler + .long SAI_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long 0 + .long 0 + .long DMA2_CH6_IRQHandler + .long 0 + .long 0 + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ FPU_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g441xx.s b/targets/device/stm32/stm32g441xx.s new file mode 100644 index 00000000..ba7e93ff --- /dev/null +++ b/targets/device/stm32/stm32g441xx.s @@ -0,0 +1,240 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g441.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G441xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long 0 + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long 0 + .long 0 + .long LPTIM1_IRQHandler + .long 0 + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long 0 + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long 0 + .long 0 + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRS_IRQHandler + .long SAI_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long 0 + .long 0 + .long DMA2_CH6_IRQHandler + .long 0 + .long 0 + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ FPU_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g471xx.s b/targets/device/stm32/stm32g471xx.s new file mode 100644 index 00000000..96f7c176 --- /dev/null +++ b/targets/device/stm32/stm32g471xx.s @@ -0,0 +1,252 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g471.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G471xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long 0 + .long LPTIM1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long 0 + .long 0 + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRS_IRQHandler + .long SAI_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPI4_IRQHandler + .long AES_IRQHandler + .long FDCAN2_intr0_IRQHandler + .long FDCAN2_intr1_IRQHandler + .long 0 + .long 0 + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long 0 + .long DMA1_CH8_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMA2_CH8_IRQHandler + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ FPU_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPI4_IRQHandler + IRQ AES_IRQHandler + IRQ FDCAN2_intr0_IRQHandler + IRQ FDCAN2_intr1_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ DMA1_CH8_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMA2_CH8_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g473xx.s b/targets/device/stm32/stm32g473xx.s new file mode 100644 index 00000000..3a74943b --- /dev/null +++ b/targets/device/stm32/stm32g473xx.s @@ -0,0 +1,263 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g473.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G473xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FMC_IRQHandler + .long LPTIM1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long ADC4_IRQHandler + .long ADC5_IRQHandler + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_5_6_IRQHandler + .long COMP7_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRS_IRQHandler + .long SAI_IRQHandler + .long TIM20_BRK_IRQHandler + .long TIM20_UP_IRQHandler + .long TIM20_TRG_COM_IRQHandler + .long TIM20_CC_IRQHandler + .long FPU_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPI4_IRQHandler + .long AES_IRQHandler + .long FDCAN2_intr0_IRQHandler + .long FDCAN2_intr1_IRQHandler + .long FDCAN3_intr0_IRQHandler + .long FDCAN3_intr1_IRQHandler + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long QUADSPI_IRQHandler + .long DMA1_CH8_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMA2_CH8_IRQHandler + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FMC_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ ADC4_IRQHandler + IRQ ADC5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_5_6_IRQHandler + IRQ COMP7_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ TIM20_BRK_IRQHandler + IRQ TIM20_UP_IRQHandler + IRQ TIM20_TRG_COM_IRQHandler + IRQ TIM20_CC_IRQHandler + IRQ FPU_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPI4_IRQHandler + IRQ AES_IRQHandler + IRQ FDCAN2_intr0_IRQHandler + IRQ FDCAN2_intr1_IRQHandler + IRQ FDCAN3_intr0_IRQHandler + IRQ FDCAN3_intr1_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ DMA1_CH8_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMA2_CH8_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g474xx.s b/targets/device/stm32/stm32g474xx.s new file mode 100644 index 00000000..d637da63 --- /dev/null +++ b/targets/device/stm32/stm32g474xx.s @@ -0,0 +1,270 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g474.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G474xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FMC_IRQHandler + .long LPTIM1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long ADC4_IRQHandler + .long ADC5_IRQHandler + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_5_6_IRQHandler + .long COMP7_IRQHandler + .long HRTIM_Master_IRQn_IRQHandler + .long HRTIM_TIMA_IRQn_IRQHandler + .long HRTIM_TIMB_IRQn_IRQHandler + .long HRTIM_TIMC_IRQn_IRQHandler + .long HRTIM_TIMD_IRQn_IRQHandler + .long HRTIM_TIME_IRQn_IRQHandler + .long HRTIM_TIM_FLT_IRQn_IRQHandler + .long HRTIM_TIMF_IRQn_IRQHandler + .long CRS_IRQHandler + .long SAI_IRQHandler + .long TIM20_BRK_IRQHandler + .long TIM20_UP_IRQHandler + .long TIM20_TRG_COM_IRQHandler + .long TIM20_CC_IRQHandler + .long FPU_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPI4_IRQHandler + .long 0 + .long FDCAN2_intr0_IRQHandler + .long FDCAN2_intr1_IRQHandler + .long FDCAN3_intr0_IRQHandler + .long FDCAN3_intr1_IRQHandler + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long QUADSPI_IRQHandler + .long DMA1_CH8_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMA2_CH8_IRQHandler + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FMC_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ ADC4_IRQHandler + IRQ ADC5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_5_6_IRQHandler + IRQ COMP7_IRQHandler + IRQ HRTIM_Master_IRQn_IRQHandler + IRQ HRTIM_TIMA_IRQn_IRQHandler + IRQ HRTIM_TIMB_IRQn_IRQHandler + IRQ HRTIM_TIMC_IRQn_IRQHandler + IRQ HRTIM_TIMD_IRQn_IRQHandler + IRQ HRTIM_TIME_IRQn_IRQHandler + IRQ HRTIM_TIM_FLT_IRQn_IRQHandler + IRQ HRTIM_TIMF_IRQn_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ TIM20_BRK_IRQHandler + IRQ TIM20_UP_IRQHandler + IRQ TIM20_TRG_COM_IRQHandler + IRQ TIM20_CC_IRQHandler + IRQ FPU_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPI4_IRQHandler + IRQ FDCAN2_intr0_IRQHandler + IRQ FDCAN2_intr1_IRQHandler + IRQ FDCAN3_intr0_IRQHandler + IRQ FDCAN3_intr1_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ DMA1_CH8_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMA2_CH8_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g483xx.s b/targets/device/stm32/stm32g483xx.s new file mode 100644 index 00000000..63ad62f2 --- /dev/null +++ b/targets/device/stm32/stm32g483xx.s @@ -0,0 +1,263 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g483.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G483xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FMC_IRQHandler + .long LPTIM1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long ADC4_IRQHandler + .long ADC5_IRQHandler + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_5_6_IRQHandler + .long COMP7_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRS_IRQHandler + .long SAI_IRQHandler + .long TIM20_BRK_IRQHandler + .long TIM20_UP_IRQHandler + .long TIM20_TRG_COM_IRQHandler + .long TIM20_CC_IRQHandler + .long FPU_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPI4_IRQHandler + .long AES_IRQHandler + .long FDCAN2_intr0_IRQHandler + .long FDCAN2_intr1_IRQHandler + .long FDCAN3_intr0_IRQHandler + .long FDCAN3_intr1_IRQHandler + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long QUADSPI_IRQHandler + .long DMA1_CH8_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMA2_CH8_IRQHandler + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FMC_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ ADC4_IRQHandler + IRQ ADC5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_5_6_IRQHandler + IRQ COMP7_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ TIM20_BRK_IRQHandler + IRQ TIM20_UP_IRQHandler + IRQ TIM20_TRG_COM_IRQHandler + IRQ TIM20_CC_IRQHandler + IRQ FPU_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPI4_IRQHandler + IRQ AES_IRQHandler + IRQ FDCAN2_intr0_IRQHandler + IRQ FDCAN2_intr1_IRQHandler + IRQ FDCAN3_intr0_IRQHandler + IRQ FDCAN3_intr1_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ DMA1_CH8_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMA2_CH8_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g484xx.s b/targets/device/stm32/stm32g484xx.s new file mode 100644 index 00000000..c4399337 --- /dev/null +++ b/targets/device/stm32/stm32g484xx.s @@ -0,0 +1,271 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g484.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G484xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FMC_IRQHandler + .long LPTIM1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long ADC4_IRQHandler + .long ADC5_IRQHandler + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_5_6_IRQHandler + .long COMP7_IRQHandler + .long HRTIM_Master_IRQn_IRQHandler + .long HRTIM_TIMA_IRQn_IRQHandler + .long HRTIM_TIMB_IRQn_IRQHandler + .long HRTIM_TIMC_IRQn_IRQHandler + .long HRTIM_TIMD_IRQn_IRQHandler + .long HRTIM_TIME_IRQn_IRQHandler + .long HRTIM_TIM_FLT_IRQn_IRQHandler + .long HRTIM_TIMF_IRQn_IRQHandler + .long CRS_IRQHandler + .long SAI_IRQHandler + .long TIM20_BRK_IRQHandler + .long TIM20_UP_IRQHandler + .long TIM20_TRG_COM_IRQHandler + .long TIM20_CC_IRQHandler + .long FPU_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPI4_IRQHandler + .long AES_IRQHandler + .long FDCAN2_intr0_IRQHandler + .long FDCAN2_intr1_IRQHandler + .long FDCAN3_intr0_IRQHandler + .long FDCAN3_intr1_IRQHandler + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long QUADSPI_IRQHandler + .long DMA1_CH8_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMA2_CH8_IRQHandler + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FMC_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ ADC4_IRQHandler + IRQ ADC5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_5_6_IRQHandler + IRQ COMP7_IRQHandler + IRQ HRTIM_Master_IRQn_IRQHandler + IRQ HRTIM_TIMA_IRQn_IRQHandler + IRQ HRTIM_TIMB_IRQn_IRQHandler + IRQ HRTIM_TIMC_IRQn_IRQHandler + IRQ HRTIM_TIMD_IRQn_IRQHandler + IRQ HRTIM_TIME_IRQn_IRQHandler + IRQ HRTIM_TIM_FLT_IRQn_IRQHandler + IRQ HRTIM_TIMF_IRQn_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ TIM20_BRK_IRQHandler + IRQ TIM20_UP_IRQHandler + IRQ TIM20_TRG_COM_IRQHandler + IRQ TIM20_CC_IRQHandler + IRQ FPU_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPI4_IRQHandler + IRQ AES_IRQHandler + IRQ FDCAN2_intr0_IRQHandler + IRQ FDCAN2_intr1_IRQHandler + IRQ FDCAN3_intr0_IRQHandler + IRQ FDCAN3_intr1_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ DMA1_CH8_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMA2_CH8_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g491xx.s b/targets/device/stm32/stm32g491xx.s new file mode 100644 index 00000000..706a965d --- /dev/null +++ b/targets/device/stm32/stm32g491xx.s @@ -0,0 +1,241 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g491.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G491xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long 0 + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long 0 + .long LPTIM1_IRQHandler + .long 0 + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long 0 + .long 0 + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRS_IRQHandler + .long SAI_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long 0 + .long 0 + .long DMA2_CH6_IRQHandler + .long 0 + .long 0 + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ FPU_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32g4a1xx.s b/targets/device/stm32/stm32g4a1xx.s new file mode 100644 index 00000000..66e61426 --- /dev/null +++ b/targets/device/stm32/stm32g4a1xx.s @@ -0,0 +1,242 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32g4a1.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32G4A1xx +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long 0 + .long ADC1_2_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long fdcan1_intr1_it_IRQHandler + .long fdcan1_intr0_it_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long USBWakeUP_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long 0 + .long LPTIM1_IRQHandler + .long 0 + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long 0 + .long 0 + .long UCPD1_IRQHandler + .long COMP1_2_3_IRQHandler + .long COMP4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long CRS_IRQHandler + .long SAI_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long FPU_IRQHandler + .long 0 + .long 0 + .long 0 + .long AES_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long RNG_IRQHandler + .long LPUART_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long DMAMUX_OVR_IRQHandler + .long 0 + .long 0 + .long DMA2_CH6_IRQHandler + .long 0 + .long 0 + .long Cordic_IRQHandler + .long FMAC_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ fdcan1_intr1_it_IRQHandler + IRQ fdcan1_intr0_it_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ USBWakeUP_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ UCPD1_IRQHandler + IRQ COMP1_2_3_IRQHandler + IRQ COMP4_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI_IRQHandler + IRQ FPU_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ LPUART_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ Cordic_IRQHandler + IRQ FMAC_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32h73x.s b/targets/device/stm32/stm32h73x.s new file mode 100644 index 00000000..c8ea0c61 --- /dev/null +++ b/targets/device/stm32/stm32h73x.s @@ -0,0 +1,346 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32h735.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32H73x +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG1_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_STAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA_STR0_IRQHandler + .long DMA_STR1_IRQHandler + .long DMA_STR2_IRQHandler + .long DMA_STR3_IRQHandler + .long DMA_STR4_IRQHandler + .long DMA_STR5_IRQHandler + .long DMA_STR6_IRQHandler + .long ADC1_2_IRQHandler + .long FDCAN1_IT0_IRQHandler + .long FDCAN2_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long FDCAN2_IT1_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long 0 + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_STR7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_STR0_IRQHandler + .long DMA2_STR1_IRQHandler + .long DMA2_STR2_IRQHandler + .long DMA2_STR3_IRQHandler + .long DMA2_STR4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long FDCAN_CAL_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA2_STR5_IRQHandler + .long DMA2_STR6_IRQHandler + .long DMA2_STR7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long 0 + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long 0 + .long OCTOSPI1_IRQHandler + .long LPTIM1_IRQHandler + .long CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIF_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMAMUX1_OV_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long 0 + .long SWPMI1_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long MDIOS_WKUP_IRQHandler + .long MDIOS_IRQHandler + .long 0 + .long MDMA_IRQHandler + .long 0 + .long SDMMC2_IRQHandler + .long HSEM0_IRQHandler + .long 0 + .long ADC3_IRQHandler + .long DMAMUX2_OVR_IRQHandler + .long BDMA_CH0_IRQHandler + .long BDMA_CH1_IRQHandler + .long BDMA_CH2_IRQHandler + .long BDMA_CH3_IRQHandler + .long BDMA_CH4_IRQHandler + .long BDMA_CH5_IRQHandler + .long BDMA_CH6_IRQHandler + .long BDMA_CH7_IRQHandler + .long COMP_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long LPTIM4_IRQHandler + .long LPTIM5_IRQHandler + .long LPUART_IRQHandler + .long 0 + .long CRS_IRQHandler + .long 0 + .long SAI4_IRQHandler + .long 0 + .long 0 + .long WKUP_IRQHandler + .long OCTOSPI2_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG1_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_STAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA_STR0_IRQHandler + IRQ DMA1_STR0_IRQHandler + IRQ DMA_STR1_IRQHandler + IRQ DMA1_STR1_IRQHandler + IRQ DMA_STR2_IRQHandler + IRQ DMA1_STR2_IRQHandler + IRQ DMA_STR3_IRQHandler + IRQ DMA1_STR3_IRQHandler + IRQ DMA_STR4_IRQHandler + IRQ DMA1_STR4_IRQHandler + IRQ DMA_STR5_IRQHandler + IRQ DMA1_STR5_IRQHandler + IRQ DMA_STR6_IRQHandler + IRQ DMA1_STR6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN2_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ FDCAN2_IT1_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_STR7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_STR0_IRQHandler + IRQ DMA2_STR1_IRQHandler + IRQ DMA2_STR2_IRQHandler + IRQ DMA2_STR3_IRQHandler + IRQ DMA2_STR4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ FDCAN_CAL_IRQHandler + IRQ DMA2_STR5_IRQHandler + IRQ DMA2_STR6_IRQHandler + IRQ DMA2_STR7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ OCTOSPI1_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIF_IRQHandler + IRQ DMAMUX1_OV_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ MDIOS_WKUP_IRQHandler + IRQ MDIOS_IRQHandler + IRQ MDMA_IRQHandler + IRQ SDMMC2_IRQHandler + IRQ HSEM0_IRQHandler + IRQ ADC3_IRQHandler + IRQ DMAMUX2_OVR_IRQHandler + IRQ BDMA_CH0_IRQHandler + IRQ BDMA_CH1_IRQHandler + IRQ BDMA_CH2_IRQHandler + IRQ BDMA_CH3_IRQHandler + IRQ BDMA_CH4_IRQHandler + IRQ BDMA_CH5_IRQHandler + IRQ BDMA_CH6_IRQHandler + IRQ BDMA_CH7_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ LPTIM4_IRQHandler + IRQ LPTIM5_IRQHandler + IRQ LPUART_IRQHandler + IRQ CRS_IRQHandler + IRQ SAI4_IRQHandler + IRQ WKUP_IRQHandler + IRQ OCTOSPI2_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32h743.s b/targets/device/stm32/stm32h743.s new file mode 100644 index 00000000..0745a90f --- /dev/null +++ b/targets/device/stm32/stm32h743.s @@ -0,0 +1,358 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32h743v.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32H743 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG1_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_STAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA_STR0_IRQHandler + .long DMA_STR1_IRQHandler + .long DMA1_STR2_IRQHandler + .long DMA1_STR3_IRQHandler + .long DMA1_STR4_IRQHandler + .long DMA1_STR5_IRQHandler + .long DMA1_STR6_IRQHandler + .long ADC1_2_IRQHandler + .long FDCAN1_IT0_IRQHandler + .long FDCAN2_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long FDCAN2_IT1_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long 0 + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_STR7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_STR0_IRQHandler + .long DMA2_STR1_IRQHandler + .long DMA2_STR2_IRQHandler + .long DMA2_STR3_IRQHandler + .long DMA2_STR4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long FDCAN_CAL_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA2_STR5_IRQHandler + .long DMA2_STR6_IRQHandler + .long DMA2_STR7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long 0 + .long 0 + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QUADSPI_IRQHandler + .long LPTIM1_IRQHandler + .long CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIF_IRQHandler + .long OTG_FS_EP1_OUT_IRQHandler + .long OTG_FS_EP1_IN_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long OTG_FS_IRQHandler + .long DMAMUX1_OV_IRQHandler + .long HRTIM1_MST_IRQHandler + .long HRTIM1_TIMA_IRQHandler + .long HRTIM_TIMB_IRQHandler + .long HRTIM1_TIMC_IRQHandler + .long HRTIM1_TIMD_IRQHandler + .long HRTIM_TIME_IRQHandler + .long HRTIM1_FLT_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SAI3_IRQHandler + .long SWPMI1_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long MDIOS_WKUP_IRQHandler + .long MDIOS_IRQHandler + .long JPEG_IRQHandler + .long MDMA_IRQHandler + .long 0 + .long SDMMC_IRQHandler + .long HSEM0_IRQHandler + .long 0 + .long ADC3_IRQHandler + .long DMAMUX2_OVR_IRQHandler + .long BDMA_CH1_IRQHandler + .long BDMA_CH2_IRQHandler + .long BDMA_CH3_IRQHandler + .long BDMA_CH4_IRQHandler + .long BDMA_CH5_IRQHandler + .long BDMA_CH6_IRQHandler + .long BDMA_CH7_IRQHandler + .long BDMA_CH8_IRQHandler + .long COMP_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long LPTIM4_IRQHandler + .long LPTIM5_IRQHandler + .long LPUART_IRQHandler + .long WWDG1_RST_IRQHandler + .long CRS_IRQHandler + .long RAMECC_IRQHandler + .long SAI4_IRQHandler + .long 0 + .long 0 + .long WKUP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG1_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_STAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA_STR0_IRQHandler + IRQ DMA1_STR0_IRQHandler + IRQ DMA_STR1_IRQHandler + IRQ DMA1_STR1_IRQHandler + IRQ DMA1_STR2_IRQHandler + IRQ DMA1_STR3_IRQHandler + IRQ DMA1_STR4_IRQHandler + IRQ DMA1_STR5_IRQHandler + IRQ DMA1_STR6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN2_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ FDCAN2_IT1_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_STR7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_STR0_IRQHandler + IRQ DMA2_STR1_IRQHandler + IRQ DMA2_STR2_IRQHandler + IRQ DMA2_STR3_IRQHandler + IRQ DMA2_STR4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ FDCAN_CAL_IRQHandler + IRQ DMA2_STR5_IRQHandler + IRQ DMA2_STR6_IRQHandler + IRQ DMA2_STR7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIF_IRQHandler + IRQ OTG_FS_EP1_OUT_IRQHandler + IRQ OTG_FS_EP1_IN_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMAMUX1_OV_IRQHandler + IRQ HRTIM1_MST_IRQHandler + IRQ HRTIM1_TIMA_IRQHandler + IRQ HRTIM_TIMB_IRQHandler + IRQ HRTIM1_TIMC_IRQHandler + IRQ HRTIM1_TIMD_IRQHandler + IRQ HRTIM_TIME_IRQHandler + IRQ HRTIM1_FLT_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SAI3_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ MDIOS_WKUP_IRQHandler + IRQ MDIOS_IRQHandler + IRQ JPEG_IRQHandler + IRQ MDMA_IRQHandler + IRQ SDMMC_IRQHandler + IRQ HSEM0_IRQHandler + IRQ ADC3_IRQHandler + IRQ DMAMUX2_OVR_IRQHandler + IRQ BDMA_CH1_IRQHandler + IRQ BDMA_CH2_IRQHandler + IRQ BDMA_CH3_IRQHandler + IRQ BDMA_CH4_IRQHandler + IRQ BDMA_CH5_IRQHandler + IRQ BDMA_CH6_IRQHandler + IRQ BDMA_CH7_IRQHandler + IRQ BDMA_CH8_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ LPTIM4_IRQHandler + IRQ LPTIM5_IRQHandler + IRQ LPUART_IRQHandler + IRQ WWDG1_RST_IRQHandler + IRQ CRS_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SAI4_IRQHandler + IRQ WKUP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32h753.s b/targets/device/stm32/stm32h753.s new file mode 100644 index 00000000..d1162269 --- /dev/null +++ b/targets/device/stm32/stm32h753.s @@ -0,0 +1,360 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32h753v.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32H753 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG1_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_STAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA_STR0_IRQHandler + .long DMA_STR1_IRQHandler + .long DMA1_STR2_IRQHandler + .long DMA1_STR3_IRQHandler + .long DMA1_STR4_IRQHandler + .long DMA1_STR5_IRQHandler + .long DMA1_STR6_IRQHandler + .long ADC1_2_IRQHandler + .long FDCAN1_IT0_IRQHandler + .long FDCAN2_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long FDCAN2_IT1_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long 0 + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_STR7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_STR0_IRQHandler + .long DMA2_STR1_IRQHandler + .long DMA2_STR2_IRQHandler + .long DMA2_STR3_IRQHandler + .long DMA2_STR4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long FDCAN_CAL_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA2_STR5_IRQHandler + .long DMA2_STR6_IRQHandler + .long DMA2_STR7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QUADSPI_IRQHandler + .long LPTIM1_IRQHandler + .long CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIF_IRQHandler + .long OTG_FS_EP1_OUT_IRQHandler + .long OTG_FS_EP1_IN_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long OTG_FS_IRQHandler + .long DMAMUX1_OV_IRQHandler + .long HRTIM1_MST_IRQHandler + .long HRTIM1_TIMA_IRQHandler + .long HRTIM_TIMB_IRQHandler + .long HRTIM1_TIMC_IRQHandler + .long HRTIM1_TIMD_IRQHandler + .long HRTIM_TIME_IRQHandler + .long HRTIM1_FLT_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SAI3_IRQHandler + .long SWPMI1_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long MDIOS_WKUP_IRQHandler + .long MDIOS_IRQHandler + .long JPEG_IRQHandler + .long MDMA_IRQHandler + .long 0 + .long SDMMC_IRQHandler + .long HSEM0_IRQHandler + .long 0 + .long ADC3_IRQHandler + .long DMAMUX2_OVR_IRQHandler + .long BDMA_CH1_IRQHandler + .long BDMA_CH2_IRQHandler + .long BDMA_CH3_IRQHandler + .long BDMA_CH4_IRQHandler + .long BDMA_CH5_IRQHandler + .long BDMA_CH6_IRQHandler + .long BDMA_CH7_IRQHandler + .long BDMA_CH8_IRQHandler + .long COMP_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long LPTIM4_IRQHandler + .long LPTIM5_IRQHandler + .long LPUART_IRQHandler + .long WWDG1_RST_IRQHandler + .long CRS_IRQHandler + .long RAMECC_IRQHandler + .long SAI4_IRQHandler + .long 0 + .long 0 + .long WKUP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG1_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_STAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA_STR0_IRQHandler + IRQ DMA1_STR0_IRQHandler + IRQ DMA_STR1_IRQHandler + IRQ DMA1_STR1_IRQHandler + IRQ DMA1_STR2_IRQHandler + IRQ DMA1_STR3_IRQHandler + IRQ DMA1_STR4_IRQHandler + IRQ DMA1_STR5_IRQHandler + IRQ DMA1_STR6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN2_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ FDCAN2_IT1_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_STR7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_STR0_IRQHandler + IRQ DMA2_STR1_IRQHandler + IRQ DMA2_STR2_IRQHandler + IRQ DMA2_STR3_IRQHandler + IRQ DMA2_STR4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ FDCAN_CAL_IRQHandler + IRQ DMA2_STR5_IRQHandler + IRQ DMA2_STR6_IRQHandler + IRQ DMA2_STR7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIF_IRQHandler + IRQ OTG_FS_EP1_OUT_IRQHandler + IRQ OTG_FS_EP1_IN_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMAMUX1_OV_IRQHandler + IRQ HRTIM1_MST_IRQHandler + IRQ HRTIM1_TIMA_IRQHandler + IRQ HRTIM_TIMB_IRQHandler + IRQ HRTIM1_TIMC_IRQHandler + IRQ HRTIM1_TIMD_IRQHandler + IRQ HRTIM_TIME_IRQHandler + IRQ HRTIM1_FLT_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SAI3_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ MDIOS_WKUP_IRQHandler + IRQ MDIOS_IRQHandler + IRQ JPEG_IRQHandler + IRQ MDMA_IRQHandler + IRQ SDMMC_IRQHandler + IRQ HSEM0_IRQHandler + IRQ ADC3_IRQHandler + IRQ DMAMUX2_OVR_IRQHandler + IRQ BDMA_CH1_IRQHandler + IRQ BDMA_CH2_IRQHandler + IRQ BDMA_CH3_IRQHandler + IRQ BDMA_CH4_IRQHandler + IRQ BDMA_CH5_IRQHandler + IRQ BDMA_CH6_IRQHandler + IRQ BDMA_CH7_IRQHandler + IRQ BDMA_CH8_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ LPTIM4_IRQHandler + IRQ LPTIM5_IRQHandler + IRQ LPUART_IRQHandler + IRQ WWDG1_RST_IRQHandler + IRQ CRS_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SAI4_IRQHandler + IRQ WKUP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32h757_cm4.s b/targets/device/stm32/stm32h757_cm4.s new file mode 100644 index 00000000..482d210d --- /dev/null +++ b/targets/device/stm32/stm32h757_cm4.s @@ -0,0 +1,367 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32h747cm4.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32H757_CM4 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG2_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_STAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long 0 + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA_STR0_IRQHandler + .long DMA_STR1_IRQHandler + .long DMA_STR2_IRQHandler + .long DMA_STR3_IRQHandler + .long DMA_STR4_IRQHandler + .long DMA_STR5_IRQHandler + .long DMA_STR6_IRQHandler + .long ADC1_2_IRQHandler + .long FDCAN1_IT0_IRQHandler + .long FDCAN2_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long FDCAN2_IT1_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long 0 + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_STR7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_STR0_IRQHandler + .long DMA2_STR1_IRQHandler + .long DMA2_STR2_IRQHandler + .long DMA2_STR3_IRQHandler + .long DMA2_STR4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long FDCAN_CAL_IRQHandler + .long cm7_sev_it_IRQHandler + .long 0 + .long 0 + .long 0 + .long DMA2_STR5_IRQHandler + .long DMA2_STR6_IRQHandler + .long DMA2_STR7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QUADSPI_IRQHandler + .long LPTIM1_IRQHandler + .long CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIF_IRQHandler + .long OTG_FS_EP1_OUT_IRQHandler + .long OTG_FS_EP1_IN_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long OTG_FS_IRQHandler + .long DMAMUX1_OV_IRQHandler + .long HRTIM1_MST_IRQHandler + .long HRTIM1_TIMA_IRQHandler + .long HRTIM_TIMB_IRQHandler + .long HRTIM1_TIMC_IRQHandler + .long HRTIM1_TIMD_IRQHandler + .long HRTIM_TIME_IRQHandler + .long HRTIM1_FLT_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SAI3_IRQHandler + .long SWPMI1_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long MDIOS_WKUP_IRQHandler + .long MDIOS_IRQHandler + .long JPEG_IRQHandler + .long MDMA_IRQHandler + .long DSI_IRQHandler + .long SDMMC_IRQHandler + .long HSEM0_IRQHandler + .long 0 + .long ADC3_IRQHandler + .long DMAMUX2_OVR_IRQHandler + .long BDMA_CH1_IRQHandler + .long BDMA_CH2_IRQHandler + .long BDMA_CH3_IRQHandler + .long BDMA_CH4_IRQHandler + .long BDMA_CH5_IRQHandler + .long BDMA_CH6_IRQHandler + .long BDMA_CH7_IRQHandler + .long BDMA_CH8_IRQHandler + .long COMP_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long LPTIM4_IRQHandler + .long LPTIM5_IRQHandler + .long LPUART_IRQHandler + .long WWDG1_RST_IRQHandler + .long CRS_IRQHandler + .long RAMECC_IRQHandler + .long SAI4_IRQHandler + .long 0 + .long HOLD_CORE_IRQHandler + .long WKUP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG2_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_STAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA_STR0_IRQHandler + IRQ DMA1_STR0_IRQHandler + IRQ DMA_STR1_IRQHandler + IRQ DMA1_STR1_IRQHandler + IRQ DMA_STR2_IRQHandler + IRQ DMA1_STR2_IRQHandler + IRQ DMA_STR3_IRQHandler + IRQ DMA1_STR3_IRQHandler + IRQ DMA_STR4_IRQHandler + IRQ DMA1_STR4_IRQHandler + IRQ DMA_STR5_IRQHandler + IRQ DMA1_STR5_IRQHandler + IRQ DMA_STR6_IRQHandler + IRQ DMA1_STR6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN2_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ FDCAN2_IT1_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_STR7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_STR0_IRQHandler + IRQ DMA2_STR1_IRQHandler + IRQ DMA2_STR2_IRQHandler + IRQ DMA2_STR3_IRQHandler + IRQ DMA2_STR4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ FDCAN_CAL_IRQHandler + IRQ cm7_sev_it_IRQHandler + IRQ DMA2_STR5_IRQHandler + IRQ DMA2_STR6_IRQHandler + IRQ DMA2_STR7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIF_IRQHandler + IRQ OTG_FS_EP1_OUT_IRQHandler + IRQ OTG_FS_EP1_IN_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMAMUX1_OV_IRQHandler + IRQ HRTIM1_MST_IRQHandler + IRQ HRTIM1_TIMA_IRQHandler + IRQ HRTIM_TIMB_IRQHandler + IRQ HRTIM1_TIMC_IRQHandler + IRQ HRTIM1_TIMD_IRQHandler + IRQ HRTIM_TIME_IRQHandler + IRQ HRTIM1_FLT_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SAI3_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ MDIOS_WKUP_IRQHandler + IRQ MDIOS_IRQHandler + IRQ JPEG_IRQHandler + IRQ MDMA_IRQHandler + IRQ DSI_IRQHandler + IRQ SDMMC_IRQHandler + IRQ HSEM0_IRQHandler + IRQ ADC3_IRQHandler + IRQ DMAMUX2_OVR_IRQHandler + IRQ BDMA_CH1_IRQHandler + IRQ BDMA_CH2_IRQHandler + IRQ BDMA_CH3_IRQHandler + IRQ BDMA_CH4_IRQHandler + IRQ BDMA_CH5_IRQHandler + IRQ BDMA_CH6_IRQHandler + IRQ BDMA_CH7_IRQHandler + IRQ BDMA_CH8_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ LPTIM4_IRQHandler + IRQ LPTIM5_IRQHandler + IRQ LPUART_IRQHandler + IRQ WWDG1_RST_IRQHandler + IRQ CRS_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SAI4_IRQHandler + IRQ HOLD_CORE_IRQHandler + IRQ WKUP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32h757_cm7.s b/targets/device/stm32/stm32h757_cm7.s new file mode 100644 index 00000000..d73df97f --- /dev/null +++ b/targets/device/stm32/stm32h757_cm7.s @@ -0,0 +1,367 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32h747cm7.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32H757_CM7 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG1_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_STAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long 0 + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA_STR0_IRQHandler + .long DMA_STR1_IRQHandler + .long DMA_STR2_IRQHandler + .long DMA_STR3_IRQHandler + .long DMA_STR4_IRQHandler + .long DMA_STR5_IRQHandler + .long DMA_STR6_IRQHandler + .long ADC1_2_IRQHandler + .long FDCAN1_IT0_IRQHandler + .long FDCAN2_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long FDCAN2_IT1_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long 0 + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_STR7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_STR0_IRQHandler + .long DMA2_STR1_IRQHandler + .long DMA2_STR2_IRQHandler + .long DMA2_STR3_IRQHandler + .long DMA2_STR4_IRQHandler + .long ETH_IRQHandler + .long ETH_WKUP_IRQHandler + .long FDCAN_CAL_IRQHandler + .long 0 + .long cm4_sev_it_IRQHandler + .long 0 + .long 0 + .long DMA2_STR5_IRQHandler + .long DMA2_STR6_IRQHandler + .long DMA2_STR7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QUADSPI_IRQHandler + .long LPTIM1_IRQHandler + .long CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIF_IRQHandler + .long OTG_FS_EP1_OUT_IRQHandler + .long OTG_FS_EP1_IN_IRQHandler + .long OTG_FS_WKUP_IRQHandler + .long OTG_FS_IRQHandler + .long DMAMUX1_OV_IRQHandler + .long HRTIM1_MST_IRQHandler + .long HRTIM1_TIMA_IRQHandler + .long HRTIM_TIMB_IRQHandler + .long HRTIM1_TIMC_IRQHandler + .long HRTIM1_TIMD_IRQHandler + .long HRTIM_TIME_IRQHandler + .long HRTIM1_FLT_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SAI3_IRQHandler + .long SWPMI1_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long MDIOS_WKUP_IRQHandler + .long MDIOS_IRQHandler + .long JPEG_IRQHandler + .long MDMA_IRQHandler + .long DSI_IRQHandler + .long SDMMC_IRQHandler + .long HSEM0_IRQHandler + .long 0 + .long ADC3_IRQHandler + .long DMAMUX2_OVR_IRQHandler + .long BDMA_CH1_IRQHandler + .long BDMA_CH2_IRQHandler + .long BDMA_CH3_IRQHandler + .long BDMA_CH4_IRQHandler + .long BDMA_CH5_IRQHandler + .long BDMA_CH6_IRQHandler + .long BDMA_CH7_IRQHandler + .long BDMA_CH8_IRQHandler + .long COMP_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long LPTIM4_IRQHandler + .long LPTIM5_IRQHandler + .long LPUART_IRQHandler + .long WWDG2_RST_IRQHandler + .long CRS_IRQHandler + .long RAMECC_IRQHandler + .long SAI4_IRQHandler + .long 0 + .long HOLD_CORE_IRQHandler + .long WKUP_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG1_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_STAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA_STR0_IRQHandler + IRQ DMA1_STR0_IRQHandler + IRQ DMA_STR1_IRQHandler + IRQ DMA1_STR1_IRQHandler + IRQ DMA_STR2_IRQHandler + IRQ DMA1_STR2_IRQHandler + IRQ DMA_STR3_IRQHandler + IRQ DMA1_STR3_IRQHandler + IRQ DMA_STR4_IRQHandler + IRQ DMA1_STR4_IRQHandler + IRQ DMA_STR5_IRQHandler + IRQ DMA1_STR5_IRQHandler + IRQ DMA_STR6_IRQHandler + IRQ DMA1_STR6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN2_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ FDCAN2_IT1_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_STR7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_STR0_IRQHandler + IRQ DMA2_STR1_IRQHandler + IRQ DMA2_STR2_IRQHandler + IRQ DMA2_STR3_IRQHandler + IRQ DMA2_STR4_IRQHandler + IRQ ETH_IRQHandler + IRQ ETH_WKUP_IRQHandler + IRQ FDCAN_CAL_IRQHandler + IRQ cm4_sev_it_IRQHandler + IRQ DMA2_STR5_IRQHandler + IRQ DMA2_STR6_IRQHandler + IRQ DMA2_STR7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIF_IRQHandler + IRQ OTG_FS_EP1_OUT_IRQHandler + IRQ OTG_FS_EP1_IN_IRQHandler + IRQ OTG_FS_WKUP_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMAMUX1_OV_IRQHandler + IRQ HRTIM1_MST_IRQHandler + IRQ HRTIM1_TIMA_IRQHandler + IRQ HRTIM_TIMB_IRQHandler + IRQ HRTIM1_TIMC_IRQHandler + IRQ HRTIM1_TIMD_IRQHandler + IRQ HRTIM_TIME_IRQHandler + IRQ HRTIM1_FLT_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SAI3_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ MDIOS_WKUP_IRQHandler + IRQ MDIOS_IRQHandler + IRQ JPEG_IRQHandler + IRQ MDMA_IRQHandler + IRQ DSI_IRQHandler + IRQ SDMMC_IRQHandler + IRQ HSEM0_IRQHandler + IRQ ADC3_IRQHandler + IRQ DMAMUX2_OVR_IRQHandler + IRQ BDMA_CH1_IRQHandler + IRQ BDMA_CH2_IRQHandler + IRQ BDMA_CH3_IRQHandler + IRQ BDMA_CH4_IRQHandler + IRQ BDMA_CH5_IRQHandler + IRQ BDMA_CH6_IRQHandler + IRQ BDMA_CH7_IRQHandler + IRQ BDMA_CH8_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ LPTIM4_IRQHandler + IRQ LPTIM5_IRQHandler + IRQ LPUART_IRQHandler + IRQ WWDG2_RST_IRQHandler + IRQ CRS_IRQHandler + IRQ RAMECC_IRQHandler + IRQ SAI4_IRQHandler + IRQ HOLD_CORE_IRQHandler + IRQ WKUP_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32h7b3x.s b/targets/device/stm32/stm32h7b3x.s new file mode 100644 index 00000000..81ee3ed0 --- /dev/null +++ b/targets/device/stm32/stm32h7b3x.s @@ -0,0 +1,359 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32h7b3.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32H7B3x +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_STAMP_CSS_LSE_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA_STR0_IRQHandler + .long DMA_STR1_IRQHandler + .long DMA_STR2_IRQHandler + .long DMA_STR3_IRQHandler + .long DMA_STR4_IRQHandler + .long DMA_STR5_IRQHandler + .long DMA_STR6_IRQHandler + .long ADC1_2_IRQHandler + .long FDCAN1_IT0_IRQHandler + .long FDCAN2_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long FDCAN2_IT1_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long 0 + .long TIM8_BRK_TIM12_IRQHandler + .long TIM8_UP_TIM13_IRQHandler + .long TIM8_TRG_COM_TIM14_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_STR7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_STR0_IRQHandler + .long DMA2_STR1_IRQHandler + .long DMA2_STR2_IRQHandler + .long DMA2_STR3_IRQHandler + .long DMA2_STR4_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA2_STR5_IRQHandler + .long DMA2_STR6_IRQHandler + .long DMA2_STR7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long OTG_HS_EP1_OUT_IRQHandler + .long OTG_HS_EP1_IN_IRQHandler + .long OTG_HS_WKUP_IRQHandler + .long OTG_HS_IRQHandler + .long DCMI_PSSI_IRQHandler + .long CRYP_IRQHandler + .long HASH_RNG_IRQHandler + .long FPU_IRQHandler + .long UART7_IRQHandler + .long UART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long DMA2D_IRQHandler + .long SAI2_IRQHandler + .long QUADSPI_IRQHandler + .long LPTIM1_IRQHandler + .long CEC_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long SPDIFRX_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMAMUX1_OV_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long 0 + .long SWPMI1_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long MDIOS_WKUP_IRQHandler + .long MDIOS_IRQHandler + .long JPEG_IRQHandler + .long MDMA_IRQHandler + .long 0 + .long SDMMC_IRQHandler + .long HSEM0_IRQHandler + .long 0 + .long DAC2_IRQHandler + .long DMAMUX2_OVR_IRQHandler + .long BDMA_CH1_IRQHandler + .long BDMA_CH2_IRQHandler + .long BDMA_CH3_IRQHandler + .long BDMA_CH4_IRQHandler + .long BDMA_CH5_IRQHandler + .long BDMA_CH6_IRQHandler + .long BDMA_CH7_IRQHandler + .long BDMA_CH8_IRQHandler + .long COMP_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long UART9_IRQHandler + .long USART10_IRQHandler + .long LPUART_IRQHandler + .long WWDG1_RST_IRQHandler + .long CRS_IRQHandler + .long RAMECC_IRQHandler + .long 0 + .long 0 + .long 0 + .long WKUP_IRQHandler + .long OCTOSPI2_IRQHandler + .long OTFDEC1_IRQHandler + .long OTFDEC2_IRQHandler + .long 0 + .long BDMA1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_STAMP_CSS_LSE_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA_STR0_IRQHandler + IRQ DMA1_STR0_IRQHandler + IRQ DMA_STR1_IRQHandler + IRQ DMA1_STR1_IRQHandler + IRQ DMA_STR2_IRQHandler + IRQ DMA1_STR2_IRQHandler + IRQ DMA_STR3_IRQHandler + IRQ DMA1_STR3_IRQHandler + IRQ DMA_STR4_IRQHandler + IRQ DMA1_STR4_IRQHandler + IRQ DMA_STR5_IRQHandler + IRQ DMA1_STR5_IRQHandler + IRQ DMA_STR6_IRQHandler + IRQ DMA1_STR6_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN2_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ FDCAN2_IT1_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ TIM8_BRK_TIM12_IRQHandler + IRQ TIM8_UP_TIM13_IRQHandler + IRQ TIM8_TRG_COM_TIM14_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_STR7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_STR0_IRQHandler + IRQ DMA2_STR1_IRQHandler + IRQ DMA2_STR2_IRQHandler + IRQ DMA2_STR3_IRQHandler + IRQ DMA2_STR4_IRQHandler + IRQ DMA2_STR5_IRQHandler + IRQ DMA2_STR6_IRQHandler + IRQ DMA2_STR7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ OTG_HS_EP1_OUT_IRQHandler + IRQ OTG_HS_EP1_IN_IRQHandler + IRQ OTG_HS_WKUP_IRQHandler + IRQ OTG_HS_IRQHandler + IRQ DCMI_PSSI_IRQHandler + IRQ CRYP_IRQHandler + IRQ HASH_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ UART7_IRQHandler + IRQ UART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ DMA2D_IRQHandler + IRQ SAI2_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ OCTOSPI1_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ SPDIFRX_IRQHandler + IRQ DMAMUX1_OV_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ MDIOS_WKUP_IRQHandler + IRQ MDIOS_IRQHandler + IRQ JPEG_IRQHandler + IRQ MDMA_IRQHandler + IRQ SDMMC_IRQHandler + IRQ HSEM0_IRQHandler + IRQ DAC2_IRQHandler + IRQ DMAMUX2_OVR_IRQHandler + IRQ BDMA_CH1_IRQHandler + IRQ BDMA_CH2_IRQHandler + IRQ BDMA_CH3_IRQHandler + IRQ BDMA_CH4_IRQHandler + IRQ BDMA_CH5_IRQHandler + IRQ BDMA_CH6_IRQHandler + IRQ BDMA_CH7_IRQHandler + IRQ BDMA_CH8_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ UART9_IRQHandler + IRQ USART10_IRQHandler + IRQ LPUART_IRQHandler + IRQ WWDG1_RST_IRQHandler + IRQ CRS_IRQHandler + IRQ RAMECC_IRQHandler + IRQ WKUP_IRQHandler + IRQ OCTOSPI2_IRQHandler + IRQ OTFDEC1_IRQHandler + IRQ OTFDEC2_IRQHandler + IRQ BDMA1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l0x0.s b/targets/device/stm32/stm32l0x0.s new file mode 100644 index 00000000..791d99e3 --- /dev/null +++ b/targets/device/stm32/stm32l0x0.s @@ -0,0 +1,116 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l0x0.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L0x0 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long 0 + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long 0 + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_3_IRQHandler + .long DMA1_Channel4_7_IRQHandler + .long ADC_IRQHandler + .long LPTIM1_IRQHandler + .long 0 + .long TIM2_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long TIM21_IRQHandler + .long 0 + .long TIM22_IRQHandler + .long I2C1_IRQHandler + .long 0 + .long SPI1_IRQHandler + .long 0 + .long 0 + .long USART2_IRQHandler + .long LPUART1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_3_IRQHandler + IRQ DMA1_Channel4_7_IRQHandler + IRQ ADC_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM21_IRQHandler + IRQ TIM22_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART2_IRQHandler + IRQ LPUART1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l0x1.s b/targets/device/stm32/stm32l0x1.s new file mode 100644 index 00000000..d72f2c6f --- /dev/null +++ b/targets/device/stm32/stm32l0x1.s @@ -0,0 +1,125 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l0x1.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L0x1 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long 0 + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_3_IRQHandler + .long DMA1_Channel4_7_IRQHandler + .long ADC_COMP_IRQHandler + .long LPTIM1_IRQHandler + .long USART4_USART5_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long 0 + .long TIM21_IRQHandler + .long I2C3_IRQHandler + .long TIM22_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long AES_RNG_LPUART1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_3_IRQHandler + IRQ DMA1_Channel4_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ USART4_USART5_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM21_IRQHandler + IRQ I2C3_IRQHandler + IRQ TIM22_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ AES_RNG_LPUART1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l0x2.s b/targets/device/stm32/stm32l0x2.s new file mode 100644 index 00000000..8048e2d4 --- /dev/null +++ b/targets/device/stm32/stm32l0x2.s @@ -0,0 +1,128 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l0x2.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L0x2 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_IRQHandler + .long 0 + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long TSC_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_3_IRQHandler + .long DMA1_Channel4_7_IRQHandler + .long ADC_COMP_IRQHandler + .long LPTIM1_IRQHandler + .long USART4_USART5_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long 0 + .long TIM21_IRQHandler + .long I2C3_IRQHandler + .long TIM22_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long AES_RNG_LPUART1_IRQHandler + .long 0 + .long USB_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ TSC_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_3_IRQHandler + IRQ DMA1_Channel4_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ USART4_USART5_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM21_IRQHandler + IRQ I2C3_IRQHandler + IRQ TIM22_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ AES_RNG_LPUART1_IRQHandler + IRQ USB_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l0x3.s b/targets/device/stm32/stm32l0x3.s new file mode 100644 index 00000000..70908014 --- /dev/null +++ b/targets/device/stm32/stm32l0x3.s @@ -0,0 +1,129 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l0x3.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L0x3 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_IRQHandler + .long 0 + .long RCC_IRQHandler + .long EXTI0_1_IRQHandler + .long EXTI2_3_IRQHandler + .long EXTI4_15_IRQHandler + .long TSC_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_3_IRQHandler + .long DMA1_Channel4_7_IRQHandler + .long ADC_COMP_IRQHandler + .long LPTIM1_IRQHandler + .long USART4_USART5_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long 0 + .long TIM21_IRQHandler + .long I2C3_IRQHandler + .long TIM22_IRQHandler + .long I2C1_IRQHandler + .long I2C2_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long AES_RNG_LPUART1_IRQHandler + .long LCD_IRQHandler + .long USB_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ TSC_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_3_IRQHandler + IRQ DMA1_Channel4_7_IRQHandler + IRQ ADC_COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ USART4_USART5_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM21_IRQHandler + IRQ I2C3_IRQHandler + IRQ TIM22_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ AES_RNG_LPUART1_IRQHandler + IRQ LCD_IRQHandler + IRQ USB_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l100.s b/targets/device/stm32/stm32l100.s new file mode 100644 index 00000000..7fb2517a --- /dev/null +++ b/targets/device/stm32/stm32l100.s @@ -0,0 +1,181 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l100.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L100 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMPER_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC1_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long DAC_IRQHandler + .long COMP_CA_IRQHandler + .long EXTI9_5_IRQHandler + .long LCD_IRQHandler + .long TIM9_IRQHandler + .long TIM10_IRQHandler + .long TIM11_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long USB_FS_WKUP_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long USART4_IRQHandler + .long USART5_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long AES_IRQHandler + .long COMP_ACQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ DAC_IRQHandler + IRQ COMP_CA_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ LCD_IRQHandler + IRQ TIM9_IRQHandler + IRQ TIM10_IRQHandler + IRQ TIM11_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ USB_FS_WKUP_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ USART4_IRQHandler + IRQ USART5_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ AES_IRQHandler + IRQ COMP_ACQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l151.s b/targets/device/stm32/stm32l151.s new file mode 100644 index 00000000..3debb359 --- /dev/null +++ b/targets/device/stm32/stm32l151.s @@ -0,0 +1,181 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l151.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L151 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMPER_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC1_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long DAC_IRQHandler + .long COMP_CA_IRQHandler + .long EXTI9_5_IRQHandler + .long LCD_IRQHandler + .long TIM9_IRQHandler + .long TIM10_IRQHandler + .long TIM11_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long USB_FS_WKUP_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long AES_IRQHandler + .long COMP_ACQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ DAC_IRQHandler + IRQ COMP_CA_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ LCD_IRQHandler + IRQ TIM9_IRQHandler + IRQ TIM10_IRQHandler + IRQ TIM11_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ USB_FS_WKUP_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ AES_IRQHandler + IRQ COMP_ACQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l162.s b/targets/device/stm32/stm32l162.s new file mode 100644 index 00000000..be455ecc --- /dev/null +++ b/targets/device/stm32/stm32l162.s @@ -0,0 +1,181 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l162.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L162 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMPER_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC1_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long DAC_IRQHandler + .long COMP_CA_IRQHandler + .long EXTI9_5_IRQHandler + .long LCD_IRQHandler + .long TIM9_IRQHandler + .long TIM10_IRQHandler + .long TIM11_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_Alarm_IRQHandler + .long USB_FS_WKUP_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long SDIO_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long AES_IRQHandler + .long COMP_ACQ_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ DAC_IRQHandler + IRQ COMP_CA_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ LCD_IRQHandler + IRQ TIM9_IRQHandler + IRQ TIM10_IRQHandler + IRQ TIM11_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_Alarm_IRQHandler + IRQ USB_FS_WKUP_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ SDIO_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ AES_IRQHandler + IRQ COMP_ACQ_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l4r9.s b/targets/device/stm32/stm32l4r9.s new file mode 100644 index 00000000..cece4738 --- /dev/null +++ b/targets/device/stm32/stm32l4r9.s @@ -0,0 +1,253 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l4r9.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L4R9 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_TIM17_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long COMP_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long LPUART1_IRQHandler + .long OCTOSPI1_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long OCTOSPI2_IRQHandler + .long TSC_IRQHandler + .long DSIHOST_IRQHandler + .long AES_IRQHandler + .long RNG_HASH_IRQHandler + .long FPU_IRQHandler + .long CRS_IRQHandler + .long I2C4_ER_IRQHandler + .long I2C4_EV_IRQHandler + .long DCMI_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long DMA2D_IRQHandler + .long LCD_TFT_IRQHandler + .long LCD_TFT_ER_IRQHandler + .long GFXMMU_IRQHandler + .long DMAMUX_OVR_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_TIM17_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ LPUART1_IRQHandler + IRQ OCTOSPI1_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ OCTOSPI2_IRQHandler + IRQ TSC_IRQHandler + IRQ DSIHOST_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_HASH_IRQHandler + IRQ FPU_IRQHandler + IRQ CRS_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ DCMI_IRQHandler + IRQ DMA2D_IRQHandler + IRQ LCD_TFT_IRQHandler + IRQ LCD_TFT_ER_IRQHandler + IRQ GFXMMU_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l4x1.s b/targets/device/stm32/stm32l4x1.s new file mode 100644 index 00000000..6d2b44a3 --- /dev/null +++ b/targets/device/stm32/stm32l4x1.s @@ -0,0 +1,227 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l4x1.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L4x1 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long 0 + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SDMMC1_IRQHandler + .long 0 + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long 0 + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DFSDM1_IRQHandler + .long DFSDM2_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long COMP_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long USB_FS_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long LPUART1_IRQHandler + .long QUADSPI_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SAI1_IRQHandler + .long 0 + .long SWPMI1_IRQHandler + .long TSC_IRQHandler + .long LCD_IRQHandler + .long AES_IRQHandler + .long RNG_IRQHandler + .long FPU_IRQHandler + .long CRS_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DFSDM1_IRQHandler + IRQ DFSDM2_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ USB_FS_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ LPUART1_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SAI1_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TSC_IRQHandler + IRQ LCD_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ CRS_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l4x2.s b/targets/device/stm32/stm32l4x2.s new file mode 100644 index 00000000..474cfcde --- /dev/null +++ b/targets/device/stm32/stm32l4x2.s @@ -0,0 +1,227 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l4x2.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L4x2 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long 0 + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SDMMC1_IRQHandler + .long 0 + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long 0 + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DFSDM1_IRQHandler + .long DFSDM2_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long COMP_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long USB_FS_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long LPUART1_IRQHandler + .long QUADSPI_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SAI1_IRQHandler + .long 0 + .long SWPMI1_IRQHandler + .long TSC_IRQHandler + .long LCD_IRQHandler + .long AES_IRQHandler + .long RNG_IRQHandler + .long FPU_IRQHandler + .long CRS_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DFSDM1_IRQHandler + IRQ DFSDM2_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ USB_FS_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ LPUART1_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SAI1_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TSC_IRQHandler + IRQ LCD_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ CRS_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l4x3.s b/targets/device/stm32/stm32l4x3.s new file mode 100644 index 00000000..ff318e00 --- /dev/null +++ b/targets/device/stm32/stm32l4x3.s @@ -0,0 +1,212 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l4x3.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L4x3 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long 0 + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long 0 + .long 0 + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SDMMC_IRQHandler + .long 0 + .long SPI3_IRQHandler + .long 0 + .long 0 + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long 0 + .long 0 + .long 0 + .long COMP_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long USB_FS_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long 0 + .long 0 + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SAI1_IRQHandler + .long 0 + .long SWPMI1_IRQHandler + .long TSC_IRQHandler + .long LCD_IRQHandler + .long RNG_IRQHandler + .long CRS_IRQHandler + .long FPU_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ SDMMC_IRQHandler + IRQ SPI3_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ USB_FS_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SAI1_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TSC_IRQHandler + IRQ LCD_IRQHandler + IRQ RNG_IRQHandler + IRQ CRS_IRQHandler + IRQ FPU_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l4x5.s b/targets/device/stm32/stm32l4x5.s new file mode 100644 index 00000000..56dca1c4 --- /dev/null +++ b/targets/device/stm32/stm32l4x5.s @@ -0,0 +1,224 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l4x5.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L4x5 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long 0 + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long EXTI9_5_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM1_TRG_COM_TIM17_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long DFSDM3_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FMC_IRQHandler + .long SDMMC_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DAC_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DFSDM0_IRQHandler + .long DFSDM1_IRQHandler + .long DFSDM2_IRQHandler + .long COMP_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long 0 + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long 0 + .long QUADSPI_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long SWPMI1_IRQHandler + .long TSC_IRQHandler + .long LCD_IRQHandler + .long AES_IRQHandler + .long RNG_IRQHandler + .long FPU_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM1_TRG_COM_TIM17_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ DFSDM3_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DAC_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DFSDM0_IRQHandler + IRQ DFSDM1_IRQHandler + IRQ DFSDM2_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TSC_IRQHandler + IRQ LCD_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ FPU_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l4x6.s b/targets/device/stm32/stm32l4x6.s new file mode 100644 index 00000000..87199e37 --- /dev/null +++ b/targets/device/stm32/stm32l4x6.s @@ -0,0 +1,249 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l4x6.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L4x6 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long TAMP_STAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC1_2_IRQHandler + .long CAN1_TX_IRQHandler + .long CAN1_RX0_IRQHandler + .long CAN1_RX1_IRQHandler + .long CAN1_SCE_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_TIM15_IRQHandler + .long TIM1_UP_TIM16_IRQHandler + .long TIM1_TRG_COM_TIM17_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long ADC3_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long TIM6_DACUNDER_IRQHandler + .long TIM7_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long COMP_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long OTG_FS_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long LPUART1_IRQHandler + .long QUADSPI_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long SWPMI1_IRQHandler + .long TSC_IRQHandler + .long LCD_IRQHandler + .long AES_IRQHandler + .long RNG_HASH_IRQHandler + .long FPU_IRQHandler + .long CRS_IRQHandler + .long I2C4_EV_IRQHandler + .long I2C4_ER_IRQHandler + .long DCMI_IRQHandler + .long CAN2_TX_IRQHandler + .long CAN2_RX0_IRQHandler + .long CAN2_RX1_IRQHandler + .long CAN2_SCE_IRQHandler + .long DMA2D_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ TAMP_STAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ CAN1_TX_IRQHandler + IRQ CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_TIM15_IRQHandler + IRQ TIM1_UP_TIM16_IRQHandler + IRQ TIM1_TRG_COM_TIM17_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TIM6_DACUNDER_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ COMP_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ OTG_FS_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ LPUART1_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ SWPMI1_IRQHandler + IRQ TSC_IRQHandler + IRQ LCD_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_HASH_IRQHandler + IRQ FPU_IRQHandler + IRQ CRS_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ DCMI_IRQHandler + IRQ CAN2_TX_IRQHandler + IRQ CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler + IRQ DMA2D_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l552.s b/targets/device/stm32/stm32l552.s new file mode 100644 index 00000000..e5b2f0d2 --- /dev/null +++ b/targets/device/stm32/stm32l552.s @@ -0,0 +1,274 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l552.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L552 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_IRQHandler + .long RTC_S_IRQHandler + .long TAMP_IRQHandler + .long TAMP_S_IRQHandler + .long FLASH_IRQHandler + .long FLASH_S_IRQHandler + .long 0 + .long RCC_IRQHandler + .long RCC_S_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long EXTI5_IRQHandler + .long EXTI6_IRQHandler + .long EXTI7_IRQHandler + .long EXTI8_IRQHandler + .long EXTI9_IRQHandler + .long EXTI10_IRQHandler + .long EXTI11_IRQHandler + .long EXTI12_IRQHandler + .long EXTI13_IRQHandler + .long EXTI14_IRQHandler + .long EXTI15_IRQHandler + .long DMAMUX1_OVR_IRQHandler + .long DMAMUX1_OVR_S_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long DMA1_Channel8_IRQHandler + .long ADC1_2_IRQHandler + .long 0 + .long FDCAN1_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long TIM5_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long LPUART1_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long COMP_IRQHandler + .long USB_FS_IRQHandler + .long 0 + .long FMC_IRQHandler + .long OCTOSPI1_IRQHandler + .long 0 + .long SDMMC1_IRQHandler + .long 0 + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMA2_CH8_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long TSC_IRQHandler + .long 0 + .long RNG_IRQHandler + .long 0 + .long 0 + .long 0 + .long LPTIM3_IRQHandler + .long SPI3_IRQHandler + .long I2C4_ER_IRQHandler + .long I2C4_EV_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long UCPD1_IRQHandler + .long ICACHE_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_S_IRQHandler + IRQ TAMP_IRQHandler + IRQ TAMP_S_IRQHandler + IRQ FLASH_IRQHandler + IRQ FLASH_S_IRQHandler + IRQ RCC_IRQHandler + IRQ RCC_S_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ DMAMUX1_OVR_IRQHandler + IRQ DMAMUX1_OVR_S_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ DMA1_Channel8_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ TIM5_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ COMP_IRQHandler + IRQ USB_FS_IRQHandler + IRQ FMC_IRQHandler + IRQ OCTOSPI1_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMA2_CH8_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ TSC_IRQHandler + IRQ RNG_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ SPI3_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ UCPD1_IRQHandler + IRQ ICACHE_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32l562.s b/targets/device/stm32/stm32l562.s new file mode 100644 index 00000000..d7687772 --- /dev/null +++ b/targets/device/stm32/stm32l562.s @@ -0,0 +1,278 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32l562.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32L562 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_IRQHandler + .long RTC_IRQHandler + .long RTC_S_IRQHandler + .long TAMP_IRQHandler + .long TAMP_S_IRQHandler + .long FLASH_IRQHandler + .long FLASH_S_IRQHandler + .long 0 + .long RCC_IRQHandler + .long RCC_S_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long EXTI5_IRQHandler + .long EXTI6_IRQHandler + .long EXTI7_IRQHandler + .long EXTI8_IRQHandler + .long EXTI9_IRQHandler + .long EXTI10_IRQHandler + .long EXTI11_IRQHandler + .long EXTI12_IRQHandler + .long EXTI13_IRQHandler + .long EXTI14_IRQHandler + .long EXTI15_IRQHandler + .long DMAMUX1_OVR_IRQHandler + .long DMAMUX1_OVR_S_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long DMA1_Channel8_IRQHandler + .long ADC1_2_IRQHandler + .long 0 + .long FDCAN1_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long TIM5_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long UART4_IRQHandler + .long UART5_IRQHandler + .long LPUART1_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long COMP_IRQHandler + .long USB_FS_IRQHandler + .long 0 + .long FMC_IRQHandler + .long OCTOSPI1_IRQHandler + .long 0 + .long SDMMC1_IRQHandler + .long 0 + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMA2_CH8_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SAI1_IRQHandler + .long SAI2_IRQHandler + .long TSC_IRQHandler + .long AES_IRQHandler + .long RNG_IRQHandler + .long 0 + .long 0 + .long PKA_IRQHandler + .long LPTIM3_IRQHandler + .long SPI3_IRQHandler + .long I2C4_ER_IRQHandler + .long I2C4_EV_IRQHandler + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long UCPD1_IRQHandler + .long ICACHE_IRQHandler + .long OTFDEC1_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_IRQHandler + IRQ RTC_IRQHandler + IRQ RTC_S_IRQHandler + IRQ TAMP_IRQHandler + IRQ TAMP_S_IRQHandler + IRQ FLASH_IRQHandler + IRQ FLASH_S_IRQHandler + IRQ RCC_IRQHandler + IRQ RCC_S_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ DMAMUX1_OVR_IRQHandler + IRQ DMAMUX1_OVR_S_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ DMA1_Channel8_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ TIM5_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ COMP_IRQHandler + IRQ USB_FS_IRQHandler + IRQ FMC_IRQHandler + IRQ OCTOSPI1_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMA2_CH8_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SAI1_IRQHandler + IRQ SAI2_IRQHandler + IRQ TSC_IRQHandler + IRQ AES_IRQHandler + IRQ RNG_IRQHandler + IRQ PKA_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ SPI3_IRQHandler + IRQ I2C4_ER_IRQHandler + IRQ I2C4_EV_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ UCPD1_IRQHandler + IRQ ICACHE_IRQHandler + IRQ OTFDEC1_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32mp153.s b/targets/device/stm32/stm32mp153.s new file mode 100644 index 00000000..69c68e39 --- /dev/null +++ b/targets/device/stm32/stm32mp153.s @@ -0,0 +1,424 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32mp153.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32MP153x +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG1_IT_IRQHandler + .long PVD_AVD_IRQHandler + .long TAMP_IRQHandler + .long RTC_WKUP_ALARM_IRQHandler + .long TZC_IT_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_STR0_IRQHandler + .long DMA1_STR1_IRQHandler + .long DMA1_STR2_IRQHandler + .long DMA1_STR3_IRQHandler + .long DMA1_STR4_IRQHandler + .long DMA1_STR5_IRQHandler + .long DMA1_STR6_IRQHandler + .long ADC1_IRQHandler + .long FDCAN1_IT0_IRQHandler + .long FDCAN2_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long FDCAN2_IT1_IRQHandler + .long EXTI5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EVT_IRQHandler + .long I2C1_ERR_IRQHandler + .long I2C2_EVT_IRQHandler + .long I2C2_ERR_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI10_IRQHandler + .long RTC_TS_IRQHandler + .long EXTI11_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_STR7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long USART4_IRQHandler + .long USART5_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long DMA2_STR0_IRQHandler + .long DMA2_STR1_IRQHandler + .long DMA2_STR2_IRQHandler + .long DMA2_STR3_IRQHandler + .long DMA2_STR4_IRQHandler + .long ETH1_IRQHandler + .long ETH1_WKUP_IRQHandler + .long 0 + .long EXTI6_IRQHandler + .long EXTI7_IRQHandler + .long EXTI8_IRQHandler + .long EXTI9_IRQHandler + .long DMA2_STR5_IRQHandler + .long DMA2_STR6_IRQHandler + .long DMA2_STR7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EVT_IRQHandler + .long I2C3_ERR_IRQHandler + .long 0 + .long 0 + .long EXTI12_IRQHandler + .long EXTI13_IRQHandler + .long DCMI_IRQHandler + .long CRYP1_IRQHandler + .long HASH1_IRQHandler + .long 0 + .long USART7_IRQHandler + .long USART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long ADC2_IRQHandler + .long SAI2_IRQHandler + .long QUADSPI_IRQHandler + .long LPTIM1_IRQHandler + .long CEC_IRQHandler + .long I2C4_EVT_IRQHandler + .long I2C4_ERR_IRQHandler + .long SPDIFRX_IRQHandler + .long OTG_IRQHandler + .long 0 + .long IPCC_RX0_IRQHandler + .long IPCC_TX0_IRQHandler + .long DMAMUX1_OVR_REQ_IRQHandler + .long IPCC_RX1_IRQHandler + .long IPCC_TX1_IRQHandler + .long CRYP2_IRQHandler + .long HASH2_IRQHandler + .long I2C5_EVT_IRQHandler + .long I2C5_ERR_IRQHandler + .long 0 + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SAI3_IRQHandler + .long DFSDM1_FLT4_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long TIM12_IRQHandler + .long MDIOS_IRQHandler + .long EXTI14_IRQHandler + .long MDMA_IRQHandler + .long 0 + .long SDMMC2_IRQHandler + .long HSEM_IT2_IRQHandler + .long DFSDM1_FLT5_IRQHandler + .long EXTI15_IRQHandler + .long 0 + .long 0 + .long TIM13_IRQHandler + .long TIM14_IRQHandler + .long DAC_IRQHandler + .long RNG1_IRQHandler + .long RNG2_IRQHandler + .long I2C6_EVT_IRQHandler + .long I2C6_ERR_IRQHandler + .long SDMMC3_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long LPTIM4_IRQHandler + .long LPTIM5_IRQHandler + .long ETH1_LPI_IRQHandler + .long 0 + .long 0 + .long RCC_WAKEUP_IRQHandler + .long SAI4_IRQHandler + .long DTS_IRQHandler + .long 0 + .long 0 + .long IWDG1_IT_IRQHandler + .long IWDG2_IT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TAMP_S_IRQHandler + .long RTC_WKUP_ALARM_S_IRQHandler + .long RTC_TS_S_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DDRPERFM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG1_IT_IRQHandler + IRQ PVD_AVD_IRQHandler + IRQ TAMP_IRQHandler + IRQ RTC_WKUP_ALARM_IRQHandler + IRQ TZC_IT_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_STR0_IRQHandler + IRQ DMA1_STR1_IRQHandler + IRQ DMA1_STR2_IRQHandler + IRQ DMA1_STR3_IRQHandler + IRQ DMA1_STR4_IRQHandler + IRQ DMA1_STR5_IRQHandler + IRQ DMA1_STR6_IRQHandler + IRQ ADC1_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN2_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ FDCAN2_IT1_IRQHandler + IRQ EXTI5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EVT_IRQHandler + IRQ I2C1_ERR_IRQHandler + IRQ I2C2_EVT_IRQHandler + IRQ I2C2_ERR_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI10_IRQHandler + IRQ RTC_TS_IRQHandler + IRQ EXTI11_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_STR7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ USART4_IRQHandler + IRQ USART5_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_STR0_IRQHandler + IRQ DMA2_STR1_IRQHandler + IRQ DMA2_STR2_IRQHandler + IRQ DMA2_STR3_IRQHandler + IRQ DMA2_STR4_IRQHandler + IRQ ETH1_IRQHandler + IRQ ETH1_WKUP_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ DMA2_STR5_IRQHandler + IRQ DMA2_STR6_IRQHandler + IRQ DMA2_STR7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EVT_IRQHandler + IRQ I2C3_ERR_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP1_IRQHandler + IRQ HASH1_IRQHandler + IRQ USART7_IRQHandler + IRQ USART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ ADC2_IRQHandler + IRQ SAI2_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C4_EVT_IRQHandler + IRQ I2C4_ERR_IRQHandler + IRQ SPDIFRX_IRQHandler + IRQ OTG_IRQHandler + IRQ IPCC_RX0_IRQHandler + IRQ IPCC_TX0_IRQHandler + IRQ DMAMUX1_OVR_REQ_IRQHandler + IRQ IPCC_RX1_IRQHandler + IRQ IPCC_TX1_IRQHandler + IRQ CRYP2_IRQHandler + IRQ HASH2_IRQHandler + IRQ I2C5_EVT_IRQHandler + IRQ I2C5_ERR_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SAI3_IRQHandler + IRQ DFSDM1_FLT4_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ TIM12_IRQHandler + IRQ MDIOS_IRQHandler + IRQ EXTI14_IRQHandler + IRQ MDMA_IRQHandler + IRQ SDMMC2_IRQHandler + IRQ HSEM_IT2_IRQHandler + IRQ DFSDM1_FLT5_IRQHandler + IRQ EXTI15_IRQHandler + IRQ TIM13_IRQHandler + IRQ TIM14_IRQHandler + IRQ DAC_IRQHandler + IRQ RNG1_IRQHandler + IRQ RNG2_IRQHandler + IRQ I2C6_EVT_IRQHandler + IRQ I2C6_ERR_IRQHandler + IRQ SDMMC3_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ LPTIM4_IRQHandler + IRQ LPTIM5_IRQHandler + IRQ ETH1_LPI_IRQHandler + IRQ RCC_WAKEUP_IRQHandler + IRQ SAI4_IRQHandler + IRQ DTS_IRQHandler + IRQ IWDG1_IT_IRQHandler + IRQ IWDG2_IT_IRQHandler + IRQ TAMP_S_IRQHandler + IRQ RTC_WKUP_ALARM_S_IRQHandler + IRQ RTC_TS_S_IRQHandler + IRQ DDRPERFM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32mp157.s b/targets/device/stm32/stm32mp157.s new file mode 100644 index 00000000..dc963e54 --- /dev/null +++ b/targets/device/stm32/stm32mp157.s @@ -0,0 +1,425 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32mp157.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32MP157x +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG1_IT_IRQHandler + .long PVD_AVD_IRQHandler + .long TAMP_IRQHandler + .long RTC_WKUP_ALARM_IRQHandler + .long TZC_IT_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_STR0_IRQHandler + .long DMA1_STR1_IRQHandler + .long DMA1_STR2_IRQHandler + .long DMA1_STR3_IRQHandler + .long DMA1_STR4_IRQHandler + .long DMA1_STR5_IRQHandler + .long DMA1_STR6_IRQHandler + .long ADC1_IRQHandler + .long FDCAN1_IT0_IRQHandler + .long FDCAN2_IT0_IRQHandler + .long FDCAN1_IT1_IRQHandler + .long FDCAN2_IT1_IRQHandler + .long EXTI5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM3_IRQHandler + .long TIM4_IRQHandler + .long I2C1_EVT_IRQHandler + .long I2C1_ERR_IRQHandler + .long I2C2_EVT_IRQHandler + .long I2C2_ERR_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long USART3_IRQHandler + .long EXTI10_IRQHandler + .long RTC_TS_IRQHandler + .long EXTI11_IRQHandler + .long TIM8_BRK_IRQHandler + .long TIM8_UP_IRQHandler + .long TIM8_TRG_COM_IRQHandler + .long TIM8_CC_IRQHandler + .long DMA1_STR7_IRQHandler + .long FMC_IRQHandler + .long SDMMC1_IRQHandler + .long TIM5_IRQHandler + .long SPI3_IRQHandler + .long USART4_IRQHandler + .long USART5_IRQHandler + .long TIM6_IRQHandler + .long TIM7_IRQHandler + .long DMA2_STR0_IRQHandler + .long DMA2_STR1_IRQHandler + .long DMA2_STR2_IRQHandler + .long DMA2_STR3_IRQHandler + .long DMA2_STR4_IRQHandler + .long ETH1_IRQHandler + .long ETH1_WKUP_IRQHandler + .long 0 + .long EXTI6_IRQHandler + .long EXTI7_IRQHandler + .long EXTI8_IRQHandler + .long EXTI9_IRQHandler + .long DMA2_STR5_IRQHandler + .long DMA2_STR6_IRQHandler + .long DMA2_STR7_IRQHandler + .long USART6_IRQHandler + .long I2C3_EVT_IRQHandler + .long I2C3_ERR_IRQHandler + .long 0 + .long 0 + .long EXTI12_IRQHandler + .long EXTI13_IRQHandler + .long DCMI_IRQHandler + .long CRYP1_IRQHandler + .long HASH1_IRQHandler + .long 0 + .long USART7_IRQHandler + .long USART8_IRQHandler + .long SPI4_IRQHandler + .long SPI5_IRQHandler + .long SPI6_IRQHandler + .long SAI1_IRQHandler + .long LTDC_IRQHandler + .long LTDC_ER_IRQHandler + .long ADC2_IRQHandler + .long SAI2_IRQHandler + .long QUADSPI_IRQHandler + .long LPTIM1_IRQHandler + .long CEC_IRQHandler + .long I2C4_EVT_IRQHandler + .long I2C4_ERR_IRQHandler + .long SPDIFRX_IRQHandler + .long OTG_IRQHandler + .long 0 + .long IPCC_RX0_IRQHandler + .long IPCC_TX0_IRQHandler + .long DMAMUX1_OVR_REQ_IRQHandler + .long IPCC_RX1_IRQHandler + .long IPCC_TX1_IRQHandler + .long CRYP2_IRQHandler + .long HASH2_IRQHandler + .long I2C5_EVT_IRQHandler + .long I2C5_ERR_IRQHandler + .long 0 + .long DFSDM1_FLT0_IRQHandler + .long DFSDM1_FLT1_IRQHandler + .long DFSDM1_FLT2_IRQHandler + .long DFSDM1_FLT3_IRQHandler + .long SAI3_IRQHandler + .long DFSDM1_FLT4_IRQHandler + .long TIM15_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long TIM12_IRQHandler + .long MDIOS_IRQHandler + .long EXTI14_IRQHandler + .long MDMA_IRQHandler + .long DSI_IRQHandler + .long SDMMC2_IRQHandler + .long HSEM_IT2_IRQHandler + .long DFSDM1_FLT5_IRQHandler + .long EXTI15_IRQHandler + .long 0 + .long 0 + .long TIM13_IRQHandler + .long TIM14_IRQHandler + .long DAC_IRQHandler + .long RNG1_IRQHandler + .long RNG2_IRQHandler + .long I2C6_EVT_IRQHandler + .long I2C6_ERR_IRQHandler + .long SDMMC3_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long LPTIM4_IRQHandler + .long LPTIM5_IRQHandler + .long ETH1_LPI_IRQHandler + .long 0 + .long 0 + .long RCC_WAKEUP_IRQHandler + .long SAI4_IRQHandler + .long DTS_IRQHandler + .long 0 + .long 0 + .long IWDG1_IT_IRQHandler + .long IWDG2_IT_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long TAMP_S_IRQHandler + .long RTC_WKUP_ALARM_S_IRQHandler + .long RTC_TS_S_IRQHandler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long DDRPERFM_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG1_IT_IRQHandler + IRQ PVD_AVD_IRQHandler + IRQ TAMP_IRQHandler + IRQ RTC_WKUP_ALARM_IRQHandler + IRQ TZC_IT_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_STR0_IRQHandler + IRQ DMA1_STR1_IRQHandler + IRQ DMA1_STR2_IRQHandler + IRQ DMA1_STR3_IRQHandler + IRQ DMA1_STR4_IRQHandler + IRQ DMA1_STR5_IRQHandler + IRQ DMA1_STR6_IRQHandler + IRQ ADC1_IRQHandler + IRQ FDCAN1_IT0_IRQHandler + IRQ FDCAN2_IT0_IRQHandler + IRQ FDCAN1_IT1_IRQHandler + IRQ FDCAN2_IT1_IRQHandler + IRQ EXTI5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM3_IRQHandler + IRQ TIM4_IRQHandler + IRQ I2C1_EVT_IRQHandler + IRQ I2C1_ERR_IRQHandler + IRQ I2C2_EVT_IRQHandler + IRQ I2C2_ERR_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EXTI10_IRQHandler + IRQ RTC_TS_IRQHandler + IRQ EXTI11_IRQHandler + IRQ TIM8_BRK_IRQHandler + IRQ TIM8_UP_IRQHandler + IRQ TIM8_TRG_COM_IRQHandler + IRQ TIM8_CC_IRQHandler + IRQ DMA1_STR7_IRQHandler + IRQ FMC_IRQHandler + IRQ SDMMC1_IRQHandler + IRQ TIM5_IRQHandler + IRQ SPI3_IRQHandler + IRQ USART4_IRQHandler + IRQ USART5_IRQHandler + IRQ TIM6_IRQHandler + IRQ TIM7_IRQHandler + IRQ DMA2_STR0_IRQHandler + IRQ DMA2_STR1_IRQHandler + IRQ DMA2_STR2_IRQHandler + IRQ DMA2_STR3_IRQHandler + IRQ DMA2_STR4_IRQHandler + IRQ ETH1_IRQHandler + IRQ ETH1_WKUP_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ DMA2_STR5_IRQHandler + IRQ DMA2_STR6_IRQHandler + IRQ DMA2_STR7_IRQHandler + IRQ USART6_IRQHandler + IRQ I2C3_EVT_IRQHandler + IRQ I2C3_ERR_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ DCMI_IRQHandler + IRQ CRYP1_IRQHandler + IRQ HASH1_IRQHandler + IRQ USART7_IRQHandler + IRQ USART8_IRQHandler + IRQ SPI4_IRQHandler + IRQ SPI5_IRQHandler + IRQ SPI6_IRQHandler + IRQ SAI1_IRQHandler + IRQ LTDC_IRQHandler + IRQ LTDC_ER_IRQHandler + IRQ ADC2_IRQHandler + IRQ SAI2_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C4_EVT_IRQHandler + IRQ I2C4_ERR_IRQHandler + IRQ SPDIFRX_IRQHandler + IRQ OTG_IRQHandler + IRQ IPCC_RX0_IRQHandler + IRQ IPCC_TX0_IRQHandler + IRQ DMAMUX1_OVR_REQ_IRQHandler + IRQ IPCC_RX1_IRQHandler + IRQ IPCC_TX1_IRQHandler + IRQ CRYP2_IRQHandler + IRQ HASH2_IRQHandler + IRQ I2C5_EVT_IRQHandler + IRQ I2C5_ERR_IRQHandler + IRQ DFSDM1_FLT0_IRQHandler + IRQ DFSDM1_FLT1_IRQHandler + IRQ DFSDM1_FLT2_IRQHandler + IRQ DFSDM1_FLT3_IRQHandler + IRQ SAI3_IRQHandler + IRQ DFSDM1_FLT4_IRQHandler + IRQ TIM15_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ TIM12_IRQHandler + IRQ MDIOS_IRQHandler + IRQ EXTI14_IRQHandler + IRQ MDMA_IRQHandler + IRQ DSI_IRQHandler + IRQ SDMMC2_IRQHandler + IRQ HSEM_IT2_IRQHandler + IRQ DFSDM1_FLT5_IRQHandler + IRQ EXTI15_IRQHandler + IRQ TIM13_IRQHandler + IRQ TIM14_IRQHandler + IRQ DAC_IRQHandler + IRQ RNG1_IRQHandler + IRQ RNG2_IRQHandler + IRQ I2C6_EVT_IRQHandler + IRQ I2C6_ERR_IRQHandler + IRQ SDMMC3_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ LPTIM4_IRQHandler + IRQ LPTIM5_IRQHandler + IRQ ETH1_LPI_IRQHandler + IRQ RCC_WAKEUP_IRQHandler + IRQ SAI4_IRQHandler + IRQ DTS_IRQHandler + IRQ IWDG1_IT_IRQHandler + IRQ IWDG2_IT_IRQHandler + IRQ TAMP_S_IRQHandler + IRQ RTC_WKUP_ALARM_S_IRQHandler + IRQ RTC_TS_S_IRQHandler + IRQ DDRPERFM_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32wb55.s b/targets/device/stm32/stm32wb55.s new file mode 100644 index 00000000..0b3ce6df --- /dev/null +++ b/targets/device/stm32/stm32wb55.s @@ -0,0 +1,193 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32wb55.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32WBxx_CM4 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_IRQHandler + .long RTC_TAMP_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_Channel1_IRQHandler + .long DMA1_Channel2_IRQHandler + .long DMA1_Channel3_IRQHandler + .long DMA1_Channel4_IRQHandler + .long DMA1_Channel5_IRQHandler + .long DMA1_Channel6_IRQHandler + .long DMA1_Channel7_IRQHandler + .long ADC1_IRQHandler + .long USB_HP_IRQHandler + .long USB_LP_IRQHandler + .long C2SEV_IRQHandler + .long COMP_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_TIM17_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long PKA_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long USART1_IRQHandler + .long LPUART1_IRQHandler + .long SAI1_IRQHandler + .long TSC_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long CRS_IT_IRQHandler + .long PWR_SOTF_IRQHandler + .long IPCC_C1_RX_IT_IRQHandler + .long IPCC_C1_TX_IT_IRQHandler + .long HSEM_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long LCD_IRQHandler + .long QUADSPI_IRQHandler + .long AES1_IRQHandler + .long AES2_IRQHandler + .long True_RNG_IRQHandler + .long FPU_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMAMUX_OVR_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_IRQHandler + IRQ RTC_TAMP_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_IRQHandler + IRQ USB_HP_IRQHandler + IRQ USB_LP_IRQHandler + IRQ C2SEV_IRQHandler + IRQ COMP_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_TIM17_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ PKA_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ LPUART1_IRQHandler + IRQ SAI1_IRQHandler + IRQ TSC_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ CRS_IT_IRQHandler + IRQ PWR_SOTF_IRQHandler + IRQ IPCC_C1_RX_IT_IRQHandler + IRQ IPCC_C1_TX_IT_IRQHandler + IRQ HSEM_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LCD_IRQHandler + IRQ QUADSPI_IRQHandler + IRQ AES1_IRQHandler + IRQ AES2_IRQHandler + IRQ True_RNG_IRQHandler + IRQ FPU_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMAMUX_OVR_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32wl5x_cm0p.s b/targets/device/stm32/stm32wl5x_cm0p.s new file mode 100644 index 00000000..c4aba843 --- /dev/null +++ b/targets/device/stm32/stm32wl5x_cm0p.s @@ -0,0 +1,131 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32wl5x_cm0p.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32WL5x_CM0P +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long TZIC_ILA_IRQHandler + .long PVD_PVM_3_IRQHandler + .long TAMP_RTCSTAMP_LSECSS_RTCALARM_RTCSSRU_RTCWKUP_IRQHandler + .long FLASH_RCC_C1SEV_IRQHandler + .long EXTI1_0_IRQHandler + .long EXTI3_2_IRQHandler + .long EXTI15_4_IRQHandler + .long ADC_COMP_DAC_IRQHandler + .long DMA1_CH3_1_IRQHandler + .long DMA1_CH7_4_IRQHandler + .long DMA2_CH7_1_DMAMUX1_OVR_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long LPTIM3_IRQHandler + .long TIM1_BRK_TIM1_UP_TIM1_TRG_COM_TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long IPCC_C2_RX_IT_IPCC_C2_TX_IT_IRQHandler + .long HSEM_IRQHandler + .long True_RNG_IRQHandler + .long AES_PKA_IRQHandler + .long I2C1_EV_I2C1_ER_IRQHandler + .long I2C2_EV_I2C2_ER_IRQHandler + .long I2C3_EV_I2C3_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2S2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long LPUART1_IRQHandler + .long SUBGHZSPI_IRQHandler + .long Radio_IRQ_Busy_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ TZIC_ILA_IRQHandler + IRQ PVD_PVM_3_IRQHandler + IRQ TAMP_RTCSTAMP_LSECSS_RTCALARM_RTCSSRU_RTCWKUP_IRQHandler + IRQ FLASH_RCC_C1SEV_IRQHandler + IRQ EXTI1_0_IRQHandler + IRQ EXTI3_2_IRQHandler + IRQ EXTI15_4_IRQHandler + IRQ ADC_COMP_DAC_IRQHandler + IRQ DMA1_CH3_1_IRQHandler + IRQ DMA1_CH7_4_IRQHandler + IRQ DMA2_CH7_1_DMAMUX1_OVR_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ TIM1_BRK_TIM1_UP_TIM1_TRG_COM_TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ IPCC_C2_RX_IT_IPCC_C2_TX_IT_IRQHandler + IRQ HSEM_IRQHandler + IRQ True_RNG_IRQHandler + IRQ AES_PKA_IRQHandler + IRQ I2C1_EV_I2C1_ER_IRQHandler + IRQ I2C2_EV_I2C2_ER_IRQHandler + IRQ I2C3_EV_I2C3_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2S2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ LPUART1_IRQHandler + IRQ SUBGHZSPI_IRQHandler + IRQ Radio_IRQ_Busy_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32wl5x_cm4.s b/targets/device/stm32/stm32wl5x_cm4.s new file mode 100644 index 00000000..6fbc20ef --- /dev/null +++ b/targets/device/stm32/stm32wl5x_cm4.s @@ -0,0 +1,191 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32wl5x_cm4.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32WL5x_CM4 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_3_IRQHandler + .long TAMP_RTCSTAMP_LSECSS_RTCSSRU_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC_IRQHandler + .long DAC_IRQHandler + .long PWR_C2H_C2SEV_IRQHandler + .long COMP_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2S2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long LPUART1_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long LPTIM3_IRQHandler + .long SUBGHZSPI_IRQHandler + .long IPCC_C1_RX_IT_IRQHandler + .long IPCC_C1_TX_IT_IRQHandler + .long HSEM_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long Radio_IRQ_Busy_IRQHandler + .long AES_IRQHandler + .long True_RNG_IRQHandler + .long PKA_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMAMUX1_OVR_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_3_IRQHandler + IRQ TAMP_RTCSTAMP_LSECSS_RTCSSRU_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC_IRQHandler + IRQ DAC_IRQHandler + IRQ PWR_C2H_C2SEV_IRQHandler + IRQ COMP_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2S2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ SUBGHZSPI_IRQHandler + IRQ IPCC_C1_RX_IT_IRQHandler + IRQ IPCC_C1_TX_IT_IRQHandler + IRQ HSEM_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ Radio_IRQ_Busy_IRQHandler + IRQ AES_IRQHandler + IRQ True_RNG_IRQHandler + IRQ PKA_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMAMUX1_OVR_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/device/stm32/stm32wle5.s b/targets/device/stm32/stm32wle5.s new file mode 100644 index 00000000..21f1173f --- /dev/null +++ b/targets/device/stm32/stm32wle5.s @@ -0,0 +1,187 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from stm32wle5.svd, see https://github.com/tinygo-org/stm32-svd + +/* +// STM32WLE5_CM4 +*/ + + + +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + wfe + b Default_Handler +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +// Must set the "a" flag on the section: +// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049 +// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Extra interrupts for peripherals defined by the hardware vendor. + .long WWDG_IRQHandler + .long PVD_PVM_3_IRQHandler + .long TAMP_RTCSTAMP_LSECSS_RTCSSRU_IRQHandler + .long RTC_WKUP_IRQHandler + .long FLASH_IRQHandler + .long RCC_IRQHandler + .long EXTI0_IRQHandler + .long EXTI1_IRQHandler + .long EXTI2_IRQHandler + .long EXTI3_IRQHandler + .long EXTI4_IRQHandler + .long DMA1_CH1_IRQHandler + .long DMA1_CH2_IRQHandler + .long DMA1_CH3_IRQHandler + .long DMA1_CH4_IRQHandler + .long DMA1_CH5_IRQHandler + .long DMA1_CH6_IRQHandler + .long DMA1_CH7_IRQHandler + .long ADC_IRQHandler + .long DAC_IRQHandler + .long 0 + .long COMP_IRQHandler + .long EXTI9_5_IRQHandler + .long TIM1_BRK_IRQHandler + .long TIM1_UP_IRQHandler + .long TIM1_TRG_COM_IRQHandler + .long TIM1_CC_IRQHandler + .long TIM2_IRQHandler + .long TIM16_IRQHandler + .long TIM17_IRQHandler + .long I2C1_EV_IRQHandler + .long I2C1_ER_IRQHandler + .long I2C2_EV_IRQHandler + .long I2C2_ER_IRQHandler + .long SPI1_IRQHandler + .long SPI2S2_IRQHandler + .long USART1_IRQHandler + .long USART2_IRQHandler + .long LPUART1_IRQHandler + .long LPTIM1_IRQHandler + .long LPTIM2_IRQHandler + .long EXTI15_10_IRQHandler + .long RTC_ALARM_IRQHandler + .long LPTIM3_IRQHandler + .long 0 + .long 0 + .long 0 + .long HSEM_IRQHandler + .long I2C3_EV_IRQHandler + .long I2C3_ER_IRQHandler + .long Radio_IRQ_Busy_IRQHandler + .long AES_IRQHandler + .long True_RNG_IRQHandler + .long PKA_IRQHandler + .long DMA2_CH1_IRQHandler + .long DMA2_CH2_IRQHandler + .long DMA2_CH3_IRQHandler + .long DMA2_CH4_IRQHandler + .long DMA2_CH5_IRQHandler + .long DMA2_CH6_IRQHandler + .long DMA2_CH7_IRQHandler + .long DMAMUX1_OVR_IRQHandler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + IRQ WWDG_IRQHandler + IRQ PVD_PVM_3_IRQHandler + IRQ TAMP_RTCSTAMP_LSECSS_RTCSSRU_IRQHandler + IRQ RTC_WKUP_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCC_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ DMA1_CH1_IRQHandler + IRQ DMA1_CH2_IRQHandler + IRQ DMA1_CH3_IRQHandler + IRQ DMA1_CH4_IRQHandler + IRQ DMA1_CH5_IRQHandler + IRQ DMA1_CH6_IRQHandler + IRQ DMA1_CH7_IRQHandler + IRQ ADC_IRQHandler + IRQ DAC_IRQHandler + IRQ COMP_IRQHandler + IRQ EXTI9_5_IRQHandler + IRQ TIM1_BRK_IRQHandler + IRQ TIM1_UP_IRQHandler + IRQ TIM1_TRG_COM_IRQHandler + IRQ TIM1_CC_IRQHandler + IRQ TIM2_IRQHandler + IRQ TIM16_IRQHandler + IRQ TIM17_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2S2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ LPUART1_IRQHandler + IRQ LPTIM1_IRQHandler + IRQ LPTIM2_IRQHandler + IRQ EXTI15_10_IRQHandler + IRQ RTC_ALARM_IRQHandler + IRQ LPTIM3_IRQHandler + IRQ HSEM_IRQHandler + IRQ I2C3_EV_IRQHandler + IRQ I2C3_ER_IRQHandler + IRQ Radio_IRQ_Busy_IRQHandler + IRQ AES_IRQHandler + IRQ True_RNG_IRQHandler + IRQ PKA_IRQHandler + IRQ DMA2_CH1_IRQHandler + IRQ DMA2_CH2_IRQHandler + IRQ DMA2_CH3_IRQHandler + IRQ DMA2_CH4_IRQHandler + IRQ DMA2_CH5_IRQHandler + IRQ DMA2_CH6_IRQHandler + IRQ DMA2_CH7_IRQHandler + IRQ DMAMUX1_OVR_IRQHandler + +.size __isr_vector, .-__isr_vector diff --git a/targets/esp32.json b/targets/esp32.json index f49282fd..841c7d41 100644 --- a/targets/esp32.json +++ b/targets/esp32.json @@ -11,8 +11,7 @@ "libc": "picolibc", "linkerscript": "targets/esp32.ld", "extra-files": [ - "src/device/esp/esp32.S", - "src/internal/task/task_stack_esp32.S" + "targets/device/esp/esp32.S" ], "binary-format": "esp32", "flash-command": "esptool.py --chip=esp32 --port {port} write_flash 0x1000 {bin} -ff 80m -fm dout", diff --git a/targets/esp32c3.json b/targets/esp32c3.json index 900c4845..b9586bef 100644 --- a/targets/esp32c3.json +++ b/targets/esp32c3.json @@ -10,7 +10,7 @@ ], "linkerscript": "targets/esp32c3.ld", "extra-files": [ - "src/device/esp/esp32c3.S" + "targets/device/esp/esp32c3.S" ], "binary-format": "esp32c3", "flash-command": "esptool.py --chip=esp32c3 --port {port} write_flash 0x0 {bin}", diff --git a/targets/esp8266.json b/targets/esp8266.json index bb02c3db..390ce61c 100644 --- a/targets/esp8266.json +++ b/targets/esp8266.json @@ -10,8 +10,7 @@ "libc": "picolibc", "linkerscript": "targets/esp8266.ld", "extra-files": [ - "src/device/esp/esp8266.S", - "src/internal/task/task_stack_esp8266.S" + "targets/device/esp/esp8266.S" ], "binary-format": "esp8266", "flash-command": "esptool.py --chip=esp8266 --port {port} write_flash 0x00000 {bin} -fm qio" diff --git a/targets/feather-stm32f405.json b/targets/feather-stm32f405.json index 3d824d1e..2d5a0d1b 100644 --- a/targets/feather-stm32f405.json +++ b/targets/feather-stm32f405.json @@ -5,7 +5,7 @@ "automatic-stack-size": false, "linkerscript": "targets/stm32f405.ld", "extra-files": [ - "src/device/stm32/stm32f405.s" + "targets/device/stm32/stm32f405.s" ], "flash-method": "command", "flash-command": "dfu-util --alt 0 --dfuse-address 0x08000000 --download {bin}", diff --git a/targets/gameboy-advance.json b/targets/gameboy-advance.json index 72ab6e3a..3bf6270c 100644 --- a/targets/gameboy-advance.json +++ b/targets/gameboy-advance.json @@ -20,8 +20,7 @@ ], "linkerscript": "targets/gameboy-advance.ld", "extra-files": [ - "targets/gameboy-advance.s", - "src/runtime/asm_arm.S" + "targets/gameboy-advance.s" ], "gdb": ["gdb-multiarch"], "emulator": "mgba -3 {}" diff --git a/targets/mksnanov3.json b/targets/mksnanov3.json index fc57a71d..d6b07593 100644 --- a/targets/mksnanov3.json +++ b/targets/mksnanov3.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32f407.ld", "extra-files": [ - "src/device/stm32/stm32f407.s" + "targets/device/stm32/stm32f407.s" ], "flash-method": "openocd", "openocd-interface": "stlink", diff --git a/targets/nintendoswitch.json b/targets/nintendoswitch.json index f83f8fcc..15a21bac 100644 --- a/targets/nintendoswitch.json +++ b/targets/nintendoswitch.json @@ -28,8 +28,6 @@ "linkerscript": "targets/nintendoswitch.ld", "extra-files": [ "targets/nintendoswitch.s", - "src/internal/task/task_stack_arm64.S", - "src/runtime/asm_arm64.S", - "src/runtime/runtime_nintendoswitch.S" + "targets/runtime_nintendoswitch.S" ] } diff --git a/targets/nrf51.json b/targets/nrf51.json index 714e2c55..5a85de65 100644 --- a/targets/nrf51.json +++ b/targets/nrf51.json @@ -8,8 +8,7 @@ ], "linkerscript": "targets/nrf51.ld", "extra-files": [ - "lib/nrfx/mdk/system_nrf51.c", - "src/device/nrf/nrf51.s" + "targets/device/nrf/nrf51.s" ], "openocd-transport": "swd", "openocd-target": "nrf51" diff --git a/targets/nrf52.json b/targets/nrf52.json index 3248ef73..1f579d51 100644 --- a/targets/nrf52.json +++ b/targets/nrf52.json @@ -8,8 +8,7 @@ ], "linkerscript": "targets/nrf52.ld", "extra-files": [ - "lib/nrfx/mdk/system_nrf52.c", - "src/device/nrf/nrf52.s" + "targets/device/nrf/nrf52.s" ], "openocd-transport": "swd", "openocd-target": "nrf51" diff --git a/targets/nrf52833.json b/targets/nrf52833.json index 54304dbc..99f6f808 100644 --- a/targets/nrf52833.json +++ b/targets/nrf52833.json @@ -8,8 +8,7 @@ ], "linkerscript": "targets/nrf52833.ld", "extra-files": [ - "lib/nrfx/mdk/system_nrf52833.c", - "src/device/nrf/nrf52833.s" + "targets/device/nrf/nrf52833.s" ], "openocd-transport": "swd", "openocd-target": "nrf52" diff --git a/targets/nrf52840.json b/targets/nrf52840.json index 9d86a650..ccd1ea22 100644 --- a/targets/nrf52840.json +++ b/targets/nrf52840.json @@ -8,8 +8,7 @@ ], "linkerscript": "targets/nrf52840.ld", "extra-files": [ - "lib/nrfx/mdk/system_nrf52840.c", - "src/device/nrf/nrf52840.s" + "targets/device/nrf/nrf52840.s" ], "openocd-transport": "swd", "openocd-target": "nrf51" diff --git a/targets/nucleo-f103rb.json b/targets/nucleo-f103rb.json index 723c5eef..7f8b78e7 100644 --- a/targets/nucleo-f103rb.json +++ b/targets/nucleo-f103rb.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32f103rb.ld", "extra-files": [ - "src/device/stm32/stm32f103.s" + "targets/device/stm32/stm32f103.s" ], "flash-method": "openocd", "openocd-interface": "stlink-v2-1", diff --git a/targets/nucleo-f722ze.json b/targets/nucleo-f722ze.json index f426b332..8d353541 100644 --- a/targets/nucleo-f722ze.json +++ b/targets/nucleo-f722ze.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32f7x2zetx.ld", "extra-files": [ - "src/device/stm32/stm32f7x2.s" + "targets/device/stm32/stm32f7x2.s" ], "flash-method": "openocd", "openocd-interface": "stlink-v2-1", diff --git a/targets/nucleo-l031k6.json b/targets/nucleo-l031k6.json index eed8f38f..c418c3c1 100644 --- a/targets/nucleo-l031k6.json +++ b/targets/nucleo-l031k6.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32l031k6.ld", "extra-files": [ - "src/device/stm32/stm32l0x1.s" + "targets/device/stm32/stm32l0x1.s" ], "flash-method": "openocd", "openocd-interface": "stlink", diff --git a/targets/nucleo-l432kc.json b/targets/nucleo-l432kc.json index 028b034b..f45c0dbd 100644 --- a/targets/nucleo-l432kc.json +++ b/targets/nucleo-l432kc.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32l4x2.ld", "extra-files": [ - "src/device/stm32/stm32l4x2.s" + "targets/device/stm32/stm32l4x2.s" ], "flash-method": "openocd", "openocd-interface": "stlink-v2-1", diff --git a/targets/nucleo-l476rg.json b/targets/nucleo-l476rg.json index 73eddee8..8db0c0b6 100644 --- a/targets/nucleo-l476rg.json +++ b/targets/nucleo-l476rg.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32l4x6.ld", "extra-files": [ - "src/device/stm32/stm32l4x6.s" + "targets/device/stm32/stm32l4x6.s" ], "flash-method": "openocd", "openocd-interface": "stlink-v2-1", diff --git a/targets/nucleo-l552ze.json b/targets/nucleo-l552ze.json index 9ee43680..306e8ec6 100644 --- a/targets/nucleo-l552ze.json +++ b/targets/nucleo-l552ze.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32l5x2xe.ld", "extra-files": [ - "src/device/stm32/stm32l552.s" + "targets/device/stm32/stm32l552.s" ], "flash-method": "openocd", "openocd-interface": "stlink", diff --git a/targets/riscv.json b/targets/riscv.json index 920110da..a7bc21a2 100644 --- a/targets/riscv.json +++ b/targets/riscv.json @@ -16,10 +16,8 @@ "--gc-sections" ], "extra-files": [ - "src/device/riscv/start.S", - "src/internal/task/task_stack_tinygoriscv.S", - "src/runtime/asm_riscv.S", - "src/device/riscv/handleinterrupt.S" + "targets/device/riscv/start.S", + "targets/device/riscv/handleinterrupt.S" ], "gdb": ["riscv64-unknown-elf-gdb"] } diff --git a/targets/rp2040.json b/targets/rp2040.json index 3f9fea45..fe356383 100644 --- a/targets/rp2040.json +++ b/targets/rp2040.json @@ -11,7 +11,7 @@ "uf2-family-id": "0xe48bff56", "rp2040-boot-patch": true, "extra-files": [ - "src/device/rp/rp2040.s" + "targets/device/rp/rp2040.s" ], "ldflags": [ "--defsym=__num_stacks=2" diff --git a/targets/rp2350.json b/targets/rp2350.json index 0487aa14..35778220 100644 --- a/targets/rp2350.json +++ b/targets/rp2350.json @@ -9,7 +9,7 @@ "binary-format": "uf2", "uf2-family-id": "0xe48bff59","comment":"See page 393 of RP2350 datasheet: RP2350 Arm Secure image (i.e. one intended to be booted directly by the bootrom)", "extra-files": [ - "src/device/rp/rp2350.s", + "targets/device/rp/rp2350.s", "targets/rp2350_embedded_block.s" ], "ldflags": [ diff --git a/targets/runtime_nintendoswitch.S b/targets/runtime_nintendoswitch.S new file mode 100644 index 00000000..a4cac23e --- /dev/null +++ b/targets/runtime_nintendoswitch.S @@ -0,0 +1,40 @@ +// Macro for writing less code +.macro FUNC name + .section .text.\name, "ax", %progbits + .global \name + .type \name, %function + .align 2 +\name: +.endm + +FUNC armGetSystemTick + mrs x0, cntpct_el0 + ret + +// Horizon System Calls +// https://switchbrew.org/wiki/SVC +FUNC svcSetHeapSize + str x0, [sp, #-16]! + svc 0x1 + ldr x2, [sp], #16 + str x1, [x2] + ret + +FUNC svcExitProcess + svc 0x7 + ret + +FUNC svcSleepThread + svc 0xB + ret + +FUNC svcOutputDebugString + svc 0x27 + ret + +FUNC svcGetInfo + str x0, [sp, #-16]! + svc 0x29 + ldr x2, [sp], #16 + str x1, [x2] + ret diff --git a/targets/stm32f469disco.json b/targets/stm32f469disco.json index 37deaa3a..90dd865f 100644 --- a/targets/stm32f469disco.json +++ b/targets/stm32f469disco.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32f469.ld", "extra-files": [ - "src/device/stm32/stm32f469.s" + "targets/device/stm32/stm32f469.s" ], "flash-method": "openocd", "openocd-interface": "stlink", diff --git a/targets/stm32f4disco.json b/targets/stm32f4disco.json index 4485c41d..f60b964e 100644 --- a/targets/stm32f4disco.json +++ b/targets/stm32f4disco.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32f407.ld", "extra-files": [ - "src/device/stm32/stm32f407.s" + "targets/device/stm32/stm32f407.s" ], "flash-method": "openocd", "openocd-interface": "stlink-v2", diff --git a/targets/stm32l0x2.json b/targets/stm32l0x2.json index 13b42cc5..846c1038 100644 --- a/targets/stm32l0x2.json +++ b/targets/stm32l0x2.json @@ -8,6 +8,6 @@ "stm32" ], "extra-files": [ - "src/device/stm32/stm32l0x2.s" + "targets/device/stm32/stm32l0x2.s" ] } \ No newline at end of file diff --git a/targets/stm32wl5x_cm4.json b/targets/stm32wl5x_cm4.json index 00d8bbb8..085cc431 100644 --- a/targets/stm32wl5x_cm4.json +++ b/targets/stm32wl5x_cm4.json @@ -2,7 +2,7 @@ "inherits": ["cortex-m4"], "build-tags": [ "stm32wl5x_cm4","stm32wlx", "stm32"], "extra-files": [ - "src/device/stm32/stm32wl5x_cm4.s" + "targets/device/stm32/stm32wl5x_cm4.s" ], "linkerscript": "targets/stm32wlx.ld" } diff --git a/targets/stm32wle5.json b/targets/stm32wle5.json index f24f28f2..96f2f5bf 100644 --- a/targets/stm32wle5.json +++ b/targets/stm32wle5.json @@ -2,7 +2,7 @@ "inherits": ["cortex-m4"], "build-tags": [ "stm32wle5","stm32wlx", "stm32"], "extra-files": [ - "src/device/stm32/stm32wle5.s" + "targets/device/stm32/stm32wle5.s" ], "linkerscript": "targets/stm32wlx.ld" } diff --git a/targets/swan.json b/targets/swan.json index fbb46a55..1615e4c0 100644 --- a/targets/swan.json +++ b/targets/swan.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/stm32l4x5.ld", "extra-files": [ - "src/device/stm32/stm32l4x5.s" + "targets/device/stm32/stm32l4x5.s" ], "flash-method": "command", "flash-command": "dfu-util --alt 0 --dfuse-address 0x08000000 --download {bin}", diff --git a/targets/teensy36.json b/targets/teensy36.json index 253e3970..76bce93c 100644 --- a/targets/teensy36.json +++ b/targets/teensy36.json @@ -4,7 +4,7 @@ "serial": "uart", "linkerscript": "targets/nxpmk66f18.ld", "extra-files": [ - "src/device/nxp/mk66f18.s", + "targets/device/nxp/mk66f18.s", "targets/teensy36.s" ], "flash-command": "teensy_loader_cli -mmcu=mk66fx1m0 -v -w {hex}" diff --git a/targets/teensy40.json b/targets/teensy40.json index 223db6f6..029d92ef 100644 --- a/targets/teensy40.json +++ b/targets/teensy40.json @@ -5,7 +5,7 @@ "automatic-stack-size": false, "linkerscript": "targets/mimxrt1062-teensy40.ld", "extra-files": [ - "src/device/nxp/mimxrt1062.s", + "targets/device/nxp/mimxrt1062.s", "targets/teensy40.s" ], "flash-command": "teensy_loader_cli -mmcu=imxrt1062 -v -w {hex}" diff --git a/targets/teensy41.json b/targets/teensy41.json index 8866bc48..a2f4ee4e 100644 --- a/targets/teensy41.json +++ b/targets/teensy41.json @@ -5,7 +5,7 @@ "automatic-stack-size": false, "linkerscript": "targets/mimxrt1062-teensy40.ld", "extra-files": [ - "src/device/nxp/mimxrt1062.s", + "targets/device/nxp/mimxrt1062.s", "targets/teensy40.s" ], "flash-command": "teensy_loader_cli -mmcu=imxrt1062 -v -w {hex}" diff --git a/targets/wasip1.json b/targets/wasip1.json index 8abc65e1..b916de04 100644 --- a/targets/wasip1.json +++ b/targets/wasip1.json @@ -22,9 +22,5 @@ "--stack-first", "--no-demangle" ], - "extra-files": [ - "src/runtime/asm_tinygowasm.S", - "src/runtime/gc_boehm.c" - ], "emulator": "wasmtime run --dir={tmpDir}::/tmp {}" } diff --git a/targets/wasip2.json b/targets/wasip2.json index 66e79eda..1b30db93 100644 --- a/targets/wasip2.json +++ b/targets/wasip2.json @@ -24,9 +24,6 @@ "--no-demangle", "--no-entry" ], - "extra-files": [ - "src/runtime/asm_tinygowasm.S" - ], "emulator": "wasmtime run --wasm component-model -Sinherit-network -Sallow-ip-name-lookup --dir={tmpDir}::/tmp {}", "wit-package": "{root}/lib/wasi-cli/wit/", "wit-world": "wasi:cli/command" diff --git a/targets/wasm-unknown.json b/targets/wasm-unknown.json index d64fa575..a667a413 100644 --- a/targets/wasm-unknown.json +++ b/targets/wasm-unknown.json @@ -23,8 +23,5 @@ "--no-demangle", "--no-entry" ], - "extra-files": [ - "src/runtime/asm_tinygowasm.S" - ], "emulator": "wasmtime run --dir={tmpDir}::/tmp {}" } diff --git a/targets/wasm.json b/targets/wasm.json index a8641636..c61b607d 100644 --- a/targets/wasm.json +++ b/targets/wasm.json @@ -23,9 +23,5 @@ "--stack-first", "--no-demangle" ], - "extra-files": [ - "src/runtime/asm_tinygowasm.S", - "src/runtime/gc_boehm.c" - ], "emulator": "node {root}/targets/wasm_exec.js {}" }