feat: support riscv32

internal/crosscompile/compile/rtlib/compiler_rt.go

@@ -3,10 +3,33 @@ package rtlib
 import (
 	"fmt"
 	"path/filepath"
+	"strings"
 
 	"github.com/goplus/llgo/internal/crosscompile/compile"
 )
 
+func platformSpecifiedFiles(builtinsDir, target string) []string {
+	switch {
+	case strings.Contains(target, "riscv32"):
+		return []string{
+			filepath.Join(builtinsDir, "riscv", "mulsi3.S"),
+			filepath.Join(builtinsDir, "riscv", "fp_mode.c"),
+			filepath.Join(builtinsDir, "riscv", "save.S"),
+			filepath.Join(builtinsDir, "riscv", "restore.S"),
+		}
+	case target == "xtensa":
+		return []string{
+			filepath.Join(builtinsDir, "xtensa", "ieee754_sqrtf.S"),
+		}
+	}
+	return nil
+}
+
+func withPlatformSpecifiedFiles(baseDir, target string, files []string) []string {
+	builtinsDir := filepath.Join(baseDir, "lib", "builtins")
+	return append(files, platformSpecifiedFiles(builtinsDir, target)...)
+}
+
 func GetCompilerRTConfig(baseDir, target string) *compile.CompileConfig {
 	return &compile.CompileConfig{
 		Url:           "https://github.com/goplus/compiler-rt/archive/refs/tags/v0.1.0.tar.gz",
@@ -14,8 +37,7 @@ func GetCompilerRTConfig(baseDir, target string) *compile.CompileConfig {
 		Groups: []compile.CompileGroup{
 			{
 				OutputFileName: fmt.Sprintf("libclang_builtins-%s.a", target),
-				Files: []string{
+				Files: withPlatformSpecifiedFiles(baseDir, target, []string{
-					filepath.Join(baseDir, "lib", "builtins", "xtensa/ieee754_sqrtf.S"),
 					filepath.Join(baseDir, "lib", "builtins", "absvdi2.c"),
 					filepath.Join(baseDir, "lib", "builtins", "absvsi2.c"),
 					filepath.Join(baseDir, "lib", "builtins", "absvti2.c"),
@@ -163,7 +185,8 @@ func GetCompilerRTConfig(baseDir, target string) *compile.CompileConfig {
 					filepath.Join(baseDir, "lib", "builtins", "trunctfdf2.c"),
 					filepath.Join(baseDir, "lib", "builtins", "trunctfhf2.c"),
 					filepath.Join(baseDir, "lib", "builtins", "trunctfsf2.c"),
-				},
+					filepath.Join(baseDir, "lib", "builtins", "atomic.c"),
+				}),
 				CFlags: []string{
 					"-DNDEBUG",
 					"-DVISIBILITY_HIDDEN",

internal/crosscompile/crosscompile.go

@@ -317,12 +317,12 @@ func use(goos, goarch string, wasiThreads bool) (export Export, err error) {
 			export.CCFLAGS = append(
 				export.CCFLAGS,
 				"-fdata-sections",
-				"-ffunction-sections",
+				// "-ffunction-sections",
 			)
 			export.LDFLAGS = append(
 				export.LDFLAGS,
 				"-fdata-sections",
-				"-ffunction-sections",
+				// "-ffunction-sections",
 				"-Xlinker",
 				"--gc-sections",
 				"-lm",
@@ -612,7 +612,7 @@ func useTarget(targetName string) (export Export, err error) {
 		baseDir := filepath.Join(cacheRoot(), "crosscompile")
 		outputDir := filepath.Join(baseDir, config.Libc)
 
-		compileConfig, err = getLibcCompileConfigByName(baseDir, config.Libc, config.LLVMTarget)
+		compileConfig, err = getLibcCompileConfigByName(baseDir, config.Libc, config.LLVMTarget, config.CPU)
 		if err != nil {
 			return
 		}

internal/crosscompile/libc.go

@@ -11,7 +11,7 @@ import (
 
 // GetCompileConfigByName retrieves libc compilation configuration by name
 // Returns compilation file lists and corresponding cflags
-func getLibcCompileConfigByName(baseDir, libcName, target string) (*compile.CompileConfig, error) {
+func getLibcCompileConfigByName(baseDir, libcName, target, mcpu string) (*compile.CompileConfig, error) {
 	if libcName == "" {
 		return nil, fmt.Errorf("libc name cannot be empty")
 	}
@@ -21,7 +21,7 @@ func getLibcCompileConfigByName(baseDir, libcName, target string) (*compile.Comp
 	case "picolibc":
 		return libc.GetPicolibcConfig(libcDir, target), nil
 	case "newlib-esp32":
-		return libc.GetNewlibESP32Config(libcDir, target), nil
+		return libc.GetNewlibESP32Config(libcDir, target, mcpu), nil
 	default:
 		return nil, fmt.Errorf("unsupported libc: %s", libcName)
 	}

targets/esp32-riscv.app.elf.ld

@@ -0,0 +1,195 @@
+__stack = ORIGIN(dram_seg) + LENGTH(dram_seg);
+__MIN_STACK_SIZE = 0x1000;
+_stack_top = __stack;
+
+/* Default entry point */
+ENTRY(_start)
+SECTIONS
+{
+  .text    :
+  {
+    _iram_start = .;
+
+    /* Place the _start function at the beginning of IRAM.
+     * Just in case some versions of QEMU ignore the entry address when loading the ELF file. */
+    KEEP(*(.text._start))
+
+    KEEP (*(SORT_NONE(.init)))
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    KEEP (*(SORT_NONE(.fini)))
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+  } > iram_seg
+
+  .rodata    :
+  {
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+    . = ALIGN(4);
+    __cpu_frequency = .;
+    LONG(CPU_FREQUENCY);
+    __uart0_clkdiv_reg = .;
+    LONG(UART0_CLKDIV_REG);
+    __uart0_clkdiv_val = .;
+    LONG(UART0_CLKDIV_VAL);
+    __uart0_tx_addr = .;
+    LONG(UART0_TX_ADDR);
+    __uart0_status = .;
+    LONG(UART0_STATUS);
+  } > iram_seg
+
+  .preinit_array    :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > iram_seg
+  .init_array    :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > iram_seg
+  .fini_array    :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > iram_seg
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } > iram_seg
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    _iram_end = .;
+  } > iram_seg
+
+  /**
+   * This section is required to skip .iram0.text area because iram0_0_seg and
+   * dram0_0_seg reflect the same address space on different buses.
+   */
+  .dram0.dummy (NOLOAD):
+  {
+    /* Add a gap only in case we have separate iram/dram regions */
+    . += ORIGIN(iram_seg) == ORIGIN(dram_seg) ? 0 : _iram_end - _iram_start;
+  } > dram_seg
+
+  .data          :
+  {
+    _data_start = .;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
+  } > dram_seg
+  .data1          : { *(.data1) } > dram_seg
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata     :
+  {
+    PROVIDE(__global_pointer$ = . + 0x800);
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+    _edata = .; PROVIDE (edata = .);
+    . = .;
+  } > dram_seg
+
+  .eh_frame_hdr   : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } > dram_seg
+  .eh_frame       : { KEEP (*(.eh_frame)) *(.eh_frame.*) } > dram_seg
+
+  .bss    (NOLOAD)  :
+  {
+    __bss_start = .;
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.
+      FIXME: Why do we need it? When there is no .bss section, we do not
+      pad the .data section.  */
+    . = ALIGN(. != 0 ? 32 / 8 : 1);
+
+    . = ALIGN(32 / 8);
+    . = ALIGN(32 / 8);
+    _end = .; PROVIDE (end = .);
+  } > dram_seg
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(_end <= __stack - __MIN_STACK_SIZE, "region DRAM overflowed by .data and .bss sections")
+
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* DWARF 3 */
+  .debug_pubtypes 0 : { *(.debug_pubtypes) }
+  .debug_ranges   0 : { *(.debug_ranges) }
+  /* DWARF Extension.  */
+  .debug_macro    0 : { *(.debug_macro) }
+  .debug_addr     0 : { *(.debug_addr) }
+  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}

targets/esp32c2.memory.ld

@@ -0,0 +1,33 @@
+# See "System Structure and Address Mapping" figure at
+# https://www.espressif.com/sites/default/files/documentation/esp8684_technical_reference_manual_en.pdf
+
+ICACHE_SIZE = 0x4000;
+# Skip possible ICACHE area
+IRAM_START_ADDRESS = 0x4037C000 + ICACHE_SIZE;
+IRAM_LEN = 0x40000 - ICACHE_SIZE;
+
+DRAM_START_ADDRESS = 0x3FCA0000;
+DRAM_LEN = 0x40000;
+
+# Docs say that:
+# The default console baud rate on ESP32-C2:
+#  - 115200 when a 40 MHz XTAL is used
+#  - 74880 when a 26 MHz XTAL is used
+#
+# It seems something wrong with CPU_FREQUENCY and UART0_BAUD definitions,
+# but UART0_CLKDIV_VAL == 173 gives expected baud rate 74880 on 26 MHz XTAL.
+CPU_FREQUENCY = 20000000;
+UART0_BAUD = 115200;
+
+UART0_CLKDIV_REG = 0x60000014;
+UART0_CLKDIV_VAL = CPU_FREQUENCY / UART0_BAUD;
+UART0_STATUS = 0x6000001C;
+UART0_TX_ADDR = 0x60000000;
+
+MEMORY
+{
+  iram_seg  (RX) : org = IRAM_START_ADDRESS, len = IRAM_LEN
+  dram_seg  (RW) : org = DRAM_START_ADDRESS, len = DRAM_LEN
+}
+
+INCLUDE "targets/esp32-riscv.app.elf.ld";

targets/esp32c3.json

@@ -1,23 +1,31 @@
 {
-	"inherits": ["riscv32"],
+	"inherits": [
+		"riscv32"
+	],
 	"features": "+32bit,+c,+m,+zmmul,-a,-b,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-f,-h,-relax,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xesppie,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b",
-	"build-tags": ["esp32c3", "esp"],
+	"build-tags": [
+		"esp32c3",
+		"esp"
+	],
 	"serial": "usb",
 	"rtlib": "compiler-rt",
-	"libc": "picolibc",
+	"libc": "newlib-esp32",
 	"cflags": [
 		"-march=rv32imc"
 	],
-	"linkerscript": "targets/esp32c3.ld",
+	"linkerscript": "targets/esp32c3.memory.ld",
-	"extra-files": [
+	"extra-files": [],
-		"targets/device/esp/esp32c3.S"
-	],
 	"binary-format": "esp32c3",
 	"flash-command": "esptool.py --chip=esp32c3 --port {port} write_flash 0x0 {bin}",
-	"serial-port": ["303a:1001"],
+	"serial-port": [
+		"303a:1001"
+	],
 	"openocd-interface": "esp_usb_jtag",
 	"openocd-target": "esp32c3",
- 	"openocd-commands": ["gdb_memory_map disable"],
+	"openocd-commands": [
- 	"gdb": ["riscv32-esp-elf-gdb"]
+		"gdb_memory_map disable"
+	],
+	"gdb": [
+		"riscv32-esp-elf-gdb"
+	]
 }
-

targets/esp32c3.memory.ld

@@ -0,0 +1,26 @@
+# See "System Structure and Address Mapping" figure at
+# https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
+
+ICACHE_SIZE = 0x4000;
+# Skip possible ICACHE area
+IRAM_START_ADDRESS = 0x4037C000 + ICACHE_SIZE;
+IRAM_LEN = 0x64000 - ICACHE_SIZE;
+
+DRAM_START_ADDRESS = 0x3FC80000;
+DRAM_LEN = 0x40000;
+
+CPU_FREQUENCY = 20000000;
+UART0_BAUD = 115200;
+
+UART0_CLKDIV_REG = 0x60000014;
+UART0_CLKDIV_VAL = CPU_FREQUENCY / UART0_BAUD;
+UART0_STATUS = 0x6000001C;
+UART0_TX_ADDR = 0x60000000;
+
+MEMORY
+{
+  iram_seg  (RX) : org = IRAM_START_ADDRESS, len = IRAM_LEN
+  dram_seg  (RW) : org = DRAM_START_ADDRESS, len = DRAM_LEN
+}
+
+INCLUDE "targets/esp32-riscv.app.elf.ld";

targets/esp32c5.memory.ld

@@ -0,0 +1,22 @@
+# Memory layout obtained from IDF linker files.
+
+SRAM_START_ADDRESS = 0x40800000;
+SRAM_LEN = 0x60000;
+
+CPU_FREQUENCY = 40000000;
+UART0_BAUD = 115200;
+
+UART0_CLKDIV_REG = 0x60000014;
+UART0_CLKDIV_VAL = CPU_FREQUENCY / UART0_BAUD;
+UART0_STATUS = 0x6000001C;
+UART0_TX_ADDR = 0x60000000;
+
+MEMORY
+{
+  sram_seg  (RWX) : org = SRAM_START_ADDRESS, len = SRAM_LEN
+}
+
+REGION_ALIAS("iram_seg", sram_seg);
+REGION_ALIAS("dram_seg", sram_seg);
+
+INCLUDE "targets/esp32-riscv.app.elf.ld";

targets/esp32c6.memory.ld

@@ -0,0 +1,22 @@
+# See "System Structure and Address Mapping" figure at
+# https://www.espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf
+
+SRAM_START_ADDRESS = 0x40800000;
+SRAM_LEN = 0x80000;
+
+CPU_FREQUENCY = 40000000;
+UART0_BAUD = 115200;
+
+UART0_CLKDIV_REG = 0x60000014;
+UART0_CLKDIV_VAL = CPU_FREQUENCY / UART0_BAUD;
+UART0_STATUS = 0x6000001C;
+UART0_TX_ADDR = 0x60000000;
+
+MEMORY
+{
+  sram_seg  (RWX) : org = SRAM_START_ADDRESS, len = SRAM_LEN
+}
+
+REGION_ALIAS("iram_seg", sram_seg);
+REGION_ALIAS("dram_seg", sram_seg);
+INCLUDE "targets/esp32-riscv.app.elf.ld";

targets/esp32c61.memory.ld

@@ -0,0 +1,21 @@
+# Memory layout obtained from IDF linker files.
+
+SRAM_START_ADDRESS = 0x40800000;
+SRAM_LEN = 0x50000;
+
+CPU_FREQUENCY = 40000000;
+UART0_BAUD = 115200;
+
+UART0_CLKDIV_REG = 0x60000014;
+UART0_CLKDIV_VAL = CPU_FREQUENCY / UART0_BAUD;
+UART0_STATUS = 0x6000001C;
+UART0_TX_ADDR = 0x60000000;
+
+MEMORY
+{
+  sram_seg  (RWX) : org = SRAM_START_ADDRESS, len = SRAM_LEN
+}
+
+REGION_ALIAS("iram_seg", sram_seg);
+REGION_ALIAS("dram_seg", sram_seg);
+INCLUDE "targets/esp32-riscv.app.elf.ld";

targets/esp32h2.memory.ld

@@ -0,0 +1,22 @@
+# See "System Structure and Address Mapping" figure at
+# https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
+
+SRAM_START_ADDRESS = 0x40800000;
+SRAM_LEN = 0x50000;
+
+CPU_FREQUENCY = 40000000;
+UART0_BAUD = 115200;
+
+UART0_CLKDIV_REG = 0x60000014;
+UART0_CLKDIV_VAL = CPU_FREQUENCY / UART0_BAUD;
+UART0_STATUS = 0x6000001C;
+UART0_TX_ADDR = 0x60000000;
+
+MEMORY
+{
+  sram_seg  (RWX) : org = SRAM_START_ADDRESS, len = SRAM_LEN
+}
+
+REGION_ALIAS("iram_seg", sram_seg);
+REGION_ALIAS("dram_seg", sram_seg);
+INCLUDE "targets/esp32-riscv.app.elf.ld";

targets/esp32h21.memory.ld

@@ -0,0 +1,21 @@
+# Memory layout obtained from IDF linker files.
+
+SRAM_START_ADDRESS = 0x40800000;
+SRAM_LEN = 0x50000;
+
+CPU_FREQUENCY = 40000000;
+UART0_BAUD = 115200;
+
+UART0_CLKDIV_REG = 0x60000014;
+UART0_CLKDIV_VAL = CPU_FREQUENCY / UART0_BAUD;
+UART0_STATUS = 0x6000001C;
+UART0_TX_ADDR = 0x60000000;
+
+MEMORY
+{
+  sram_seg  (RWX) : org = SRAM_START_ADDRESS, len = SRAM_LEN
+}
+
+REGION_ALIAS("iram_seg", sram_seg);
+REGION_ALIAS("dram_seg", sram_seg);
+INCLUDE "targets/esp32-riscv.app.elf.ld";

targets/esp32p4.memory.ld

@@ -0,0 +1,23 @@
+# Memory layout obtained from IDF linker files.
+
+L2_CACHE_SIZE = 0x40000;
+
+SRAM_START_ADDRESS = 0x4FF00000;
+SRAM_LEN = 0xC0000 - L2_CACHE_SIZE;
+
+CPU_FREQUENCY = 40000000;
+UART0_BAUD = 115200;
+
+UART0_CLKDIV_REG = 0x500CA014;
+UART0_CLKDIV_VAL = CPU_FREQUENCY / UART0_BAUD;
+UART0_STATUS = 0x500CA01C;
+UART0_TX_ADDR = 0x500CA000;
+
+MEMORY
+{
+  sram_seg  (RWX) : org = SRAM_START_ADDRESS, len = SRAM_LEN
+}
+
+REGION_ALIAS("iram_seg", sram_seg);
+REGION_ALIAS("dram_seg", sram_seg);
+INCLUDE "targets/esp32-riscv.app.elf.ld";

targets/xtensa.json

@@ -2,15 +2,23 @@
 	"llvm-target": "xtensa",
 	"goos": "linux",
 	"goarch": "arm",
-	"build-tags": ["xtensa", "baremetal", "linux", "arm"],
+	"build-tags": [
+		"xtensa",
+		"baremetal",
+		"linux",
+		"arm"
+	],
 	"gc": "conservative",
 	"scheduler": "none",
 	"cflags": [
 		"-Werror",
 		"-fshort-enums",
 		"-Wno-macro-redefined",
-		"-fno-exceptions", "-fno-unwind-tables", "-fno-asynchronous-unwind-tables",
+		"-fno-exceptions",
-		"-ffunction-sections", "-fdata-sections"
+		"-fno-unwind-tables",
+		"-fno-asynchronous-unwind-tables",
+		"-ffunction-sections",
+		"-fdata-sections"
 	],
 	"ldflags": [
 		"--gc-sections"