From b80a54eb0fc9f9bb1ed3ca7a7367986ab9b8c71a Mon Sep 17 00:00:00 2001 From: Li Jie Date: Sat, 26 Jul 2025 10:49:35 +1000 Subject: [PATCH 1/9] feat: implement target configuration system for issue #1176 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add comprehensive target configuration parsing and inheritance system: - Create internal/targets package with config structures - Support JSON configuration loading with inheritance resolution - Implement multi-level inheritance (e.g., rp2040 → cortex-m0plus → cortex-m) - Add 206 target configurations from TinyGo for embedded platforms - Support core fields: name, llvm-target, cpu, features, build-tags, goos, goarch, cflags, ldflags - Provide high-level resolver interface for target lookup - Include comprehensive unit tests with 100% target parsing coverage This foundation enables future -target parameter support for cross-compilation to diverse embedded platforms beyond current GOOS/GOARCH limitations. 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude --- internal/targets/config.go | 43 + internal/targets/example_test.go | 73 + internal/targets/loader.go | 176 ++ internal/targets/resolver.go | 77 + internal/targets/targets_test.go | 322 ++++ targets/adafruit-esp32-feather-v2.json | 4 + targets/ae-rp2040.json | 14 + targets/arduino-leonardo.json | 10 + targets/arduino-mega1280.json | 8 + targets/arduino-mega2560.json | 8 + targets/arduino-mkr1000.json | 7 + targets/arduino-mkrwifi1010.json | 8 + targets/arduino-nano-new.json | 4 + targets/arduino-nano.json | 10 + targets/arduino-nano33.json | 7 + targets/arduino-zero.json | 7 + targets/arduino.json | 11 + targets/arm.ld | 86 + targets/atmega1280.json | 14 + targets/atmega1284p.json | 16 + targets/atmega2560.json | 14 + targets/atmega328p.json | 11 + targets/atmega328pb.json | 15 + targets/atmega32u4.json | 11 + targets/atsamd21.ld | 10 + targets/atsamd21e18a.json | 11 + targets/atsamd21g18a.json | 11 + targets/atsamd51.ld | 10 + targets/atsamd51g19a.json | 10 + targets/atsamd51j19a.json | 10 + targets/atsamd51j20a.json | 10 + targets/atsamd51j20a.ld | 10 + targets/atsamd51p19a.json | 10 + targets/atsamd51p20a.json | 10 + targets/atsamd51p20a.ld | 10 + targets/atsame51j19a.json | 10 + targets/atsame54-xpro.json | 7 + targets/atsame54p20a.json | 10 + targets/atsame5xx19.ld | 10 + targets/atsame5xx20-no-bootloader.ld | 10 + targets/attiny1616.json | 14 + targets/attiny85.json | 13 + targets/avr.S | 84 + targets/avr.json | 24 + targets/avr.ld | 56 + targets/avrtiny.S | 43 + targets/avrtiny.json | 25 + targets/avrtiny.ld | 58 + targets/badger2040-w.json | 13 + targets/badger2040.json | 13 + targets/bluemicro840.json | 6 + targets/bluepill-clone.json | 4 + targets/bluepill.json | 12 + targets/btt-skr-pico.json | 13 + targets/challenger-rp2040.json | 13 + targets/circuitplay-bluefruit.json | 6 + targets/circuitplay-express.json | 9 + targets/clue-alpha.json | 6 + targets/clue.json | 3 + targets/cortex-m-qemu.json | 10 + targets/cortex-m-qemu.s | 59 + targets/cortex-m.json | 30 + targets/cortex-m0.json | 6 + targets/cortex-m0plus.json | 6 + targets/cortex-m3.json | 6 + targets/cortex-m33.json | 6 + targets/cortex-m4.json | 6 + targets/cortex-m7.json | 6 + targets/d1mini.json | 3 + targets/digispark.json | 10 + targets/elecrow-rp2040.json | 12 + targets/elecrow-rp2350.json | 12 + targets/esp-c3-32s-kit.json | 5 + targets/esp32-c3-devkit-rust-1.json | 4 + targets/esp32-coreboard-v2.json | 4 + targets/esp32-mini32.json | 3 + targets/esp32.json | 21 + targets/esp32.ld | 202 ++ targets/esp32c3-12f.json | 5 + targets/esp32c3-supermini.json | 4 + targets/esp32c3.json | 23 + targets/esp32c3.ld | 2238 ++++++++++++++++++++++ targets/esp8266.json | 18 + targets/esp8266.ld | 109 ++ targets/fe310.json | 6 + targets/feather-m0-express.json | 10 + targets/feather-m0.json | 10 + targets/feather-m4-can.json | 10 + targets/feather-m4.json | 10 + targets/feather-nrf52840-sense.json | 6 + targets/feather-nrf52840.json | 6 + targets/feather-rp2040-boot-stage2.S | 17 + targets/feather-rp2040.json | 13 + targets/feather-stm32f405.json | 15 + targets/gameboy-advance.json | 28 + targets/gameboy-advance.ld | 84 + targets/gameboy-advance.s | 77 + targets/gemma-m0.json | 10 + targets/gnse.json | 12 + targets/gobadge.json | 3 + targets/gopher-badge.json | 13 + targets/gopherbot.json | 3 + targets/gopherbot2.json | 3 + targets/grandcentral-m4.json | 11 + targets/hifive1b.json | 10 + targets/hifive1b.ld | 10 + targets/hw-651-s110v8.json | 3 + targets/hw-651.json | 7 + targets/itsybitsy-m0.json | 10 + targets/itsybitsy-m4.json | 10 + targets/itsybitsy-nrf52840.json | 6 + targets/k210.json | 6 + targets/kb2040.json | 13 + targets/lgt92.json | 13 + targets/lm3s6965.ld | 10 + targets/lorae5.json | 12 + targets/m5paper.json | 5 + targets/m5stack-core2.json | 5 + targets/m5stack.json | 5 + targets/m5stamp-c3.json | 7 + targets/m5stick-c.json | 5 + targets/macropad-rp2040-boot-stage2.S | 17 + targets/macropad-rp2040.json | 13 + targets/maixbit.json | 7 + targets/maixbit.ld | 65 + targets/makerfabs-esp32c3spi35.json | 4 + targets/matrixportal-m4.json | 13 + targets/mch2022.json | 4 + targets/mdbt50qrx-uf2.json | 6 + targets/metro-m4-airlift.json | 10 + targets/microbit-s110v8.json | 4 + targets/microbit-v2-s113v7.json | 4 + targets/microbit-v2-s140v7.json | 4 + targets/microbit-v2.json | 9 + targets/microbit.json | 9 + targets/mimxrt1062-teensy40.ld | 107 ++ targets/mksnanov3.json | 13 + targets/nano-33-ble-s140v6-uf2.json | 6 + targets/nano-33-ble-s140v7-uf2.json | 6 + targets/nano-33-ble-s140v7.json | 6 + targets/nano-33-ble.json | 9 + targets/nano-33-ble.ld | 14 + targets/nano-rp2040.json | 13 + targets/nicenano.json | 5 + targets/nintendoswitch.json | 35 + targets/nintendoswitch.ld | 85 + targets/nintendoswitch.s | 126 ++ targets/nodemcu.json | 5 + targets/nrf51-s110v8.json | 4 + targets/nrf51-s110v8.ld | 12 + targets/nrf51.json | 16 + targets/nrf51.ld | 10 + targets/nrf52-s132v6.json | 4 + targets/nrf52-s132v6.ld | 13 + targets/nrf52.json | 16 + targets/nrf52.ld | 10 + targets/nrf52833-s113v7.json | 7 + targets/nrf52833-s113v7.ld | 14 + targets/nrf52833-s140v7.json | 7 + targets/nrf52833-s140v7.ld | 14 + targets/nrf52833.json | 16 + targets/nrf52833.ld | 10 + targets/nrf52840-mdk-usb-dongle.json | 5 + targets/nrf52840-mdk.json | 7 + targets/nrf52840-s140v6-uf2-generic.json | 5 + targets/nrf52840-s140v6-uf2.json | 10 + targets/nrf52840-s140v6-uf2.ld | 13 + targets/nrf52840-s140v7-uf2.json | 11 + targets/nrf52840-s140v7-uf2.ld | 17 + targets/nrf52840-s140v7.json | 7 + targets/nrf52840-s140v7.ld | 14 + targets/nrf52840.json | 16 + targets/nrf52840.ld | 10 + targets/nucleo-f103rb.json | 12 + targets/nucleo-f722ze.json | 12 + targets/nucleo-l031k6.json | 12 + targets/nucleo-l432kc.json | 12 + targets/nucleo-l476rg.json | 12 + targets/nucleo-l552ze.json | 12 + targets/nucleo-wl55jc.json | 12 + targets/nxpmk66f18.ld | 38 + targets/p1am-100.json | 6 + targets/particle-3rd-gen.json | 7 + targets/particle-argon.json | 4 + targets/particle-boron.json | 4 + targets/particle-xenon.json | 4 + targets/pca10031.json | 7 + targets/pca10040-s132v6.json | 3 + targets/pca10040.json | 9 + targets/pca10056-s140v6-uf2.json | 6 + targets/pca10056-s140v7.json | 3 + targets/pca10056.json | 11 + targets/pca10059-s140v7.json | 3 + targets/pca10059.json | 8 + targets/pca10059.ld | 10 + targets/pga2350.json | 7 + targets/pico-boot-stage2.S | 17 + targets/pico-plus2.json | 11 + targets/pico-w.json | 4 + targets/pico.json | 14 + targets/pico2-w.json | 4 + targets/pico2.json | 11 + targets/pinetime.json | 9 + targets/pybadge.json | 10 + targets/pygamer.json | 10 + targets/pyportal.json | 10 + targets/qtpy-esp32c3.json | 4 + targets/qtpy-rp2040-boot-stage2.S | 17 + targets/qtpy-rp2040.json | 13 + targets/qtpy.json | 10 + targets/rak4631.json | 6 + targets/reelboard-s140v7.json | 4 + targets/reelboard.json | 9 + targets/riscv-qemu.json | 21 + targets/riscv-qemu.ld | 16 + targets/riscv.json | 25 + targets/riscv.ld | 85 + targets/riscv32.json | 19 + targets/riscv64.json | 13 + targets/rp2040-boot-stage2.S | 471 +++++ targets/rp2040.json | 23 + targets/rp2040.ld | 36 + targets/rp2350.json | 22 + targets/rp2350.ld | 23 + targets/rp2350_embedded_block.s | 10 + targets/rp2350b.json | 5 + targets/simavr.json | 5 + targets/stm32.ld | 10 + targets/stm32f103rb.ld | 10 + targets/stm32f405.ld | 9 + targets/stm32f407.ld | 10 + targets/stm32f469.ld | 10 + targets/stm32f469disco.json | 12 + targets/stm32f4disco-1.json | 4 + targets/stm32f4disco.json | 12 + targets/stm32f7x2zetx.ld | 10 + targets/stm32l031k6.ld | 10 + targets/stm32l072czt6.ld | 10 + targets/stm32l0x2.json | 13 + targets/stm32l4x2.ld | 10 + targets/stm32l4x5.ld | 10 + targets/stm32l4x6.ld | 11 + targets/stm32l5x2xe.ld | 10 + targets/stm32wl5x_cm4.json | 8 + targets/stm32wle5.json | 8 + targets/stm32wlx.ld | 10 + targets/swan.json | 13 + targets/teensy36.json | 12 + targets/teensy36.s | 19 + targets/teensy40.json | 13 + targets/teensy40.s | 199 ++ targets/teensy41.json | 12 + targets/thingplus-rp2040.json | 13 + targets/thumby.json | 14 + targets/tiny2350.json | 10 + targets/tkey.json | 13 + targets/tkey.ld | 11 + targets/trinket-m0.json | 10 + targets/trinkey-qt2040-boot-stage2.S | 17 + targets/trinkey-qt2040.json | 13 + targets/tufty2040.json | 13 + targets/wasi.json | 3 + targets/wasip1.json | 30 + targets/wasip2.json | 33 + targets/wasm-undefined.txt | 16 + targets/wasm-unknown.json | 30 + targets/wasm.json | 31 + targets/wasm_exec.js | 553 ++++++ targets/waveshare-rp2040-tiny.json | 13 + targets/waveshare-rp2040-zero.json | 13 + targets/wioterminal.json | 11 + targets/x9pro.json | 9 + targets/xiao-ble.json | 6 + targets/xiao-esp32c3.json | 4 + targets/xiao-rp2040.json | 13 + targets/xiao.json | 10 + targets/xtensa.json | 18 + 277 files changed, 8202 insertions(+) create mode 100644 internal/targets/config.go create mode 100644 internal/targets/example_test.go create mode 100644 internal/targets/loader.go create mode 100644 internal/targets/resolver.go create mode 100644 internal/targets/targets_test.go create mode 100644 targets/adafruit-esp32-feather-v2.json create mode 100644 targets/ae-rp2040.json create mode 100644 targets/arduino-leonardo.json create mode 100644 targets/arduino-mega1280.json create mode 100644 targets/arduino-mega2560.json create mode 100644 targets/arduino-mkr1000.json create mode 100644 targets/arduino-mkrwifi1010.json create mode 100644 targets/arduino-nano-new.json create mode 100644 targets/arduino-nano.json create mode 100644 targets/arduino-nano33.json create mode 100644 targets/arduino-zero.json create mode 100644 targets/arduino.json create mode 100644 targets/arm.ld create mode 100644 targets/atmega1280.json create mode 100644 targets/atmega1284p.json create mode 100644 targets/atmega2560.json create mode 100644 targets/atmega328p.json create mode 100644 targets/atmega328pb.json create mode 100644 targets/atmega32u4.json create mode 100644 targets/atsamd21.ld create mode 100644 targets/atsamd21e18a.json create mode 100644 targets/atsamd21g18a.json create mode 100644 targets/atsamd51.ld create mode 100644 targets/atsamd51g19a.json create mode 100644 targets/atsamd51j19a.json create mode 100644 targets/atsamd51j20a.json create mode 100644 targets/atsamd51j20a.ld create mode 100644 targets/atsamd51p19a.json create mode 100644 targets/atsamd51p20a.json create mode 100644 targets/atsamd51p20a.ld create mode 100644 targets/atsame51j19a.json create mode 100644 targets/atsame54-xpro.json create mode 100644 targets/atsame54p20a.json create mode 100644 targets/atsame5xx19.ld create mode 100644 targets/atsame5xx20-no-bootloader.ld create mode 100644 targets/attiny1616.json create mode 100644 targets/attiny85.json create mode 100644 targets/avr.S create mode 100644 targets/avr.json create mode 100644 targets/avr.ld create mode 100644 targets/avrtiny.S create mode 100644 targets/avrtiny.json create mode 100644 targets/avrtiny.ld create mode 100644 targets/badger2040-w.json create mode 100644 targets/badger2040.json create mode 100644 targets/bluemicro840.json create mode 100644 targets/bluepill-clone.json create mode 100644 targets/bluepill.json create mode 100644 targets/btt-skr-pico.json create mode 100644 targets/challenger-rp2040.json create mode 100644 targets/circuitplay-bluefruit.json create mode 100644 targets/circuitplay-express.json create mode 100644 targets/clue-alpha.json create mode 100644 targets/clue.json create mode 100644 targets/cortex-m-qemu.json create mode 100644 targets/cortex-m-qemu.s create mode 100644 targets/cortex-m.json create mode 100644 targets/cortex-m0.json create mode 100644 targets/cortex-m0plus.json create mode 100644 targets/cortex-m3.json create mode 100644 targets/cortex-m33.json create mode 100644 targets/cortex-m4.json create mode 100644 targets/cortex-m7.json create mode 100644 targets/d1mini.json create mode 100644 targets/digispark.json create mode 100644 targets/elecrow-rp2040.json create mode 100644 targets/elecrow-rp2350.json create mode 100644 targets/esp-c3-32s-kit.json create mode 100644 targets/esp32-c3-devkit-rust-1.json create mode 100644 targets/esp32-coreboard-v2.json create mode 100644 targets/esp32-mini32.json create mode 100644 targets/esp32.json create mode 100644 targets/esp32.ld create mode 100644 targets/esp32c3-12f.json create mode 100644 targets/esp32c3-supermini.json create mode 100644 targets/esp32c3.json create mode 100644 targets/esp32c3.ld create mode 100644 targets/esp8266.json create mode 100644 targets/esp8266.ld create mode 100644 targets/fe310.json create mode 100644 targets/feather-m0-express.json create mode 100644 targets/feather-m0.json create mode 100644 targets/feather-m4-can.json create mode 100644 targets/feather-m4.json create mode 100644 targets/feather-nrf52840-sense.json create mode 100644 targets/feather-nrf52840.json create mode 100644 targets/feather-rp2040-boot-stage2.S create mode 100644 targets/feather-rp2040.json create mode 100644 targets/feather-stm32f405.json create mode 100644 targets/gameboy-advance.json create mode 100644 targets/gameboy-advance.ld create mode 100644 targets/gameboy-advance.s create mode 100644 targets/gemma-m0.json create mode 100644 targets/gnse.json create mode 100644 targets/gobadge.json create mode 100644 targets/gopher-badge.json create mode 100644 targets/gopherbot.json create mode 100644 targets/gopherbot2.json create mode 100644 targets/grandcentral-m4.json create mode 100644 targets/hifive1b.json create mode 100644 targets/hifive1b.ld create mode 100644 targets/hw-651-s110v8.json create mode 100644 targets/hw-651.json create mode 100644 targets/itsybitsy-m0.json create mode 100644 targets/itsybitsy-m4.json create mode 100644 targets/itsybitsy-nrf52840.json create mode 100644 targets/k210.json create mode 100644 targets/kb2040.json create mode 100644 targets/lgt92.json create mode 100644 targets/lm3s6965.ld create mode 100644 targets/lorae5.json create mode 100644 targets/m5paper.json create mode 100644 targets/m5stack-core2.json create mode 100644 targets/m5stack.json create mode 100644 targets/m5stamp-c3.json create mode 100644 targets/m5stick-c.json create mode 100644 targets/macropad-rp2040-boot-stage2.S create mode 100644 targets/macropad-rp2040.json create mode 100644 targets/maixbit.json create mode 100644 targets/maixbit.ld create mode 100644 targets/makerfabs-esp32c3spi35.json create mode 100644 targets/matrixportal-m4.json create mode 100644 targets/mch2022.json create mode 100644 targets/mdbt50qrx-uf2.json create mode 100644 targets/metro-m4-airlift.json create mode 100644 targets/microbit-s110v8.json create mode 100644 targets/microbit-v2-s113v7.json create mode 100644 targets/microbit-v2-s140v7.json create mode 100644 targets/microbit-v2.json create mode 100644 targets/microbit.json create mode 100644 targets/mimxrt1062-teensy40.ld create mode 100644 targets/mksnanov3.json create mode 100644 targets/nano-33-ble-s140v6-uf2.json create mode 100644 targets/nano-33-ble-s140v7-uf2.json create mode 100644 targets/nano-33-ble-s140v7.json create mode 100644 targets/nano-33-ble.json create mode 100644 targets/nano-33-ble.ld create mode 100644 targets/nano-rp2040.json create mode 100644 targets/nicenano.json create mode 100644 targets/nintendoswitch.json create mode 100644 targets/nintendoswitch.ld create mode 100644 targets/nintendoswitch.s create mode 100644 targets/nodemcu.json create mode 100644 targets/nrf51-s110v8.json create mode 100644 targets/nrf51-s110v8.ld create mode 100644 targets/nrf51.json create mode 100644 targets/nrf51.ld create mode 100644 targets/nrf52-s132v6.json create mode 100644 targets/nrf52-s132v6.ld create mode 100644 targets/nrf52.json create mode 100644 targets/nrf52.ld create mode 100644 targets/nrf52833-s113v7.json create mode 100644 targets/nrf52833-s113v7.ld create mode 100644 targets/nrf52833-s140v7.json create mode 100644 targets/nrf52833-s140v7.ld create mode 100644 targets/nrf52833.json create mode 100644 targets/nrf52833.ld create mode 100644 targets/nrf52840-mdk-usb-dongle.json create mode 100644 targets/nrf52840-mdk.json create mode 100644 targets/nrf52840-s140v6-uf2-generic.json create mode 100644 targets/nrf52840-s140v6-uf2.json create mode 100644 targets/nrf52840-s140v6-uf2.ld create mode 100644 targets/nrf52840-s140v7-uf2.json create mode 100644 targets/nrf52840-s140v7-uf2.ld create mode 100644 targets/nrf52840-s140v7.json create mode 100644 targets/nrf52840-s140v7.ld create mode 100644 targets/nrf52840.json create mode 100644 targets/nrf52840.ld create mode 100644 targets/nucleo-f103rb.json create mode 100644 targets/nucleo-f722ze.json create mode 100644 targets/nucleo-l031k6.json create mode 100644 targets/nucleo-l432kc.json create mode 100644 targets/nucleo-l476rg.json create mode 100644 targets/nucleo-l552ze.json create mode 100644 targets/nucleo-wl55jc.json create mode 100644 targets/nxpmk66f18.ld create mode 100644 targets/p1am-100.json create mode 100644 targets/particle-3rd-gen.json create mode 100644 targets/particle-argon.json create mode 100644 targets/particle-boron.json create mode 100644 targets/particle-xenon.json create mode 100644 targets/pca10031.json create mode 100644 targets/pca10040-s132v6.json create mode 100644 targets/pca10040.json create mode 100644 targets/pca10056-s140v6-uf2.json create mode 100644 targets/pca10056-s140v7.json create mode 100644 targets/pca10056.json create mode 100644 targets/pca10059-s140v7.json create mode 100644 targets/pca10059.json create mode 100644 targets/pca10059.ld create mode 100644 targets/pga2350.json create mode 100644 targets/pico-boot-stage2.S create mode 100644 targets/pico-plus2.json create mode 100644 targets/pico-w.json create mode 100644 targets/pico.json create mode 100644 targets/pico2-w.json create mode 100644 targets/pico2.json create mode 100644 targets/pinetime.json create mode 100644 targets/pybadge.json create mode 100644 targets/pygamer.json create mode 100644 targets/pyportal.json create mode 100644 targets/qtpy-esp32c3.json create mode 100644 targets/qtpy-rp2040-boot-stage2.S create mode 100644 targets/qtpy-rp2040.json create mode 100644 targets/qtpy.json create mode 100644 targets/rak4631.json create mode 100644 targets/reelboard-s140v7.json create mode 100644 targets/reelboard.json create mode 100644 targets/riscv-qemu.json create mode 100644 targets/riscv-qemu.ld create mode 100644 targets/riscv.json create mode 100644 targets/riscv.ld create mode 100644 targets/riscv32.json create mode 100644 targets/riscv64.json create mode 100644 targets/rp2040-boot-stage2.S create mode 100644 targets/rp2040.json create mode 100644 targets/rp2040.ld create mode 100644 targets/rp2350.json create mode 100644 targets/rp2350.ld create mode 100644 targets/rp2350_embedded_block.s create mode 100644 targets/rp2350b.json create mode 100644 targets/simavr.json create mode 100644 targets/stm32.ld create mode 100644 targets/stm32f103rb.ld create mode 100644 targets/stm32f405.ld create mode 100644 targets/stm32f407.ld create mode 100644 targets/stm32f469.ld create mode 100644 targets/stm32f469disco.json create mode 100644 targets/stm32f4disco-1.json create mode 100644 targets/stm32f4disco.json create mode 100644 targets/stm32f7x2zetx.ld create mode 100644 targets/stm32l031k6.ld create mode 100644 targets/stm32l072czt6.ld create mode 100644 targets/stm32l0x2.json create mode 100644 targets/stm32l4x2.ld create mode 100644 targets/stm32l4x5.ld create mode 100644 targets/stm32l4x6.ld create mode 100644 targets/stm32l5x2xe.ld create mode 100644 targets/stm32wl5x_cm4.json create mode 100644 targets/stm32wle5.json create mode 100644 targets/stm32wlx.ld create mode 100644 targets/swan.json create mode 100644 targets/teensy36.json create mode 100644 targets/teensy36.s create mode 100644 targets/teensy40.json create mode 100644 targets/teensy40.s create mode 100644 targets/teensy41.json create mode 100644 targets/thingplus-rp2040.json create mode 100644 targets/thumby.json create mode 100644 targets/tiny2350.json create mode 100644 targets/tkey.json create mode 100644 targets/tkey.ld create mode 100644 targets/trinket-m0.json create mode 100644 targets/trinkey-qt2040-boot-stage2.S create mode 100644 targets/trinkey-qt2040.json create mode 100644 targets/tufty2040.json create mode 100644 targets/wasi.json create mode 100644 targets/wasip1.json create mode 100644 targets/wasip2.json create mode 100644 targets/wasm-undefined.txt create mode 100644 targets/wasm-unknown.json create mode 100644 targets/wasm.json create mode 100644 targets/wasm_exec.js create mode 100644 targets/waveshare-rp2040-tiny.json create mode 100644 targets/waveshare-rp2040-zero.json create mode 100644 targets/wioterminal.json create mode 100644 targets/x9pro.json create mode 100644 targets/xiao-ble.json create mode 100644 targets/xiao-esp32c3.json create mode 100644 targets/xiao-rp2040.json create mode 100644 targets/xiao.json create mode 100644 targets/xtensa.json diff --git a/internal/targets/config.go b/internal/targets/config.go new file mode 100644 index 00000000..66874434 --- /dev/null +++ b/internal/targets/config.go @@ -0,0 +1,43 @@ +package targets + +// Config represents a complete target configuration after inheritance resolution +type Config struct { + // Target identification + Name string `json:"-"` + + // LLVM configuration + LLVMTarget string `json:"llvm-target"` + CPU string `json:"cpu"` + Features string `json:"features"` + + // Build configuration + BuildTags []string `json:"build-tags"` + GOOS string `json:"goos"` + GOARCH string `json:"goarch"` + + // Compiler and linker configuration + Linker string `json:"linker"` + CFlags []string `json:"cflags"` + LDFlags []string `json:"ldflags"` +} + +// RawConfig represents the raw JSON configuration before inheritance resolution +type RawConfig struct { + Inherits []string `json:"inherits"` + Config +} + +// IsEmpty returns true if the config appears to be uninitialized +func (c *Config) IsEmpty() bool { + return c.Name == "" && c.LLVMTarget == "" && c.GOOS == "" && c.GOARCH == "" +} + +// HasInheritance returns true if this config inherits from other configs +func (rc *RawConfig) HasInheritance() bool { + return len(rc.Inherits) > 0 +} + +// GetInherits returns the list of configs this config inherits from +func (rc *RawConfig) GetInherits() []string { + return rc.Inherits +} diff --git a/internal/targets/example_test.go b/internal/targets/example_test.go new file mode 100644 index 00000000..93bb8bb9 --- /dev/null +++ b/internal/targets/example_test.go @@ -0,0 +1,73 @@ +package targets_test + +import ( + "fmt" + "log" + "sort" + + "github.com/goplus/llgo/internal/targets" +) + +func ExampleResolver_Resolve() { + resolver := targets.NewDefaultResolver() + + // Resolve a specific target + config, err := resolver.Resolve("rp2040") + if err != nil { + log.Fatal(err) + } + + fmt.Printf("Target: %s\n", config.Name) + fmt.Printf("LLVM Target: %s\n", config.LLVMTarget) + fmt.Printf("CPU: %s\n", config.CPU) + fmt.Printf("GOOS: %s\n", config.GOOS) + fmt.Printf("GOARCH: %s\n", config.GOARCH) + if len(config.BuildTags) > 0 { + fmt.Printf("Build Tags: %v\n", config.BuildTags) + } + if len(config.CFlags) > 0 { + fmt.Printf("C Flags: %v\n", config.CFlags) + } + if len(config.LDFlags) > 0 { + fmt.Printf("LD Flags: %v\n", config.LDFlags) + } +} + +func ExampleResolver_ListAvailableTargets() { + resolver := targets.NewDefaultResolver() + + targets, err := resolver.ListAvailableTargets() + if err != nil { + log.Fatal(err) + } + + // Show first 10 targets + sort.Strings(targets) + fmt.Printf("Available targets (first 10 of %d):\n", len(targets)) + for i, target := range targets[:10] { + fmt.Printf("%d. %s\n", i+1, target) + } +} + +func ExampleResolver_ResolveAll() { + resolver := targets.NewDefaultResolver() + + configs, err := resolver.ResolveAll() + if err != nil { + log.Fatal(err) + } + + // Count targets by GOOS + goosCounts := make(map[string]int) + for _, config := range configs { + if config.GOOS != "" { + goosCounts[config.GOOS]++ + } + } + + fmt.Printf("Loaded %d target configurations\n", len(configs)) + fmt.Printf("GOOS distribution:\n") + for goos, count := range goosCounts { + fmt.Printf(" %s: %d targets\n", goos, count) + } +} diff --git a/internal/targets/loader.go b/internal/targets/loader.go new file mode 100644 index 00000000..cea4ee6d --- /dev/null +++ b/internal/targets/loader.go @@ -0,0 +1,176 @@ +package targets + +import ( + "encoding/json" + "fmt" + "os" + "path/filepath" + "strings" +) + +// Loader handles loading and parsing target configurations +type Loader struct { + targetsDir string + cache map[string]*RawConfig +} + +// NewLoader creates a new target configuration loader +func NewLoader(targetsDir string) *Loader { + return &Loader{ + targetsDir: targetsDir, + cache: make(map[string]*RawConfig), + } +} + +// LoadRaw loads a raw configuration without resolving inheritance +func (l *Loader) LoadRaw(name string) (*RawConfig, error) { + // Check cache first + if config, exists := l.cache[name]; exists { + return config, nil + } + + // Construct file path + configPath := filepath.Join(l.targetsDir, name+".json") + + // Read file + data, err := os.ReadFile(configPath) + if err != nil { + return nil, fmt.Errorf("failed to read target config %s: %w", name, err) + } + + // Parse JSON + var config RawConfig + if err := json.Unmarshal(data, &config); err != nil { + return nil, fmt.Errorf("failed to parse target config %s: %w", name, err) + } + + // Set the name + config.Name = name + + // Cache the result + l.cache[name] = &config + + return &config, nil +} + +// Load loads a target configuration with inheritance resolved +func (l *Loader) Load(name string) (*Config, error) { + raw, err := l.LoadRaw(name) + if err != nil { + return nil, err + } + + return l.resolveInheritance(raw) +} + +// LoadAll loads all target configurations in the targets directory +func (l *Loader) LoadAll() (map[string]*Config, error) { + entries, err := os.ReadDir(l.targetsDir) + if err != nil { + return nil, fmt.Errorf("failed to read targets directory: %w", err) + } + + configs := make(map[string]*Config) + + for _, entry := range entries { + if entry.IsDir() || !strings.HasSuffix(entry.Name(), ".json") { + continue + } + + name := strings.TrimSuffix(entry.Name(), ".json") + config, err := l.Load(name) + if err != nil { + return nil, fmt.Errorf("failed to load target %s: %w", name, err) + } + + configs[name] = config + } + + return configs, nil +} + +// resolveInheritance resolves inheritance chain for a configuration +func (l *Loader) resolveInheritance(raw *RawConfig) (*Config, error) { + if !raw.HasInheritance() { + // No inheritance, return as-is + return &raw.Config, nil + } + + // Start with base config + result := &Config{Name: raw.Name} + + // Apply inheritance in order + for _, parentName := range raw.GetInherits() { + parent, err := l.Load(parentName) + if err != nil { + return nil, fmt.Errorf("failed to load parent config %s: %w", parentName, err) + } + + // Merge parent into result + l.mergeConfig(result, parent) + } + + // Finally, apply current config on top + l.mergeConfig(result, &raw.Config) + + return result, nil +} + +// mergeConfig merges source config into destination config +// Non-empty values in source override those in destination +func (l *Loader) mergeConfig(dst, src *Config) { + if src.LLVMTarget != "" { + dst.LLVMTarget = src.LLVMTarget + } + if src.CPU != "" { + dst.CPU = src.CPU + } + if src.Features != "" { + dst.Features = src.Features + } + if src.GOOS != "" { + dst.GOOS = src.GOOS + } + if src.GOARCH != "" { + dst.GOARCH = src.GOARCH + } + if src.Linker != "" { + dst.Linker = src.Linker + } + + // Merge slices (append, don't replace) + if len(src.BuildTags) > 0 { + dst.BuildTags = append(dst.BuildTags, src.BuildTags...) + } + if len(src.CFlags) > 0 { + dst.CFlags = append(dst.CFlags, src.CFlags...) + } + if len(src.LDFlags) > 0 { + dst.LDFlags = append(dst.LDFlags, src.LDFlags...) + } +} + +// GetTargetsDir returns the targets directory path +func (l *Loader) GetTargetsDir() string { + return l.targetsDir +} + +// ListTargets returns a list of all available target names +func (l *Loader) ListTargets() ([]string, error) { + entries, err := os.ReadDir(l.targetsDir) + if err != nil { + return nil, fmt.Errorf("failed to read targets directory: %w", err) + } + + var targets []string + for _, entry := range entries { + if entry.IsDir() || !strings.HasSuffix(entry.Name(), ".json") { + continue + } + + name := strings.TrimSuffix(entry.Name(), ".json") + targets = append(targets, name) + } + + return targets, nil +} diff --git a/internal/targets/resolver.go b/internal/targets/resolver.go new file mode 100644 index 00000000..d144bc18 --- /dev/null +++ b/internal/targets/resolver.go @@ -0,0 +1,77 @@ +package targets + +import ( + "fmt" + "path/filepath" + "runtime" +) + +// Resolver provides high-level interface for target configuration resolution +type Resolver struct { + loader *Loader +} + +// NewResolver creates a new target resolver +func NewResolver(targetsDir string) *Resolver { + return &Resolver{ + loader: NewLoader(targetsDir), + } +} + +// NewDefaultResolver creates a resolver with default targets directory +func NewDefaultResolver() *Resolver { + // Assume targets directory is relative to this package + _, filename, _, _ := runtime.Caller(0) + projectRoot := filepath.Dir(filepath.Dir(filepath.Dir(filename))) + targetsDir := filepath.Join(projectRoot, "targets") + + return NewResolver(targetsDir) +} + +// Resolve resolves a target configuration by name +func (r *Resolver) Resolve(targetName string) (*Config, error) { + config, err := r.loader.Load(targetName) + if err != nil { + return nil, fmt.Errorf("failed to resolve target %s: %w", targetName, err) + } + + // Validate required fields + if err := r.validateConfig(config); err != nil { + return nil, fmt.Errorf("invalid target config %s: %w", targetName, err) + } + + return config, nil +} + +// ResolveAll resolves all available target configurations +func (r *Resolver) ResolveAll() (map[string]*Config, error) { + return r.loader.LoadAll() +} + +// ListAvailableTargets returns a list of all available target names +func (r *Resolver) ListAvailableTargets() ([]string, error) { + return r.loader.ListTargets() +} + +// validateConfig validates that a resolved config has required fields +func (r *Resolver) validateConfig(config *Config) error { + if config.Name == "" { + return fmt.Errorf("target name is required") + } + + // For now, we don't require any specific fields since different targets + // may have different requirements. This can be extended in the future. + + return nil +} + +// GetTargetsDirectory returns the path to the targets directory +func (r *Resolver) GetTargetsDirectory() string { + return r.loader.GetTargetsDir() +} + +// HasTarget checks if a target with the given name exists +func (r *Resolver) HasTarget(name string) bool { + _, err := r.loader.LoadRaw(name) + return err == nil +} diff --git a/internal/targets/targets_test.go b/internal/targets/targets_test.go new file mode 100644 index 00000000..bfe5c677 --- /dev/null +++ b/internal/targets/targets_test.go @@ -0,0 +1,322 @@ +//go:build !llgo + +package targets + +import ( + "os" + "path/filepath" + "testing" +) + +func TestConfigBasics(t *testing.T) { + config := &Config{ + Name: "test", + LLVMTarget: "arm-none-eabi", + GOOS: "linux", + GOARCH: "arm", + } + + if config.IsEmpty() { + t.Error("Config should not be empty when fields are set") + } + + empty := &Config{} + if !empty.IsEmpty() { + t.Error("Empty config should report as empty") + } +} + +func TestRawConfigInheritance(t *testing.T) { + raw := &RawConfig{ + Inherits: []string{"parent1", "parent2"}, + Config: Config{ + Name: "child", + }, + } + + if !raw.HasInheritance() { + t.Error("RawConfig should report having inheritance") + } + + inherits := raw.GetInherits() + if len(inherits) != 2 || inherits[0] != "parent1" || inherits[1] != "parent2" { + t.Errorf("Expected inheritance list [parent1, parent2], got %v", inherits) + } + + noInherit := &RawConfig{} + if noInherit.HasInheritance() { + t.Error("RawConfig with no inherits should not report having inheritance") + } +} + +func TestLoaderLoadRaw(t *testing.T) { + // Create a temporary directory for test configs + tempDir := t.TempDir() + + // Create a test config file + testConfig := `{ + "llvm-target": "thumbv6m-unknown-unknown-eabi", + "cpu": "cortex-m0plus", + "goos": "linux", + "goarch": "arm", + "build-tags": ["test", "embedded"], + "cflags": ["-Os", "-g"], + "ldflags": ["--gc-sections"] + }` + + configPath := filepath.Join(tempDir, "test-target.json") + if err := os.WriteFile(configPath, []byte(testConfig), 0644); err != nil { + t.Fatalf("Failed to write test config: %v", err) + } + + loader := NewLoader(tempDir) + config, err := loader.LoadRaw("test-target") + if err != nil { + t.Fatalf("Failed to load raw config: %v", err) + } + + if config.Name != "test-target" { + t.Errorf("Expected name 'test-target', got '%s'", config.Name) + } + if config.LLVMTarget != "thumbv6m-unknown-unknown-eabi" { + t.Errorf("Expected llvm-target 'thumbv6m-unknown-unknown-eabi', got '%s'", config.LLVMTarget) + } + if config.CPU != "cortex-m0plus" { + t.Errorf("Expected cpu 'cortex-m0plus', got '%s'", config.CPU) + } + if len(config.BuildTags) != 2 || config.BuildTags[0] != "test" || config.BuildTags[1] != "embedded" { + t.Errorf("Expected build-tags [test, embedded], got %v", config.BuildTags) + } +} + +func TestLoaderInheritance(t *testing.T) { + tempDir := t.TempDir() + + // Create parent config + parentConfig := `{ + "llvm-target": "thumbv6m-unknown-unknown-eabi", + "cpu": "cortex-m0plus", + "goos": "linux", + "goarch": "arm", + "cflags": ["-Os"], + "ldflags": ["--gc-sections"] + }` + + // Create child config that inherits from parent + childConfig := `{ + "inherits": ["parent"], + "cpu": "cortex-m4", + "build-tags": ["child"], + "cflags": ["-O2"], + "ldflags": ["-g"] + }` + + parentPath := filepath.Join(tempDir, "parent.json") + childPath := filepath.Join(tempDir, "child.json") + + if err := os.WriteFile(parentPath, []byte(parentConfig), 0644); err != nil { + t.Fatalf("Failed to write parent config: %v", err) + } + if err := os.WriteFile(childPath, []byte(childConfig), 0644); err != nil { + t.Fatalf("Failed to write child config: %v", err) + } + + loader := NewLoader(tempDir) + config, err := loader.Load("child") + if err != nil { + t.Fatalf("Failed to load child config: %v", err) + } + + // Check inherited values + if config.LLVMTarget != "thumbv6m-unknown-unknown-eabi" { + t.Errorf("Expected inherited llvm-target 'thumbv6m-unknown-unknown-eabi', got '%s'", config.LLVMTarget) + } + if config.GOOS != "linux" { + t.Errorf("Expected inherited goos 'linux', got '%s'", config.GOOS) + } + if config.GOARCH != "arm" { + t.Errorf("Expected inherited goarch 'arm', got '%s'", config.GOARCH) + } + + // Check overridden values + if config.CPU != "cortex-m4" { + t.Errorf("Expected overridden cpu 'cortex-m4', got '%s'", config.CPU) + } + + // Check merged arrays + expectedCFlags := []string{"-Os", "-O2"} + if len(config.CFlags) != 2 || config.CFlags[0] != "-Os" || config.CFlags[1] != "-O2" { + t.Errorf("Expected merged cflags %v, got %v", expectedCFlags, config.CFlags) + } + + expectedLDFlags := []string{"--gc-sections", "-g"} + if len(config.LDFlags) != 2 || config.LDFlags[0] != "--gc-sections" || config.LDFlags[1] != "-g" { + t.Errorf("Expected merged ldflags %v, got %v", expectedLDFlags, config.LDFlags) + } + + // Check child-specific values + if len(config.BuildTags) != 1 || config.BuildTags[0] != "child" { + t.Errorf("Expected build-tags [child], got %v", config.BuildTags) + } +} + +func TestLoaderListTargets(t *testing.T) { + tempDir := t.TempDir() + + // Create some test config files + configs := []string{"target1.json", "target2.json", "not-a-target.txt"} + for _, config := range configs { + configPath := filepath.Join(tempDir, config) + if err := os.WriteFile(configPath, []byte("{}"), 0644); err != nil { + t.Fatalf("Failed to write config %s: %v", config, err) + } + } + + loader := NewLoader(tempDir) + targets, err := loader.ListTargets() + if err != nil { + t.Fatalf("Failed to list targets: %v", err) + } + + expectedTargets := []string{"target1", "target2"} + if len(targets) != len(expectedTargets) { + t.Errorf("Expected %d targets, got %d", len(expectedTargets), len(targets)) + } + + for _, expected := range expectedTargets { + found := false + for _, target := range targets { + if target == expected { + found = true + break + } + } + if !found { + t.Errorf("Expected target %s not found in list %v", expected, targets) + } + } +} + +func TestResolver(t *testing.T) { + tempDir := t.TempDir() + + // Create a test config + testConfig := `{ + "llvm-target": "wasm32-unknown-wasi", + "cpu": "generic", + "goos": "wasip1", + "goarch": "wasm" + }` + + configPath := filepath.Join(tempDir, "wasi.json") + if err := os.WriteFile(configPath, []byte(testConfig), 0644); err != nil { + t.Fatalf("Failed to write test config: %v", err) + } + + resolver := NewResolver(tempDir) + + // Test resolve + config, err := resolver.Resolve("wasi") + if err != nil { + t.Fatalf("Failed to resolve target: %v", err) + } + + if config.Name != "wasi" { + t.Errorf("Expected name 'wasi', got '%s'", config.Name) + } + + // Test has target + if !resolver.HasTarget("wasi") { + t.Error("Resolver should report having 'wasi' target") + } + if resolver.HasTarget("nonexistent") { + t.Error("Resolver should not report having 'nonexistent' target") + } + + // Test list available targets + targets, err := resolver.ListAvailableTargets() + if err != nil { + t.Fatalf("Failed to list available targets: %v", err) + } + + if len(targets) != 1 || targets[0] != "wasi" { + t.Errorf("Expected targets [wasi], got %v", targets) + } +} + +func TestResolverWithRealTargets(t *testing.T) { + // Test with actual targets directory if it exists + resolver := NewDefaultResolver() + targetsDir := resolver.GetTargetsDirectory() + + // Check if targets directory exists + if _, err := os.Stat(targetsDir); os.IsNotExist(err) { + t.Skipf("Targets directory %s does not exist, skipping real targets test", targetsDir) + } + + // Test listing real targets + targets, err := resolver.ListAvailableTargets() + if err != nil { + t.Fatalf("Failed to list real targets: %v", err) + } + + t.Logf("Found %d targets in %s", len(targets), targetsDir) + + // Test resolving some known targets + knownTargets := []string{"wasi", "cortex-m", "rp2040"} + for _, targetName := range knownTargets { + if resolver.HasTarget(targetName) { + config, err := resolver.Resolve(targetName) + if err != nil { + t.Errorf("Failed to resolve known target %s: %v", targetName, err) + continue + } + t.Logf("Resolved target %s: LLVM=%s, CPU=%s, GOOS=%s, GOARCH=%s", + targetName, config.LLVMTarget, config.CPU, config.GOOS, config.GOARCH) + } + } +} + +func TestResolveAllRealTargets(t *testing.T) { + resolver := NewDefaultResolver() + targetsDir := resolver.GetTargetsDirectory() + + // Check if targets directory exists + if _, err := os.Stat(targetsDir); os.IsNotExist(err) { + t.Skipf("Targets directory %s does not exist, skipping resolve all test", targetsDir) + } + + // Test resolving all targets + configs, err := resolver.ResolveAll() + if err != nil { + t.Fatalf("Failed to resolve all targets: %v", err) + } + + t.Logf("Successfully resolved %d targets", len(configs)) + + // Check that all configs have names + for name, config := range configs { + if config.Name != name { + t.Errorf("Config name mismatch: key=%s, config.Name=%s", name, config.Name) + } + if config.IsEmpty() { + t.Errorf("Config %s appears to be empty", name) + } + } + + // Log some statistics + goosCounts := make(map[string]int) + goarchCounts := make(map[string]int) + + for _, config := range configs { + if config.GOOS != "" { + goosCounts[config.GOOS]++ + } + if config.GOARCH != "" { + goarchCounts[config.GOARCH]++ + } + } + + t.Logf("GOOS distribution: %v", goosCounts) + t.Logf("GOARCH distribution: %v", goarchCounts) +} diff --git a/targets/adafruit-esp32-feather-v2.json b/targets/adafruit-esp32-feather-v2.json new file mode 100644 index 00000000..9db914db --- /dev/null +++ b/targets/adafruit-esp32-feather-v2.json @@ -0,0 +1,4 @@ +{ + "inherits": ["esp32"], + "build-tags": ["adafruit_esp32_feather_v2"] +} diff --git a/targets/ae-rp2040.json b/targets/ae-rp2040.json new file mode 100644 index 00000000..026ea443 --- /dev/null +++ b/targets/ae-rp2040.json @@ -0,0 +1,14 @@ +{ + "inherits": [ + "rp2040" + ], + "build-tags": ["ae_rp2040"], + "serial-port": ["2e8a:000A"], + "ldflags": [ + "--defsym=__flash_size=2048K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} + diff --git a/targets/arduino-leonardo.json b/targets/arduino-leonardo.json new file mode 100644 index 00000000..17652d85 --- /dev/null +++ b/targets/arduino-leonardo.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atmega32u4"], + "build-tags": ["arduino_leonardo"], + "ldflags": [ + "--defsym=_bootloader_size=512", + "--defsym=_stack_size=512" + ], + "flash-command": "avrdude -c avr109 -p atmega32u4 -b 57600 -P {port} -U flash:w:{hex}:i", + "emulator": "simavr -m atmega32u4 -f 16000000 {}" +} diff --git a/targets/arduino-mega1280.json b/targets/arduino-mega1280.json new file mode 100644 index 00000000..d289297f --- /dev/null +++ b/targets/arduino-mega1280.json @@ -0,0 +1,8 @@ +{ + "inherits": ["atmega1280"], + "build-tags": ["arduino_mega1280"], + "ldflags": [ + "--defsym=_bootloader_size=4096" + ], + "flash-command":"avrdude -c arduino -b 57600 -p atmega1280 -P {port} -U flash:w:{hex}:i -v -D" +} diff --git a/targets/arduino-mega2560.json b/targets/arduino-mega2560.json new file mode 100644 index 00000000..afbd7554 --- /dev/null +++ b/targets/arduino-mega2560.json @@ -0,0 +1,8 @@ +{ + "inherits": ["atmega2560"], + "build-tags": ["arduino_mega2560"], + "ldflags": [ + "--defsym=_bootloader_size=8192" + ], + "flash-command":"avrdude -c wiring -b 115200 -p atmega2560 -P {port} -U flash:w:{hex}:i -v -D" +} diff --git a/targets/arduino-mkr1000.json b/targets/arduino-mkr1000.json new file mode 100644 index 00000000..89d7bfa6 --- /dev/null +++ b/targets/arduino-mkr1000.json @@ -0,0 +1,7 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["arduino_mkr1000"], + "serial": "usb", + "flash-command": "bossac -i -e -w -v -R -U --port={port} --offset=0x2000 {bin}", + "flash-1200-bps-reset": "true" +} diff --git a/targets/arduino-mkrwifi1010.json b/targets/arduino-mkrwifi1010.json new file mode 100644 index 00000000..225d29be --- /dev/null +++ b/targets/arduino-mkrwifi1010.json @@ -0,0 +1,8 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["arduino_mkrwifi1010", "ninafw"], + "serial": "usb", + "serial-port": ["2341:8054", "2341:0054"], + "flash-command": "bossac -i -e -w -v -R -U --port={port} --offset=0x2000 {bin}", + "flash-1200-bps-reset": "true" +} diff --git a/targets/arduino-nano-new.json b/targets/arduino-nano-new.json new file mode 100644 index 00000000..78c990f5 --- /dev/null +++ b/targets/arduino-nano-new.json @@ -0,0 +1,4 @@ +{ + "inherits": ["arduino-nano"], + "flash-command": "avrdude -c arduino -p atmega328p -b 115200 -P {port} -U flash:w:{hex}:i" +} diff --git a/targets/arduino-nano.json b/targets/arduino-nano.json new file mode 100644 index 00000000..65dd6c2d --- /dev/null +++ b/targets/arduino-nano.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atmega328p"], + "build-tags": ["arduino_nano"], + "ldflags": [ + "--defsym=_bootloader_size=512", + "--defsym=_stack_size=512" + ], + "flash-command": "avrdude -c arduino -p atmega328p -b 57600 -P {port} -U flash:w:{hex}:i", + "emulator": "simavr -m atmega328p -f 16000000 {}" +} diff --git a/targets/arduino-nano33.json b/targets/arduino-nano33.json new file mode 100644 index 00000000..f37fbabb --- /dev/null +++ b/targets/arduino-nano33.json @@ -0,0 +1,7 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["arduino_nano33", "ninafw", "ninafw_machine_init"], + "flash-command": "bossac -i -e -w -v -R -U --port={port} --offset=0x2000 {bin}", + "serial-port": ["2341:8057", "2341:0057"], + "flash-1200-bps-reset": "true" +} diff --git a/targets/arduino-zero.json b/targets/arduino-zero.json new file mode 100644 index 00000000..045bb8c0 --- /dev/null +++ b/targets/arduino-zero.json @@ -0,0 +1,7 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["arduino_zero"], + "serial": "usb", + "flash-command": "bossac -i -e -w -v -R -U --port={port} --offset=0x2000 {bin}", + "flash-1200-bps-reset": "true" +} diff --git a/targets/arduino.json b/targets/arduino.json new file mode 100644 index 00000000..b5bd9775 --- /dev/null +++ b/targets/arduino.json @@ -0,0 +1,11 @@ +{ + "inherits": ["atmega328p"], + "build-tags": ["arduino"], + "ldflags": [ + "--defsym=_bootloader_size=512", + "--defsym=_stack_size=512" + ], + "flash-command": "avrdude -c arduino -p atmega328p -P {port} -U flash:w:{hex}:i", + "serial-port": ["2341:0043", "2341:0001", "2a03:0043", "2341:0243"], + "emulator": "simavr -m atmega328p -f 16000000 {}" +} diff --git a/targets/arm.ld b/targets/arm.ld new file mode 100644 index 00000000..c5f30ea6 --- /dev/null +++ b/targets/arm.ld @@ -0,0 +1,86 @@ + +/* Unused, but here to silence a linker warning. */ +ENTRY(Reset_Handler) + +/* define output sections */ +SECTIONS +{ + /* Program code and read-only data goes to FLASH_TEXT. */ + .text : + { + KEEP(*(.isr_vector)) + KEEP(*(.after_isr_vector)) /* for the RP2350 */ + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + } >FLASH_TEXT + + .tinygo_stacksizes : + { + *(.tinygo_stacksizes) + } > FLASH_TEXT + + /* Put the stack at the bottom of RAM, so that the application will + * crash on stack overflow instead of silently corrupting memory. + * See: http://blog.japaric.io/stack-overflow-protection/ */ + .stack (NOLOAD) : + { + . = ALIGN(4); + . += _stack_size; + _stack_top = .; + } >RAM + + /* Stack for second core (core 1), if there is one. */ + .stack1 (NOLOAD) : + { + . = ALIGN(4); + . += DEFINED(__num_stacks) && __num_stacks >= 2 ? _stack_size : 0; + _stack1_top = .; + } >RAM + + /* Start address (in flash) of .data, used by startup code. */ + _sidata = LOADADDR(.data); + + /* Globals with initial value */ + .data : + { + . = ALIGN(4); + _sdata = .; /* used by startup code */ + *(.data) + *(.data.*) + . = ALIGN(4); + *(.ramfuncs*) /* Functions that must execute from RAM */ + . = ALIGN(4); + _edata = .; /* used by startup code */ + } >RAM AT>FLASH_TEXT + + /* Zero-initialized globals */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* used by startup code */ + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* used by startup code */ + } >RAM + + /DISCARD/ : + { + *(.ARM.exidx) /* causes 'no memory region specified' error in lld */ + *(.ARM.exidx.*) /* causes spurious 'undefined reference' errors */ + } +} + +/* For the memory allocator. */ +_heap_start = _ebss; +_heap_end = ORIGIN(RAM) + LENGTH(RAM); +_globals_start = _sdata; +_globals_end = _ebss; + +/* For the flash API */ +__flash_data_start = LOADADDR(.data) + SIZEOF(.data); +__flash_data_end = ORIGIN(FLASH_TEXT) + LENGTH(FLASH_TEXT); diff --git a/targets/atmega1280.json b/targets/atmega1280.json new file mode 100644 index 00000000..34e78f41 --- /dev/null +++ b/targets/atmega1280.json @@ -0,0 +1,14 @@ +{ + "inherits": ["avr"], + "cpu": "atmega1280", + "build-tags": ["atmega1280", "atmega"], + "serial": "uart", + "ldflags": [ + "--defsym=_stack_size=512" + ], + "linkerscript": "src/device/avr/atmega1280.ld", + "extra-files": [ + "targets/avr.S", + "src/device/avr/atmega1280.s" + ] +} diff --git a/targets/atmega1284p.json b/targets/atmega1284p.json new file mode 100644 index 00000000..501fb58d --- /dev/null +++ b/targets/atmega1284p.json @@ -0,0 +1,16 @@ +{ + "inherits": ["avr"], + "cpu": "atmega1284p", + "build-tags": ["atmega1284p", "atmega"], + "serial": "uart", + "ldflags": [ + "--defsym=_bootloader_size=0", + "--defsym=_stack_size=512" + ], + "linkerscript": "src/device/avr/atmega1284p.ld", + "extra-files": [ + "targets/avr.S", + "src/device/avr/atmega1284p.s" + ], + "emulator": "simavr -m atmega1284p -f 20000000 {}" +} diff --git a/targets/atmega2560.json b/targets/atmega2560.json new file mode 100644 index 00000000..a00179ef --- /dev/null +++ b/targets/atmega2560.json @@ -0,0 +1,14 @@ +{ + "inherits": ["avr"], + "cpu": "atmega2560", + "build-tags": ["atmega2560", "atmega"], + "serial": "uart", + "ldflags": [ + "--defsym=_stack_size=512" + ], + "linkerscript": "src/device/avr/atmega2560.ld", + "extra-files": [ + "targets/avr.S", + "src/device/avr/atmega2560.s" + ] +} diff --git a/targets/atmega328p.json b/targets/atmega328p.json new file mode 100644 index 00000000..d4098d4b --- /dev/null +++ b/targets/atmega328p.json @@ -0,0 +1,11 @@ +{ + "inherits": ["avr"], + "cpu": "atmega328p", + "build-tags": ["atmega328p", "atmega", "avr5"], + "serial": "uart", + "linkerscript": "src/device/avr/atmega328p.ld", + "extra-files": [ + "targets/avr.S", + "src/device/avr/atmega328p.s" + ] +} diff --git a/targets/atmega328pb.json b/targets/atmega328pb.json new file mode 100644 index 00000000..c4e1b447 --- /dev/null +++ b/targets/atmega328pb.json @@ -0,0 +1,15 @@ +{ + "inherits": ["avr"], + "cpu": "atmega328pb", + "build-tags": ["atmega328pb", "atmega", "avr5"], + "ldflags": [ + "--defsym=_bootloader_size=512", + "--defsym=_stack_size=512" + ], + "serial": "uart", + "linkerscript": "src/device/avr/atmega328pb.ld", + "extra-files": [ + "targets/avr.S", + "src/device/avr/atmega328pb.s" + ] +} diff --git a/targets/atmega32u4.json b/targets/atmega32u4.json new file mode 100644 index 00000000..7aa2c08b --- /dev/null +++ b/targets/atmega32u4.json @@ -0,0 +1,11 @@ +{ + "inherits": ["avr"], + "cpu": "atmega32u4", + "build-tags": ["atmega32u4", "avr5"], + "serial": "none", + "linkerscript": "src/device/avr/atmega32u4.ld", + "extra-files": [ + "targets/avr.S", + "src/device/avr/atmega32u4.s" + ] +} diff --git a/targets/atsamd21.ld b/targets/atsamd21.ld new file mode 100644 index 00000000..5bfcf454 --- /dev/null +++ b/targets/atsamd21.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000+0x2000, LENGTH = 0x00040000-0x2000 /* First 8KB used by bootloader */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" diff --git a/targets/atsamd21e18a.json b/targets/atsamd21e18a.json new file mode 100644 index 00000000..92b671c9 --- /dev/null +++ b/targets/atsamd21e18a.json @@ -0,0 +1,11 @@ +{ + "inherits": ["cortex-m0plus"], + "build-tags": ["atsamd21e18a", "atsamd21e18", "atsamd21", "sam"], + "serial": "usb", + "linkerscript": "targets/atsamd21.ld", + "extra-files": [ + "src/device/sam/atsamd21e18a.s" + ], + "openocd-transport": "swd", + "openocd-target": "at91samdXX" +} diff --git a/targets/atsamd21g18a.json b/targets/atsamd21g18a.json new file mode 100644 index 00000000..db46c962 --- /dev/null +++ b/targets/atsamd21g18a.json @@ -0,0 +1,11 @@ +{ + "inherits": ["cortex-m0plus"], + "build-tags": ["atsamd21g18a", "atsamd21g18", "atsamd21", "sam"], + "serial": "usb", + "linkerscript": "targets/atsamd21.ld", + "extra-files": [ + "src/device/sam/atsamd21g18a.s" + ], + "openocd-transport": "swd", + "openocd-target": "at91samdXX" +} diff --git a/targets/atsamd51.ld b/targets/atsamd51.ld new file mode 100644 index 00000000..908ce6a8 --- /dev/null +++ b/targets/atsamd51.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x00080000-0x4000 /* First 16KB used by bootloader */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/atsamd51g19a.json b/targets/atsamd51g19a.json new file mode 100644 index 00000000..4534d1c1 --- /dev/null +++ b/targets/atsamd51g19a.json @@ -0,0 +1,10 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["atsamd51g19a", "atsamd51g19", "atsamd51", "sam"], + "linkerscript": "targets/atsamd51.ld", + "extra-files": [ + "src/device/sam/atsamd51g19a.s" + ], + "openocd-transport": "swd", + "openocd-target": "atsame5x" +} diff --git a/targets/atsamd51j19a.json b/targets/atsamd51j19a.json new file mode 100644 index 00000000..2493ca4d --- /dev/null +++ b/targets/atsamd51j19a.json @@ -0,0 +1,10 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["atsamd51j19a", "atsamd51j19", "atsamd51", "sam"], + "linkerscript": "targets/atsamd51.ld", + "extra-files": [ + "src/device/sam/atsamd51j19a.s" + ], + "openocd-transport": "swd", + "openocd-target": "atsame5x" +} diff --git a/targets/atsamd51j20a.json b/targets/atsamd51j20a.json new file mode 100644 index 00000000..9f59e32d --- /dev/null +++ b/targets/atsamd51j20a.json @@ -0,0 +1,10 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["sam", "atsamd51", "atsamd51j20", "atsamd51j20a"], + "linkerscript": "targets/atsamd51j20a.ld", + "extra-files": [ + "src/device/sam/atsamd51j20a.s" + ], + "openocd-transport": "swd", + "openocd-target": "atsame5x" +} diff --git a/targets/atsamd51j20a.ld b/targets/atsamd51j20a.ld new file mode 100644 index 00000000..5b8ce971 --- /dev/null +++ b/targets/atsamd51j20a.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x00100000-0x4000 /* First 16KB used by bootloader */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/atsamd51p19a.json b/targets/atsamd51p19a.json new file mode 100644 index 00000000..6b2f6b5b --- /dev/null +++ b/targets/atsamd51p19a.json @@ -0,0 +1,10 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["atsamd51p19a", "atsamd51p19", "atsamd51", "sam"], + "linkerscript": "targets/atsamd51.ld", + "extra-files": [ + "src/device/sam/atsamd51p19a.s" + ], + "openocd-transport": "swd", + "openocd-target": "atsame5x" +} diff --git a/targets/atsamd51p20a.json b/targets/atsamd51p20a.json new file mode 100644 index 00000000..bc66ca03 --- /dev/null +++ b/targets/atsamd51p20a.json @@ -0,0 +1,10 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["sam", "atsamd51", "atsamd51p20", "atsamd51p20a"], + "linkerscript": "targets/atsamd51p20a.ld", + "extra-files": [ + "src/device/sam/atsamd51p20a.s" + ], + "openocd-transport": "swd", + "openocd-target": "atsame5x" +} diff --git a/targets/atsamd51p20a.ld b/targets/atsamd51p20a.ld new file mode 100644 index 00000000..5b8ce971 --- /dev/null +++ b/targets/atsamd51p20a.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x00100000-0x4000 /* First 16KB used by bootloader */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/atsame51j19a.json b/targets/atsame51j19a.json new file mode 100644 index 00000000..98136769 --- /dev/null +++ b/targets/atsame51j19a.json @@ -0,0 +1,10 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["atsame51j19a", "atsame51j19", "atsame51", "atsame5x", "sam"], + "linkerscript": "targets/atsame5xx19.ld", + "extra-files": [ + "src/device/sam/atsame51j19a.s" + ], + "openocd-transport": "swd", + "openocd-target": "atsame5x" +} diff --git a/targets/atsame54-xpro.json b/targets/atsame54-xpro.json new file mode 100644 index 00000000..b50e79f3 --- /dev/null +++ b/targets/atsame54-xpro.json @@ -0,0 +1,7 @@ +{ + "inherits": ["atsame54p20a"], + "build-tags": ["atsame54_xpro"], + "serial": "usb", + "flash-method": "openocd", + "openocd-interface": "cmsis-dap" +} diff --git a/targets/atsame54p20a.json b/targets/atsame54p20a.json new file mode 100644 index 00000000..f2450fb4 --- /dev/null +++ b/targets/atsame54p20a.json @@ -0,0 +1,10 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["sam", "atsame5x", "atsame54", "atsame54p20", "atsame54p20a"], + "linkerscript": "targets/atsame5xx20-no-bootloader.ld", + "extra-files": [ + "src/device/sam/atsame54p20a.s" + ], + "openocd-transport": "swd", + "openocd-target": "atsame5x" +} diff --git a/targets/atsame5xx19.ld b/targets/atsame5xx19.ld new file mode 100644 index 00000000..908ce6a8 --- /dev/null +++ b/targets/atsame5xx19.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x00080000-0x4000 /* First 16KB used by bootloader */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/atsame5xx20-no-bootloader.ld b/targets/atsame5xx20-no-bootloader.ld new file mode 100644 index 00000000..1e8ea33f --- /dev/null +++ b/targets/atsame5xx20-no-bootloader.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000+0x0000, LENGTH = 0x00100000-0x0000 + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/attiny1616.json b/targets/attiny1616.json new file mode 100644 index 00000000..38e645ae --- /dev/null +++ b/targets/attiny1616.json @@ -0,0 +1,14 @@ +{ + "inherits": ["avrtiny"], + "cpu": "attiny1616", + "build-tags": ["attiny1616"], + "gc": "none", + "cflags": [ + "-D__AVR_ARCH__=103" + ], + "linkerscript": "src/device/avr/attiny1616.ld", + "extra-files": [ + "src/device/avr/attiny1616.s" + ], + "flash-command": "pymcuprog write -f {hex} --erase --verify -d attiny1616 -t uart -u {port}" +} diff --git a/targets/attiny85.json b/targets/attiny85.json new file mode 100644 index 00000000..3fb11114 --- /dev/null +++ b/targets/attiny85.json @@ -0,0 +1,13 @@ +{ + "inherits": ["avr"], + "cpu": "attiny85", + "build-tags": ["attiny85", "attiny", "avr2", "avr25"], + "cflags": [ + "-D__AVR_ARCH__=25" + ], + "linkerscript": "src/device/avr/attiny85.ld", + "extra-files": [ + "targets/avr.S", + "src/device/avr/attiny85.s" + ] +} diff --git a/targets/avr.S b/targets/avr.S new file mode 100644 index 00000000..568ae6ae --- /dev/null +++ b/targets/avr.S @@ -0,0 +1,84 @@ +; This file provides common code across AVRs that cannot be implemented directly +; in Go. +; The reset vector is device-specific and is generated by tools/gen-device-avr.py. + +; These definitions are necessary because LLVM does not yet know these register +; aliases. See: https://reviews.llvm.org/D96492 +#define xl r26 +#define xh r27 +#define yl r28 +#define yh r29 +#define zl r30 +#define zh r31 + +; Ugly hack until https://reviews.llvm.org/D137572 is merged. +#if !defined(__AVR_HAVE_ELPM__) && defined(__flash1) +#define __AVR_HAVE_ELPM__ +#endif + +; Startup code +.section .text.__vector_RESET +.global __vector_RESET +__vector_RESET: + clr r1 ; r1 is expected to be 0 by the C calling convention + + ; Set up the stack pointer. + ldi xl, lo8(_stack_top) + ldi xh, hi8(_stack_top) + out 0x3d, xl; SPL + out 0x3e, xh; SPH + + ; Subtract one from the stack pointer, so it doesn't point in the .data section. + push r0 + + ; Initialize .data +init_data: + ldi xl, lo8(_sdata) + ldi xh, hi8(_sdata) + ldi yl, lo8(_edata) + ldi yh, hi8(_edata) + ldi zl, lo8(_sidata) + ldi zh, hi8(_sidata) +#ifdef __AVR_HAVE_ELPM__ + ldi r16, hh8(_sidata) ; RAMPZ = hh8(_sidata) + out 0x3b, r16 +#endif +init_data_loop: + cp xl, yl ; if x == y + cpc xh, yh + breq init_data_end ; goto main +#ifdef __AVR_HAVE_ELPM__ + elpm r0, Z+ ; r0 = *(z++) +#else + lpm r0, Z+ ; r0 = *(z++) +#endif + st X+, r0 ; *(x++) = r0 + rjmp init_data_loop ; goto init_data_loop +init_data_end: + + ; main will be placed right after here by the linker script so there's no + ; need to jump. + + +; The only thing this WDT handler really does is disable itself, to get out of +; sleep mode. +.section .text.__vector_WDT +.global __vector_WDT +__vector_WDT: + push r16 + + clr r16 + wdr ; Reset watchdog + out 0x34, r16 ; Clear reset reason (MCUSR) + + ; part 1: set WDCE and WDE to enable editing WDTCSR + lds r16, 0x60 ; r16 = WDTCSR + ori r16, 0x18 ; r16 |= WDCE | WDE + sts 0x60, r16 ; WDTCSR = r16 + + ; part 2: within 4 clock cycles, set the new value for WDTCSR + clr r16 + sts 0x60, r16 ; WDTCSR = 0 + + pop r16 + reti diff --git a/targets/avr.json b/targets/avr.json new file mode 100644 index 00000000..587a3e56 --- /dev/null +++ b/targets/avr.json @@ -0,0 +1,24 @@ +{ + "llvm-target": "avr", + "build-tags": ["avr", "baremetal", "linux", "arm"], + "goos": "linux", + "goarch": "arm", + "gc": "conservative", + "linker": "ld.lld", + "scheduler": "none", + "rtlib": "compiler-rt", + "libc": "picolibc", + "default-stack-size": 256, + "cflags": [ + "-Werror" + ], + "ldflags": [ + "-T", "targets/avr.ld", + "--gc-sections" + ], + "extra-files": [ + "src/internal/task/task_stack_avr.S", + "src/runtime/asm_avr.S" + ], + "gdb": ["avr-gdb"] +} diff --git a/targets/avr.ld b/targets/avr.ld new file mode 100644 index 00000000..293a06d7 --- /dev/null +++ b/targets/avr.ld @@ -0,0 +1,56 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0, LENGTH = __flash_size - _bootloader_size + RAM (xrw) : ORIGIN = 0x800000 + __ram_start, LENGTH = __ram_size +} + +ENTRY(main) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + KEEP(*(.text.__vector_RESET)) + KEEP(*(.text.main)) /* main must follow the reset handler */ + *(.text) + *(.text.*) + *(.progmem) + *(.progmem.*) + . = ALIGN(16); /* needed with ld.lld for some reasoon */ + } + + .stack (NOLOAD) : + { + . += _stack_size; + _stack_top = .; + } >RAM + + _sidata = LOADADDR(.data); + + .data : + { + _sdata = .; /* used by startup code */ + *(.rodata) + *(.rodata.*) + *(.data) + *(.data*) + _edata = .; /* used by startup code */ + } >RAM AT>FLASH_TEXT + + .bss : + { + _sbss = .; /* used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + _ebss = .; /* used by startup code */ + } >RAM +} + +/* For the memory allocator. */ +_heap_start = _ebss; +_heap_end = ORIGIN(RAM) + LENGTH(RAM); +_globals_start = _sdata; +_globals_end = _ebss; diff --git a/targets/avrtiny.S b/targets/avrtiny.S new file mode 100644 index 00000000..6b1a195c --- /dev/null +++ b/targets/avrtiny.S @@ -0,0 +1,43 @@ +#define __tmp_reg__ r16 +#define __zero_reg__ r17 + +; Startup code +.section .text.__vector_RESET +.global __vector_RESET +__vector_RESET: + clr __zero_reg__ ; this register is expected to be 0 by the C calling convention + + ; Keep the stack pointer at the default location, which is RAMEND. + +; Initialize .data section. +.section .text.__do_copy_data,"ax",@progbits +.global __do_copy_data +__do_copy_data: + ldi xl, lo8(__data_start) + ldi xh, hi8(__data_start) + ldi yl, lo8(__data_end) + ldi yh, hi8(__data_end) + ldi zl, lo8(__data_load_start) + ldi zh, hi8(__data_load_start) +1: ; loop + cp xl, yl ; if x == y + cpc xh, yh + breq 2f ; goto end + ld r16, Z+ ; r0 = *(z++) + st X+, r16 ; *(x++) = r0 + rjmp 1b ; goto loop +2: ; end + +; Initialize .bss section. +.section .text.__do_clear_bss,"ax",@progbits +.global __do_clear_bss +__do_clear_bss: + ldi xl, lo8(__bss_start) + ldi xh, hi8(__bss_start) + ldi yl, lo8(__bss_end) +1: ; loop + cp xl, yl ; if x == y + breq 2f ; goto end + st X+, __zero_reg__ ; *(x++) = 0 + rjmp 1b ; goto loop +2: ; end diff --git a/targets/avrtiny.json b/targets/avrtiny.json new file mode 100644 index 00000000..7cb1581f --- /dev/null +++ b/targets/avrtiny.json @@ -0,0 +1,25 @@ +{ + "llvm-target": "avr", + "build-tags": ["avr", "avrtiny", "baremetal", "linux", "arm"], + "goos": "linux", + "goarch": "arm", + "gc": "conservative", + "linker": "ld.lld", + "scheduler": "none", + "rtlib": "compiler-rt", + "libc": "picolibc", + "default-stack-size": 256, + "cflags": [ + "-Werror" + ], + "ldflags": [ + "-T", "targets/avrtiny.ld", + "--gc-sections" + ], + "extra-files": [ + "src/internal/task/task_stack_avr.S", + "src/runtime/asm_avr.S", + "targets/avrtiny.S" + ], + "gdb": ["avr-gdb"] +} diff --git a/targets/avrtiny.ld b/targets/avrtiny.ld new file mode 100644 index 00000000..60821cf8 --- /dev/null +++ b/targets/avrtiny.ld @@ -0,0 +1,58 @@ +/* Linker script for AVRs with a unified flash and RAM address space. This + * includes the ATtiny10 and the ATtiny1616. + */ + +MEMORY +{ + FLASH_TEXT (x) : ORIGIN = 0, LENGTH = __flash_size + FLASH_DATA (r) : ORIGIN = __mapped_flash_start, LENGTH = __flash_size + RAM (xrw) : ORIGIN = __ram_start, LENGTH = __ram_size +} + +ENTRY(main) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text.__vector_RESET) + KEEP(*(.text.__do_copy_data)) /* TODO: only use when __do_copy_data is requested */ + KEEP(*(.text.__do_clear_bss)) + KEEP(*(.text.main)) /* main must follow the reset handler */ + *(.text) + *(.text.*) + } > FLASH_TEXT + + /* Read-only data is stored in flash, but is read from an offset (0x4000 or + * 0x8000 depending on the chip). This requires some weird math to get it in + * the right place. + */ + .rodata ORIGIN(FLASH_DATA) + ADDR(.text) + SIZEOF(.text): + { + *(.rodata) + *(.rodata.*) + } AT>FLASH_TEXT + + /* The address to which the data section should be copied by the startup + * code. + */ + __data_load_start = ORIGIN(FLASH_DATA) + LOADADDR(.data); + + .data : + { + __data_start = .; /* used by startup code */ + *(.data) + *(.data*) + __data_end = .; /* used by startup code */ + } >RAM AT>FLASH_TEXT + + .bss : + { + __bss_start = .; /* used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + __bss_end = .; /* used by startup code */ + } >RAM +} diff --git a/targets/badger2040-w.json b/targets/badger2040-w.json new file mode 100644 index 00000000..7b7e729d --- /dev/null +++ b/targets/badger2040-w.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:0003"], + "build-tags": ["badger2040_w", "cyw43439"], + "ldflags": [ + "--defsym=__flash_size=1020K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/badger2040.json b/targets/badger2040.json new file mode 100644 index 00000000..34eef117 --- /dev/null +++ b/targets/badger2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:0003"], + "build-tags": ["badger2040"], + "ldflags": [ + "--defsym=__flash_size=1020K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/bluemicro840.json b/targets/bluemicro840.json new file mode 100644 index 00000000..ece3b768 --- /dev/null +++ b/targets/bluemicro840.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["bluemicro840"], + "serial-port": ["1d50:6161"], + "msd-volume-name": ["BLUEMICRO"] +} diff --git a/targets/bluepill-clone.json b/targets/bluepill-clone.json new file mode 100644 index 00000000..843a2127 --- /dev/null +++ b/targets/bluepill-clone.json @@ -0,0 +1,4 @@ +{ + "inherits": ["bluepill"], + "openocd-commands": ["set CPUTAPID 0x2ba01477"] +} diff --git a/targets/bluepill.json b/targets/bluepill.json new file mode 100644 index 00000000..752261f4 --- /dev/null +++ b/targets/bluepill.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m3"], + "build-tags": ["bluepill", "stm32f103", "stm32f1", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32.ld", + "extra-files": [ + "src/device/stm32/stm32f103.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink-v2", + "openocd-target": "stm32f1x" +} diff --git a/targets/btt-skr-pico.json b/targets/btt-skr-pico.json new file mode 100644 index 00000000..4ba86abf --- /dev/null +++ b/targets/btt-skr-pico.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "build-tags": ["btt_skr_pico"], + "serial-port": ["2e8a:000A"], + "ldflags": [ + "--defsym=__flash_size=16M" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/challenger-rp2040.json b/targets/challenger-rp2040.json new file mode 100644 index 00000000..6d187e77 --- /dev/null +++ b/targets/challenger-rp2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:1023"], + "build-tags": ["challenger_rp2040"], + "ldflags": [ + "--defsym=__flash_size=8M" + ], + "extra-files": [ + "targets/feather-rp2040-boot-stage2.S" + ] +} diff --git a/targets/circuitplay-bluefruit.json b/targets/circuitplay-bluefruit.json new file mode 100644 index 00000000..16d3013b --- /dev/null +++ b/targets/circuitplay-bluefruit.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["circuitplay_bluefruit"], + "serial-port": ["239a:8045"], + "msd-volume-name": ["CPLAYBTBOOT"] +} diff --git a/targets/circuitplay-express.json b/targets/circuitplay-express.json new file mode 100644 index 00000000..7355eb58 --- /dev/null +++ b/targets/circuitplay-express.json @@ -0,0 +1,9 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["circuitplay_express"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "serial-port": ["239a:8018"], + "msd-volume-name": ["CPLAYBOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/clue-alpha.json b/targets/clue-alpha.json new file mode 100644 index 00000000..3a559219 --- /dev/null +++ b/targets/clue-alpha.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["clue_alpha"], + "serial-port": ["239a:8072", "239a:8071"], + "msd-volume-name": ["CLUEBOOT"] +} diff --git a/targets/clue.json b/targets/clue.json new file mode 100644 index 00000000..e39363f8 --- /dev/null +++ b/targets/clue.json @@ -0,0 +1,3 @@ +{ + "inherits": ["clue-alpha"] +} diff --git a/targets/cortex-m-qemu.json b/targets/cortex-m-qemu.json new file mode 100644 index 00000000..5a1758db --- /dev/null +++ b/targets/cortex-m-qemu.json @@ -0,0 +1,10 @@ +{ + "inherits": ["cortex-m3"], + "build-tags": ["qemu", "lm3s6965"], + "linkerscript": "targets/lm3s6965.ld", + "default-stack-size": 4096, + "extra-files": [ + "targets/cortex-m-qemu.s" + ], + "emulator": "qemu-system-arm -machine lm3s6965evb -semihosting -nographic -kernel {}" +} diff --git a/targets/cortex-m-qemu.s b/targets/cortex-m-qemu.s new file mode 100644 index 00000000..685c7fd5 --- /dev/null +++ b/targets/cortex-m-qemu.s @@ -0,0 +1,59 @@ +// Generic Cortex-M interrupt vector. +// This vector is used by the Cortex-M QEMU target. + +.cfi_sections .debug_frame +.syntax unified + +// This is the default handler for interrupts, if triggered but not defined. +.section .text.Default_Handler +.global Default_Handler +.type Default_Handler, %function +Default_Handler: + .cfi_startproc + wfe + b Default_Handler + .cfi_endproc +.size Default_Handler, .-Default_Handler + +// Avoid the need for repeated .weak and .set instructions. +.macro IRQ handler + .weak \handler + .set \handler, Default_Handler +.endm + +.section .isr_vector, "a", %progbits +.global __isr_vector +__isr_vector: + // Interrupt vector as defined by Cortex-M, starting with the stack top. + // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading + // _stack_top and Reset_Handler. + .long _stack_top + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + // Define default implementations for interrupts, redirecting to + // Default_Handler when not implemented. + IRQ NMI_Handler + IRQ HardFault_Handler + IRQ MemoryManagement_Handler + IRQ BusFault_Handler + IRQ UsageFault_Handler + IRQ SVC_Handler + IRQ DebugMon_Handler + IRQ PendSV_Handler + IRQ SysTick_Handler + +.size __isr_vector, .-__isr_vector diff --git a/targets/cortex-m.json b/targets/cortex-m.json new file mode 100644 index 00000000..cf21969f --- /dev/null +++ b/targets/cortex-m.json @@ -0,0 +1,30 @@ +{ + "build-tags": ["cortexm", "baremetal", "linux", "arm"], + "goos": "linux", + "goarch": "arm", + "gc": "conservative", + "scheduler": "tasks", + "linker": "ld.lld", + "rtlib": "compiler-rt", + "libc": "picolibc", + "automatic-stack-size": true, + "default-stack-size": 2048, + "cflags": [ + "-Werror", + "-fshort-enums", + "-fomit-frame-pointer", + "-mfloat-abi=soft", + "-fno-exceptions", "-fno-unwind-tables", "-fno-asynchronous-unwind-tables", + "-ffunction-sections", "-fdata-sections" + ], + "ldflags": [ + "--emit-relocs", + "--gc-sections" + ], + "extra-files": [ + "src/device/arm/cortexm.S", + "src/internal/task/task_stack_cortexm.S", + "src/runtime/asm_arm.S" + ], + "gdb": ["gdb-multiarch", "arm-none-eabi-gdb", "gdb"] +} diff --git a/targets/cortex-m0.json b/targets/cortex-m0.json new file mode 100644 index 00000000..3df075b1 --- /dev/null +++ b/targets/cortex-m0.json @@ -0,0 +1,6 @@ +{ + "inherits": ["cortex-m"], + "llvm-target": "thumbv6m-unknown-unknown-eabi", + "cpu": "cortex-m0", + "features": "+armv6-m,+soft-float,+strict-align,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-dsp,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-hwdiv,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-neon,-pacbti,-ras,-sb,-sha2,-vfp2,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" +} diff --git a/targets/cortex-m0plus.json b/targets/cortex-m0plus.json new file mode 100644 index 00000000..f1d35ea1 --- /dev/null +++ b/targets/cortex-m0plus.json @@ -0,0 +1,6 @@ +{ + "inherits": ["cortex-m"], + "llvm-target": "thumbv6m-unknown-unknown-eabi", + "cpu": "cortex-m0plus", + "features": "+armv6-m,+soft-float,+strict-align,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-dsp,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-hwdiv,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-neon,-pacbti,-ras,-sb,-sha2,-vfp2,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" +} diff --git a/targets/cortex-m3.json b/targets/cortex-m3.json new file mode 100644 index 00000000..44d992a9 --- /dev/null +++ b/targets/cortex-m3.json @@ -0,0 +1,6 @@ +{ + "inherits": ["cortex-m"], + "llvm-target": "thumbv7m-unknown-unknown-eabi", + "cpu": "cortex-m3", + "features": "+armv7-m,+hwdiv,+soft-float,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-dsp,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-neon,-pacbti,-ras,-sb,-sha2,-vfp2,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" +} diff --git a/targets/cortex-m33.json b/targets/cortex-m33.json new file mode 100644 index 00000000..a5582c08 --- /dev/null +++ b/targets/cortex-m33.json @@ -0,0 +1,6 @@ +{ + "inherits": ["cortex-m"], + "llvm-target": "thumbv8m.main-unknown-unknown-eabi", + "cpu": "cortex-m33", + "features": "+armv8-m.main,+dsp,+hwdiv,+soft-float,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-neon,-pacbti,-ras,-sb,-sha2,-vfp2,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" +} diff --git a/targets/cortex-m4.json b/targets/cortex-m4.json new file mode 100644 index 00000000..80ed66d4 --- /dev/null +++ b/targets/cortex-m4.json @@ -0,0 +1,6 @@ +{ + "inherits": ["cortex-m"], + "llvm-target": "thumbv7em-unknown-unknown-eabi", + "cpu": "cortex-m4", + "features": "+armv7e-m,+dsp,+hwdiv,+soft-float,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-neon,-pacbti,-ras,-sb,-sha2,-vfp2,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" +} diff --git a/targets/cortex-m7.json b/targets/cortex-m7.json new file mode 100644 index 00000000..1a39c6a9 --- /dev/null +++ b/targets/cortex-m7.json @@ -0,0 +1,6 @@ +{ + "inherits": ["cortex-m"], + "llvm-target": "thumbv7em-unknown-unknown-eabi", + "cpu": "cortex-m7", + "features": "+armv7e-m,+dsp,+hwdiv,+soft-float,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-neon,-pacbti,-ras,-sb,-sha2,-vfp2,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" +} diff --git a/targets/d1mini.json b/targets/d1mini.json new file mode 100644 index 00000000..45116dec --- /dev/null +++ b/targets/d1mini.json @@ -0,0 +1,3 @@ +{ + "inherits": ["nodemcu"] +} diff --git a/targets/digispark.json b/targets/digispark.json new file mode 100644 index 00000000..b2a29d67 --- /dev/null +++ b/targets/digispark.json @@ -0,0 +1,10 @@ +{ + "inherits": ["attiny85"], + "build-tags": ["digispark"], + "ldflags": [ + "--defsym=_bootloader_size=2180", + "--defsym=_stack_size=128" + ], + "flash-command": "micronucleus --run {hex}", + "emulator": "simavr -m attiny85 -f 16000000 {}" +} diff --git a/targets/elecrow-rp2040.json b/targets/elecrow-rp2040.json new file mode 100644 index 00000000..46feadc4 --- /dev/null +++ b/targets/elecrow-rp2040.json @@ -0,0 +1,12 @@ +{ + "inherits": ["rp2040"], + "build-tags": ["elecrow_rp2040", "comboat_fw"], + "serial-port": ["2e8a:000a"], + "default-stack-size": 8192, + "ldflags": [ + "--defsym=__flash_size=8M" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/elecrow-rp2350.json b/targets/elecrow-rp2350.json new file mode 100644 index 00000000..75876ed5 --- /dev/null +++ b/targets/elecrow-rp2350.json @@ -0,0 +1,12 @@ +{ + "inherits": ["rp2350"], + "build-tags": ["elecrow_rp2350", "comboat_fw"], + "serial-port": ["2e8a:000f"], + "default-stack-size": 8192, + "ldflags": [ + "--defsym=__flash_size=8M" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/esp-c3-32s-kit.json b/targets/esp-c3-32s-kit.json new file mode 100644 index 00000000..6f787e7d --- /dev/null +++ b/targets/esp-c3-32s-kit.json @@ -0,0 +1,5 @@ +{ + "inherits": ["esp32c3"], + "build-tags": ["esp_c3_32s_kit"], + "serial-port": ["1a86:7523"] +} diff --git a/targets/esp32-c3-devkit-rust-1.json b/targets/esp32-c3-devkit-rust-1.json new file mode 100644 index 00000000..21d6909b --- /dev/null +++ b/targets/esp32-c3-devkit-rust-1.json @@ -0,0 +1,4 @@ +{ + "inherits": ["esp32c3"], + "build-tags": ["esp32_c3_devkit_rust_1"] +} diff --git a/targets/esp32-coreboard-v2.json b/targets/esp32-coreboard-v2.json new file mode 100644 index 00000000..6d15bddb --- /dev/null +++ b/targets/esp32-coreboard-v2.json @@ -0,0 +1,4 @@ +{ + "inherits": ["esp32"], + "build-tags": ["esp32_coreboard_v2"] +} diff --git a/targets/esp32-mini32.json b/targets/esp32-mini32.json new file mode 100644 index 00000000..78dc3904 --- /dev/null +++ b/targets/esp32-mini32.json @@ -0,0 +1,3 @@ +{ + "inherits": ["esp32-coreboard-v2"] +} diff --git a/targets/esp32.json b/targets/esp32.json new file mode 100644 index 00000000..f49282fd --- /dev/null +++ b/targets/esp32.json @@ -0,0 +1,21 @@ +{ + "inherits": ["xtensa"], + "cpu": "esp32", + "features": "+atomctl,+bool,+clamps,+coprocessor,+debug,+density,+dfpaccel,+div32,+exception,+fp,+highpriinterrupts,+interrupt,+loop,+mac16,+memctl,+minmax,+miscsr,+mul32,+mul32high,+nsa,+prid,+regprotect,+rvector,+s32c1i,+sext,+threadptr,+timerint,+windowed", + "build-tags": ["esp32", "esp"], + "scheduler": "tasks", + "serial": "uart", + "linker": "ld.lld", + "default-stack-size": 2048, + "rtlib": "compiler-rt", + "libc": "picolibc", + "linkerscript": "targets/esp32.ld", + "extra-files": [ + "src/device/esp/esp32.S", + "src/internal/task/task_stack_esp32.S" + ], + "binary-format": "esp32", + "flash-command": "esptool.py --chip=esp32 --port {port} write_flash 0x1000 {bin} -ff 80m -fm dout", + "emulator": "qemu-system-xtensa -machine esp32 -nographic -drive file={img},if=mtd,format=raw", + "gdb": ["xtensa-esp32-elf-gdb"] +} diff --git a/targets/esp32.ld b/targets/esp32.ld new file mode 100644 index 00000000..6818ce31 --- /dev/null +++ b/targets/esp32.ld @@ -0,0 +1,202 @@ +/* Linker script for the ESP32 */ + +MEMORY +{ + /* Data RAM. Allows byte access. + * There are various data RAM regions: + * SRAM2: 0x3FFA_E000..0x3FFD_FFFF (72 + 128 = 200K) + * SRAM1: 0x3FFE_0000..0x3FFF_FFFF (128K) + * This gives us 328K of contiguous RAM, which is the largest span possible. + * SRAM1 has other addresses as well but the datasheet seems to indicate + * these are aliases. + */ + DRAM (rw) : ORIGIN = 0x3FFAE000, LENGTH = 200K + 128K /* Internal SRAM 1 + 2 */ + + /* Instruction RAM. */ + IRAM (x) : ORIGIN = 0x40080000, LENGTH = 128K /* Internal SRAM 0 */ +} + +/* The entry point. It is set in the image flashed to the chip, so must be + * defined. + */ +ENTRY(call_start_cpu0) + +SECTIONS +{ + /* Constant literals and code. Loaded into IRAM for now. Eventually, most + * code should be executed directly from flash. + * Note that literals must be before code for the l32r instruction to work. + */ + .text : ALIGN(4) + { + *(.literal.call_start_cpu0) + *(.text.call_start_cpu0) + *(.literal .text) + *(.literal.* .text.*) + } >IRAM + + /* Put the stack at the bottom of DRAM, so that the application will + * crash on stack overflow instead of silently corrupting memory. + * See: http://blog.japaric.io/stack-overflow-protection/ */ + .stack (NOLOAD) : + { + . = ALIGN(16); + . += _stack_size; + _stack_top = .; + } >DRAM + + /* Constant global variables. + * They are loaded in DRAM for ease of use. Eventually they should be stored + * in flash and loaded directly from there but they're kept in RAM to make + * sure they can always be accessed (even in interrupts). + */ + .rodata : ALIGN(4) + { + *(.rodata) + *(.rodata.*) + } >DRAM + + /* Mutable global variables. + */ + .data : ALIGN(4) + { + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + _edata = ABSOLUTE(.); + } >DRAM + + /* Check that the boot ROM stack (for the APP CPU) does not overlap with the + * data that is loaded by the boot ROM. There may be ways to avoid this + * issue if it occurs in practice. + * The magic value here is _stack_sentry in the boot ROM ELF file. + */ + ASSERT(_edata < 0x3ffe1320, "the .data section overlaps with the stack used by the boot ROM, possibly causing corruption at startup") + + /* Global variables that are mutable and zero-initialized. + * These must be zeroed at startup (unlike data, which is loaded by the + * bootloader). + */ + .bss (NOLOAD) : ALIGN(4) + { + . = ALIGN (4); + _sbss = ABSOLUTE(.); + *(.bss) + *(.bss.*) + . = ALIGN (4); + _ebss = ABSOLUTE(.); + } >DRAM +} + +/* For the garbage collector. + */ +_globals_start = _sdata; +_globals_end = _ebss; +_heap_start = _ebss; +_heap_end = ORIGIN(DRAM) + LENGTH(DRAM); + +_stack_size = 4K; + +/* From ESP-IDF: + * components/esp_rom/esp32/ld/esp32.rom.newlib-funcs.ld + * This is the subset that is sometimes used by LLVM during codegen, and thus + * must always be present. + */ +memcpy = 0x4000c2c8; +memmove = 0x4000c3c0; +memset = 0x4000c44c; + +/* From ESP-IDF: + * components/esp_rom/esp32/ld/esp32.rom.libgcc.ld + * These are called from LLVM during codegen. The original license is Apache + * 2.0, but I believe that a list of function names and addresses can't really + * be copyrighted. + */ +__absvdi2 = 0x4006387c; +__absvsi2 = 0x40063868; +__adddf3 = 0x40002590; +__addsf3 = 0x400020e8; +__addvdi3 = 0x40002cbc; +__addvsi3 = 0x40002c98; +__ashldi3 = 0x4000c818; +__ashrdi3 = 0x4000c830; +__bswapdi2 = 0x40064b08; +__bswapsi2 = 0x40064ae0; +__clrsbdi2 = 0x40064b7c; +__clrsbsi2 = 0x40064b64; +__clzdi2 = 0x4000ca50; +__clzsi2 = 0x4000c7e8; +__cmpdi2 = 0x40063820; +__ctzdi2 = 0x4000ca64; +__ctzsi2 = 0x4000c7f0; +__divdc3 = 0x400645a4; +__divdf3 = 0x40002954; +__divdi3 = 0x4000ca84; +__divsi3 = 0x4000c7b8; +__eqdf2 = 0x400636a8; +__eqsf2 = 0x40063374; +__extendsfdf2 = 0x40002c34; +__ffsdi2 = 0x4000ca2c; +__ffssi2 = 0x4000c804; +__fixdfdi = 0x40002ac4; +__fixdfsi = 0x40002a78; +__fixsfdi = 0x4000244c; +__fixsfsi = 0x4000240c; +__fixunsdfsi = 0x40002b30; +__fixunssfdi = 0x40002504; +__fixunssfsi = 0x400024ac; +__floatdidf = 0x4000c988; +__floatdisf = 0x4000c8c0; +__floatsidf = 0x4000c944; +__floatsisf = 0x4000c870; +__floatundidf = 0x4000c978; +__floatundisf = 0x4000c8b0; +__floatunsidf = 0x4000c938; +__floatunsisf = 0x4000c864; +__gcc_bcmp = 0x40064a70; +__gedf2 = 0x40063768; +__gesf2 = 0x4006340c; +__gtdf2 = 0x400636dc; +__gtsf2 = 0x400633a0; +__ledf2 = 0x40063704; +__lesf2 = 0x400633c0; +__lshrdi3 = 0x4000c84c; +__ltdf2 = 0x40063790; +__ltsf2 = 0x4006342c; +__moddi3 = 0x4000cd4c; +__modsi3 = 0x4000c7c0; +__muldc3 = 0x40063c90; +__muldf3 = 0x4006358c; +__muldi3 = 0x4000c9fc; +__mulsf3 = 0x400632c8; +__mulsi3 = 0x4000c7b0; +__mulvdi3 = 0x40002d78; +__mulvsi3 = 0x40002d60; +__nedf2 = 0x400636a8; +__negdf2 = 0x400634a0; +__negdi2 = 0x4000ca14; +__negsf2 = 0x400020c0; +__negvdi2 = 0x40002e98; +__negvsi2 = 0x40002e78; +__nesf2 = 0x40063374; +__nsau_data = 0x3ff96544; +__paritysi2 = 0x40002f3c; +__popcount_tab = 0x3ff96544; +__popcountdi2 = 0x40002ef8; +__popcountsi2 = 0x40002ed0; +__powidf2 = 0x400638e4; +__subdf3 = 0x400026e4; +__subsf3 = 0x400021d0; +__subvdi3 = 0x40002d20; +__subvsi3 = 0x40002cf8; +__truncdfsf2 = 0x40002b90; +__ucmpdi2 = 0x40063840; +__udiv_w_sdiv = 0x40064bec; +__udivdi3 = 0x4000cff8; +__udivmoddi4 = 0x40064bf4; +__udivsi3 = 0x4000c7c8; +__umoddi3 = 0x4000d280; +__umodsi3 = 0x4000c7d0; +__umulsidi3 = 0x4000c7d8; +__unorddf2 = 0x400637f4; +__unordsf2 = 0x40063478; diff --git a/targets/esp32c3-12f.json b/targets/esp32c3-12f.json new file mode 100644 index 00000000..371cacc7 --- /dev/null +++ b/targets/esp32c3-12f.json @@ -0,0 +1,5 @@ +{ + "inherits": ["esp32c3"], + "build-tags": ["esp32c312f"] +} + diff --git a/targets/esp32c3-supermini.json b/targets/esp32c3-supermini.json new file mode 100644 index 00000000..3e4e4089 --- /dev/null +++ b/targets/esp32c3-supermini.json @@ -0,0 +1,4 @@ +{ + "inherits": ["esp32c3"], + "build-tags": ["esp32c3_supermini"] +} diff --git a/targets/esp32c3.json b/targets/esp32c3.json new file mode 100644 index 00000000..900c4845 --- /dev/null +++ b/targets/esp32c3.json @@ -0,0 +1,23 @@ +{ + "inherits": ["riscv32"], + "features": "+32bit,+c,+m,+zmmul,-a,-b,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-f,-h,-relax,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xesppie,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b", + "build-tags": ["esp32c3", "esp"], + "serial": "usb", + "rtlib": "compiler-rt", + "libc": "picolibc", + "cflags": [ + "-march=rv32imc" + ], + "linkerscript": "targets/esp32c3.ld", + "extra-files": [ + "src/device/esp/esp32c3.S" + ], + "binary-format": "esp32c3", + "flash-command": "esptool.py --chip=esp32c3 --port {port} write_flash 0x0 {bin}", + "serial-port": ["303a:1001"], + "openocd-interface": "esp_usb_jtag", + "openocd-target": "esp32c3", + "openocd-commands": ["gdb_memory_map disable"], + "gdb": ["riscv32-esp-elf-gdb"] +} + diff --git a/targets/esp32c3.ld b/targets/esp32c3.ld new file mode 100644 index 00000000..81a8c4f2 --- /dev/null +++ b/targets/esp32c3.ld @@ -0,0 +1,2238 @@ +/* Linker script for the ESP32-C3 + * + * The ESP32-C3 has a rather funky memory layout, more like its Xtensa + * predecessors than like other RISC-V chips: + * - It has 384kB of regular RAM. This RAM can be used both as data RAM and + * instruction RAM, but needs to be accessed via a different address space + * (DRAM/IRAM). + * - It has another 16kB of RAM, that could be used as regular RAM but is + * normally used by the flash cache. + * - It has 8MB of address space for the DROM and IROM, but for some reason + * this address space is shared. So it isn't possible to map all DROM at + * 0x3C000000 and all DRAM at 0x42000000: they would overlap. + * - The MMU works in pages of 64kB, which means the bottom 16 bits of the + * address in flash and the address in DROM/IROM need to match. + * - Memory in DRAM and IRAM is loaded at reset by the ROM bootloader. + * Luckily, this doesn't have significant alignment requirements. + * + * This linker script has been written to carefully work around (or with) these + * limitations: + * - It adds dummy sections so that the bottom 16 bits of the virtual address + * and the physical address (in the generated firmware image) match. + * - It also offsets sections that share an address space using those same + * dummy sections. + * - It sorts the sections by load address, to avoid surprises as esptool.py + * also does it. + * This way, it's possible to create a very small firmware image that still + * conforms to the expectations of esptool.py and the ROM bootloader. + */ + +MEMORY +{ + /* Note: DRAM and IRAM below are actually in the same 384K address space. */ + DRAM (rw) : ORIGIN = 0x3FC80000, LENGTH = 384K /* Internal SRAM 1 (data bus) */ + IRAM (x) : ORIGIN = 0x40380000, LENGTH = 384K /* Internal SRAM 1 (instruction bus) */ + + /* Note: DROM and IROM below are actually in the same 8M address space. */ + DROM (r) : ORIGIN = 0x3C000000, LENGTH = 8M /* Data bus (read-only) */ + IROM (rx) : ORIGIN = 0x42000000, LENGTH = 8M /* Instruction bus */ +} + +/* The entry point. It is set in the image flashed to the chip, so must be + * defined. + */ +ENTRY(call_start_cpu0) + +SECTIONS +{ + /* Dummy section to make sure the .rodata section starts exactly behind the + * image header. + */ + .rodata_dummy (NOLOAD): ALIGN(4) + { + . += 0x18; /* image header at start of flash: esp_image_header_t */ + . += 0x8; /* DROM segment header (8 bytes) */ + } > DROM + + /* Constant global variables, stored in DROM. + */ + .rodata : ALIGN(4) + { + *(.rodata*) + . = ALIGN (4); + } >DROM + + /* Put the stack at the bottom of DRAM, so that the application will + * crash on stack overflow instead of silently corrupting memory. + * See: http://blog.japaric.io/stack-overflow-protection/ + * TODO: this might not actually work because memory protection hasn't been set up. + */ + .stack (NOLOAD) : + { + . = ALIGN(16); + . += _stack_size; + _stack_top = .; + } >DRAM + + /* Global variables that are mutable and zero-initialized. + * These must be zeroed at startup (unlike data, which is loaded by the + * bootloader). + */ + .bss (NOLOAD) : ALIGN(4) + { + . = ALIGN (4); + _sbss = ABSOLUTE(.); + *(.sbss) + *(.bss .bss.*) + . = ALIGN (4); + _ebss = ABSOLUTE(.); + } >DRAM + + /* Mutable global variables. This data (in the DRAM segment) is initialized + * by the ROM bootloader. + */ + .data : ALIGN(4) + { + . = ALIGN (4); + _sdata = ABSOLUTE(.); + *(.sdata) + *(.data .data.*) + *(.dram*) + . = ALIGN (4); + _edata = ABSOLUTE(.); + } >DRAM + + /* Dummy section to make sure the .init section (in the IRAM segment) is just + * behind the DRAM segment. For IRAM and DRAM, we luckily don't have to + * worry about 64kB pages or image headers as they're loaded in RAM by the + * bootloader (not mapped from flash). + */ + .iram_dummy (NOLOAD): ALIGN(4) + { + . += SIZEOF(.stack); + . += SIZEOF(.bss); + . += SIZEOF(.data); + } > IRAM + + /* IRAM segment. This contains some functions that always need to be loaded + * in IRAM, and contains initialization code. + * The initialization code is later reclaimed for the heap, so no RAM is + * wasted. + */ + .iram : ALIGN(4) + { + *(.iram*) + *(.wifislprxiram*) + *(.wifiextrairam*) + *(.wifi0iram*) + *(.wifislpiram*) + *(.wifirxiram*) + __init_start = .; + *(.init) + __init_end = .; + } >IRAM + + /* Dummy section to put the IROM segment exactly behind the IRAM segment. + * This has to follow the app image format exactly. + */ + .text_dummy (NOLOAD): ALIGN(4) + { + /* Note: DRAM and DROM are not always present so the header should only + * be inserted if it actually exists. + */ + . += 0x18; /* esp_image_header_t */ + . += SIZEOF(.rodata) + ((SIZEOF(.rodata) != 0) ? 0x8 : 0); /* DROM segment (optional) */ + . += SIZEOF(.data) + ((SIZEOF(.data) != 0) ? 0x8 : 0); /* DRAM segment (optional) */ + . += SIZEOF(.iram) + 0x8; /* IRAM segment */ + . += 0x8; /* IROM segment header */ + } > IROM + + /* IROM segment. This contains all the actual code and is placed right after + * the DROM segment. + */ + .text : ALIGN(4) + { + . = ALIGN (256); + *(.text.exception_vectors) + . = ALIGN (4); + *(.text .text.*) + } >IROM + + /DISCARD/ : + { + *(.eh_frame) /* causes 'no memory region specified' error in lld */ + } + + /* Check that the boot ROM stack (for the APP CPU) does not overlap with the + * data that is loaded by the boot ROM. This is unlikely to happen in + * practice. + * The magic value comes from here: + * https://github.com/espressif/esp-idf/blob/61299f879e/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld#L191 + */ + ASSERT((_edata + SIZEOF(.iram)) < 0x3FCDE710, "the .iram section overlaps with the stack used by the boot ROM, possibly causing corruption at startup") +} + +/* For the garbage collector. + * Note that _heap_start starts after _edata + most of the IRAM section. + * It starts just before the initialisation code, which isn't necessary anymore + * after startup and can thus be overwritten by the heap. + */ +_globals_start = _sbss; +_globals_end = _edata; +_heap_start = _edata + SIZEOF(.iram) - (__init_end - __init_start); +_heap_end = ORIGIN(DRAM) + LENGTH(DRAM); + +_stack_size = 4K; + +/* ROM functions used for setting up the flash mapping. + */ +Cache_Invalidate_ICache_All = 0x400004d8; +Cache_Suspend_ICache = 0x40000524; +Cache_Resume_ICache = 0x40000528; +Cache_MMU_Init = 0x4000055c; +Cache_Dbus_MMU_Set = 0x40000564; + +/* From ESP-IDF: + * components/esp_rom/esp32c3/ld/esp32c3.rom.libgcc.ld + * These are called from LLVM during codegen. The original license is Apache + * 2.0. + */ +__absvdi2 = 0x40000764; +__absvsi2 = 0x40000768; +__adddf3 = 0x4000076c; +__addsf3 = 0x40000770; +__addvdi3 = 0x40000774; +__addvsi3 = 0x40000778; +__ashldi3 = 0x4000077c; +__ashrdi3 = 0x40000780; +__bswapdi2 = 0x40000784; +__bswapsi2 = 0x40000788; +__clear_cache = 0x4000078c; +__clrsbdi2 = 0x40000790; +__clrsbsi2 = 0x40000794; +__clzdi2 = 0x40000798; +__clzsi2 = 0x4000079c; +__cmpdi2 = 0x400007a0; +__ctzdi2 = 0x400007a4; +__ctzsi2 = 0x400007a8; +__divdc3 = 0x400007ac; +__divdf3 = 0x400007b0; +__divdi3 = 0x400007b4; +__divsc3 = 0x400007b8; +__divsf3 = 0x400007bc; +__divsi3 = 0x400007c0; +__eqdf2 = 0x400007c4; +__eqsf2 = 0x400007c8; +__extendsfdf2 = 0x400007cc; +__ffsdi2 = 0x400007d0; +__ffssi2 = 0x400007d4; +__fixdfdi = 0x400007d8; +__fixdfsi = 0x400007dc; +__fixsfdi = 0x400007e0; +__fixsfsi = 0x400007e4; +__fixunsdfsi = 0x400007e8; +__fixunssfdi = 0x400007ec; +__fixunssfsi = 0x400007f0; +__floatdidf = 0x400007f4; +__floatdisf = 0x400007f8; +__floatsidf = 0x400007fc; +__floatsisf = 0x40000800; +__floatundidf = 0x40000804; +__floatundisf = 0x40000808; +__floatunsidf = 0x4000080c; +__floatunsisf = 0x40000810; +__gcc_bcmp = 0x40000814; +__gedf2 = 0x40000818; +__gesf2 = 0x4000081c; +__gtdf2 = 0x40000820; +__gtsf2 = 0x40000824; +__ledf2 = 0x40000828; +__lesf2 = 0x4000082c; +__lshrdi3 = 0x40000830; +__ltdf2 = 0x40000834; +__ltsf2 = 0x40000838; +__moddi3 = 0x4000083c; +__modsi3 = 0x40000840; +__muldc3 = 0x40000844; +__muldf3 = 0x40000848; +__muldi3 = 0x4000084c; +__mulsc3 = 0x40000850; +__mulsf3 = 0x40000854; +__mulsi3 = 0x40000858; +__mulvdi3 = 0x4000085c; +__mulvsi3 = 0x40000860; +__nedf2 = 0x40000864; +__negdf2 = 0x40000868; +__negdi2 = 0x4000086c; +__negsf2 = 0x40000870; +__negvdi2 = 0x40000874; +__negvsi2 = 0x40000878; +__nesf2 = 0x4000087c; +__paritysi2 = 0x40000880; +__popcountdi2 = 0x40000884; +__popcountsi2 = 0x40000888; +__powidf2 = 0x4000088c; +__powisf2 = 0x40000890; +__subdf3 = 0x40000894; +__subsf3 = 0x40000898; +__subvdi3 = 0x4000089c; +__subvsi3 = 0x400008a0; +__truncdfsf2 = 0x400008a4; +__ucmpdi2 = 0x400008a8; +__udivdi3 = 0x400008ac; +__udivmoddi4 = 0x400008b0; +__udivsi3 = 0x400008b4; +__udiv_w_sdiv = 0x400008b8; +__umoddi3 = 0x400008bc; +__umodsi3 = 0x400008c0; +__unorddf2 = 0x400008c4; +__unordsf2 = 0x400008c8; + +/* From ESP-IDF: + * components/esp_rom/esp32c3/ld/esp32c3.rom.newlib.ld + * These are called during codegen and thus it's a good idea to make them always + * available. ROM functions may also be faster than functions in IROM (that go + * through the flash cache) and are always available in interrupts. + */ +memset = 0x40000354; +memcpy = 0x40000358; +memmove = 0x4000035c; + + +/* From ESP-IDF: + * components/esp_rom/esp32c3/ld/esp32c3.rom.ld + * These are needed for wifi/BLE support and are available on the Apache 2.0 + * license. + */ +/* ROM function interface esp32c3.rom.ld for esp32c3 + * + * + * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +analog_super_wdt_reset_happened = 0x4000001c; +jtag_cpu_reset_happened = 0x40000020; +rtc_get_wakeup_cause = 0x40000024; +rtc_boot_control = 0x40000028; +rtc_select_apb_bridge = 0x4000002c; +rtc_unhold_all_pads = 0x40000030; +set_rtc_memory_crc = 0x40000034; +cacl_rtc_memory_crc = 0x40000038; +ets_is_print_boot = 0x4000003c; +ets_printf = 0x40000040; +ets_install_putc1 = 0x40000044; +ets_install_uart_printf = 0x40000048; +ets_install_putc2 = 0x4000004c; +PROVIDE( ets_delay_us = 0x40000050 ); +ets_get_stack_info = 0x40000054; +ets_install_lock = 0x40000058; +ets_backup_dma_copy = 0x4000005c; +ets_apb_backup_init_lock_func = 0x40000060; +UartRxString = 0x40000064; +uart_tx_one_char = 0x40000068; +uart_tx_one_char2 = 0x4000006c; +uart_rx_one_char = 0x40000070; +uart_rx_one_char_block = 0x40000074; +uart_rx_readbuff = 0x40000078; +uartAttach = 0x4000007c; +uart_tx_flush = 0x40000080; +uart_tx_wait_idle = 0x40000084; +uart_div_modify = 0x40000088; +multofup = 0x4000008c; +software_reset = 0x40000090; +software_reset_cpu = 0x40000094; +assist_debug_clock_enable = 0x40000098; +assist_debug_record_enable = 0x4000009c; +clear_super_wdt_reset_flag = 0x400000a0; +disable_default_watchdog = 0x400000a4; +send_packet = 0x400000a8; +recv_packet = 0x400000ac; +GetUartDevice = 0x400000b0; +UartDwnLdProc = 0x400000b4; +Uart_Init = 0x400000b8; +ets_set_user_start = 0x400000bc; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x3ff1fffc; +ets_ops_table_ptr = 0x3fcdfffc; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000c0; +mz_crc32 = 0x400000c4; +mz_free = 0x400000c8; +tdefl_compress = 0x400000cc; +tdefl_compress_buffer = 0x400000d0; +tdefl_compress_mem_to_heap = 0x400000d4; +tdefl_compress_mem_to_mem = 0x400000d8; +tdefl_compress_mem_to_output = 0x400000dc; +tdefl_get_adler32 = 0x400000e0; +tdefl_get_prev_return_status = 0x400000e4; +tdefl_init = 0x400000e8; +tdefl_write_image_to_png_file_in_memory = 0x400000ec; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f0; +tinfl_decompress = 0x400000f4; +tinfl_decompress_mem_to_callback = 0x400000f8; +tinfl_decompress_mem_to_heap = 0x400000fc; +tinfl_decompress_mem_to_mem = 0x40000100; + + +/*************************************** + Group tjpgd + ***************************************/ + +/* Functions */ +PROVIDE( jd_prepare = 0x40000104 ); +PROVIDE( jd_decomp = 0x40000108 ); + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +PROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c ); +PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000110 ); +PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000114 ); +PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000118 ); +PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000011c ); +PROVIDE( esp_rom_spiflash_erase_chip = 0x40000120 ); +PROVIDE( esp_rom_spiflash_erase_block = 0x40000124 ); +PROVIDE( esp_rom_spiflash_erase_sector = 0x40000128 ); +PROVIDE( esp_rom_spiflash_write = 0x4000012c ); +PROVIDE( esp_rom_spiflash_read = 0x40000130 ); +PROVIDE( esp_rom_spiflash_config_param = 0x40000134 ); +PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000138 ); +PROVIDE( esp_rom_spiflash_select_qio_pins = 0x4000013c ); +PROVIDE( esp_rom_spiflash_unlock = 0x40000140 ); +PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000144 ); +PROVIDE( esp_rom_spi_flash_send_resume = 0x40000148 ); +PROVIDE( esp_rom_spi_flash_update_id = 0x4000014c ); +PROVIDE( esp_rom_spiflash_config_clk = 0x40000150 ); +PROVIDE( esp_rom_spiflash_config_readmode = 0x40000154 ); +PROVIDE( esp_rom_spiflash_read_status = 0x40000158 ); +PROVIDE( esp_rom_spiflash_read_statushigh = 0x4000015c ); +PROVIDE( esp_rom_spiflash_write_status = 0x40000160 ); +PROVIDE( esp_rom_spiflash_attach = 0x40000164 ); +PROVIDE( spi_flash_get_chip_size = 0x40000168 ); +PROVIDE( spi_flash_guard_set = 0x4000016c ); +PROVIDE( spi_flash_guard_get = 0x40000170 ); +PROVIDE( spi_flash_write_config_set = 0x40000174 ); +PROVIDE( spi_flash_write_config_get = 0x40000178 ); +PROVIDE( spi_flash_safe_write_address_func_set = 0x4000017c ); +PROVIDE( spi_flash_unlock = 0x40000180 ); +PROVIDE( spi_flash_erase_range = 0x40000184 ); +PROVIDE( spi_flash_erase_sector = 0x40000188 ); +PROVIDE( spi_flash_write = 0x4000018c ); +PROVIDE( spi_flash_read = 0x40000190 ); +PROVIDE( spi_flash_write_encrypted = 0x40000194 ); +PROVIDE( spi_flash_read_encrypted = 0x40000198 ); +PROVIDE( spi_flash_mmap_os_func_set = 0x4000019c ); +PROVIDE( spi_flash_mmap_page_num_init = 0x400001a0 ); +PROVIDE( spi_flash_mmap = 0x400001a4 ); +PROVIDE( spi_flash_mmap_pages = 0x400001a8 ); +PROVIDE( spi_flash_munmap = 0x400001ac ); +PROVIDE( spi_flash_mmap_dump = 0x400001b0 ); +PROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 ); +PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 ); +PROVIDE( spi_flash_cache2phys = 0x400001bc ); +PROVIDE( spi_flash_phys2cache = 0x400001c0 ); +PROVIDE( spi_flash_disable_cache = 0x400001c4 ); +PROVIDE( spi_flash_restore_cache = 0x400001c8 ); +PROVIDE( spi_flash_cache_enabled = 0x400001cc ); +PROVIDE( spi_flash_enable_cache = 0x400001d0 ); +PROVIDE( spi_cache_mode_switch = 0x400001d4 ); +PROVIDE( spi_common_set_dummy_output = 0x400001d8 ); +PROVIDE( spi_common_set_flash_cs_timing = 0x400001dc ); +PROVIDE( esp_enable_cache_flash_wrap = 0x400001e0 ); +PROVIDE( SPIEraseArea = 0x400001e4 ); +PROVIDE( SPILock = 0x400001e8 ); +PROVIDE( SPIMasterReadModeCnfig = 0x400001ec ); +PROVIDE( SPI_Common_Command = 0x400001f0 ); +PROVIDE( SPI_WakeUp = 0x400001f4 ); +PROVIDE( SPI_block_erase = 0x400001f8 ); +PROVIDE( SPI_chip_erase = 0x400001fc ); +PROVIDE( SPI_init = 0x40000200 ); +PROVIDE( SPI_page_program = 0x40000204 ); +PROVIDE( SPI_read_data = 0x40000208 ); +PROVIDE( SPI_sector_erase = 0x4000020c ); +PROVIDE( SPI_write_enable = 0x40000210 ); +PROVIDE( SelectSpiFunction = 0x40000214 ); +PROVIDE( SetSpiDrvs = 0x40000218 ); +PROVIDE( Wait_SPI_Idle = 0x4000021c ); +PROVIDE( spi_dummy_len_fix = 0x40000220 ); +PROVIDE( Disable_QMode = 0x40000224 ); +PROVIDE( Enable_QMode = 0x40000228 ); +/* Data (.data, .bss, .rodata) */ +PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 ); +PROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 ); +PROVIDE( g_flash_guard_ops = 0x3fcdfff8 ); + + +/*************************************** + Group spi_flash_hal + ***************************************/ + +/* Functions */ +PROVIDE( spi_flash_hal_poll_cmd_done = 0x4000022c ); +PROVIDE( spi_flash_hal_device_config = 0x40000230 ); +PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000234 ); +PROVIDE( spi_flash_hal_common_command = 0x40000238 ); +PROVIDE( spi_flash_hal_read = 0x4000023c ); +PROVIDE( spi_flash_hal_erase_chip = 0x40000240 ); +PROVIDE( spi_flash_hal_erase_sector = 0x40000244 ); +PROVIDE( spi_flash_hal_erase_block = 0x40000248 ); +PROVIDE( spi_flash_hal_program_page = 0x4000024c ); +PROVIDE( spi_flash_hal_set_write_protect = 0x40000250 ); +PROVIDE( spi_flash_hal_host_idle = 0x40000254 ); + + +/*************************************** + Group spi_flash_chips + ***************************************/ + +/* Functions */ +PROVIDE( spi_flash_chip_generic_probe = 0x40000258 ); +PROVIDE( spi_flash_chip_generic_detect_size = 0x4000025c ); +PROVIDE( spi_flash_chip_generic_write = 0x40000260 ); +PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000264 ); +PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000268 ); +PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x4000026c ); +PROVIDE( spi_flash_chip_generic_reset = 0x40000270 ); +PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000274 ); +PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000278 ); +PROVIDE( spi_flash_chip_generic_erase_block = 0x4000027c ); +PROVIDE( spi_flash_chip_generic_page_program = 0x40000280 ); +PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000284 ); +PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000288 ); +PROVIDE( spi_flash_chip_generic_read_reg = 0x4000028c ); +PROVIDE( spi_flash_chip_generic_yield = 0x40000290 ); +PROVIDE( spi_flash_generic_wait_host_idle = 0x40000294 ); +PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000298 ); +PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x4000029c ); +PROVIDE( spi_flash_chip_generic_read = 0x400002a0 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400002a4 ); +PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400002a8 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400002ac ); +PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400002b0 ); +PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400002b4 ); +PROVIDE( spi_flash_common_set_io_mode = 0x400002b8 ); +PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400002bc ); +PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400002c0 ); +PROVIDE( spi_flash_chip_gd_probe = 0x400002c4 ); +PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400002c8 ); +/* Data (.data, .bss, .rodata) */ +PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffec ); + + +/*************************************** + Group memspi_host + ***************************************/ + +/* Functions */ +PROVIDE( memspi_host_read_id_hs = 0x400002cc ); +PROVIDE( memspi_host_read_status_hs = 0x400002d0 ); +PROVIDE( memspi_host_flush_cache = 0x400002d4 ); +PROVIDE( memspi_host_erase_chip = 0x400002d8 ); +PROVIDE( memspi_host_erase_sector = 0x400002dc ); +PROVIDE( memspi_host_erase_block = 0x400002e0 ); +PROVIDE( memspi_host_program_page = 0x400002e4 ); +PROVIDE( memspi_host_read = 0x400002e8 ); +PROVIDE( memspi_host_set_write_protect = 0x400002ec ); +PROVIDE( memspi_host_set_max_read_len = 0x400002f0 ); +PROVIDE( memspi_host_read_data_slicer = 0x400002f4 ); +PROVIDE( memspi_host_write_data_slicer = 0x400002f8 ); + + +/*************************************** + Group esp_flash + ***************************************/ + +/* Functions */ +PROVIDE( esp_flash_chip_driver_initialized = 0x400002fc ); +PROVIDE( esp_flash_read_id = 0x40000300 ); +PROVIDE( esp_flash_get_size = 0x40000304 ); +PROVIDE( esp_flash_erase_chip = 0x40000308 ); +PROVIDE( rom_esp_flash_erase_region = 0x4000030c ); +PROVIDE( esp_flash_get_chip_write_protect = 0x40000310 ); +PROVIDE( esp_flash_set_chip_write_protect = 0x40000314 ); +PROVIDE( esp_flash_get_protectable_regions = 0x40000318 ); +PROVIDE( esp_flash_get_protected_region = 0x4000031c ); +PROVIDE( esp_flash_set_protected_region = 0x40000320 ); +PROVIDE( esp_flash_read = 0x40000324 ); +PROVIDE( esp_flash_write = 0x40000328 ); +PROVIDE( esp_flash_write_encrypted = 0x4000032c ); +PROVIDE( esp_flash_read_encrypted = 0x40000330 ); +PROVIDE( esp_flash_get_io_mode = 0x40000334 ); +PROVIDE( esp_flash_set_io_mode = 0x40000338 ); +PROVIDE( spi_flash_boot_attach = 0x4000033c ); +PROVIDE( spi_flash_dump_counters = 0x40000340 ); +PROVIDE( spi_flash_get_counters = 0x40000344 ); +PROVIDE( spi_flash_op_counters_config = 0x40000348 ); +PROVIDE( spi_flash_reset_counters = 0x4000034c ); +/* Data (.data, .bss, .rodata) */ +PROVIDE( esp_flash_default_chip = 0x3fcdffe8 ); +PROVIDE( esp_flash_api_funcs = 0x3fcdffe4 ); + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +PROVIDE( Cache_Get_ICache_Line_Size = 0x400004b0 ); +PROVIDE( Cache_Get_Mode = 0x400004b4 ); +PROVIDE( Cache_Address_Through_IBus = 0x400004b8 ); +PROVIDE( Cache_Address_Through_DBus = 0x400004bc ); +PROVIDE( Cache_Set_Default_Mode = 0x400004c0 ); +PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004c4 ); +PROVIDE( ROM_Boot_Cache_Init = 0x400004c8 ); +PROVIDE( Cache_Invalidate_ICache_Items = 0x400004cc ); +PROVIDE( Cache_Op_Addr = 0x400004d0 ); +PROVIDE( Cache_Invalidate_Addr = 0x400004d4 ); +PROVIDE( Cache_Invalidate_ICache_All = 0x400004d8 ); +PROVIDE( Cache_Mask_All = 0x400004dc ); +PROVIDE( Cache_UnMask_Dram0 = 0x400004e0 ); +PROVIDE( Cache_Suspend_ICache_Autoload = 0x400004e4 ); +PROVIDE( Cache_Resume_ICache_Autoload = 0x400004e8 ); +PROVIDE( Cache_Start_ICache_Preload = 0x400004ec ); +PROVIDE( Cache_ICache_Preload_Done = 0x400004f0 ); +PROVIDE( Cache_End_ICache_Preload = 0x400004f4 ); +PROVIDE( Cache_Config_ICache_Autoload = 0x400004f8 ); +PROVIDE( Cache_Enable_ICache_Autoload = 0x400004fc ); +PROVIDE( Cache_Disable_ICache_Autoload = 0x40000500 ); +PROVIDE( Cache_Enable_ICache_PreLock = 0x40000504 ); +PROVIDE( Cache_Disable_ICache_PreLock = 0x40000508 ); +PROVIDE( Cache_Lock_ICache_Items = 0x4000050c ); +PROVIDE( Cache_Unlock_ICache_Items = 0x40000510 ); +PROVIDE( Cache_Lock_Addr = 0x40000514 ); +PROVIDE( Cache_Unlock_Addr = 0x40000518 ); +PROVIDE( Cache_Disable_ICache = 0x4000051c ); +PROVIDE( Cache_Enable_ICache = 0x40000520 ); +PROVIDE( Cache_Suspend_ICache = 0x40000524 ); +PROVIDE( Cache_Resume_ICache = 0x40000528 ); +PROVIDE( Cache_Freeze_ICache_Enable = 0x4000052c ); +PROVIDE( Cache_Freeze_ICache_Disable = 0x40000530 ); +PROVIDE( Cache_Pms_Lock = 0x40000534 ); +PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000538 ); +PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x4000053c ); +PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000540 ); +PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000544 ); +PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000548 ); +PROVIDE( Cache_Get_IROM_MMU_End = 0x4000054c ); +PROVIDE( Cache_Get_DROM_MMU_End = 0x40000550 ); +PROVIDE( Cache_Owner_Init = 0x40000554 ); +PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000558 ); +PROVIDE( Cache_MMU_Init = 0x4000055c ); +PROVIDE( Cache_Ibus_MMU_Set = 0x40000560 ); +PROVIDE( Cache_Dbus_MMU_Set = 0x40000564 ); +PROVIDE( Cache_Count_Flash_Pages = 0x40000568 ); +PROVIDE( Cache_Travel_Tag_Memory = 0x4000056c ); +PROVIDE( Cache_Get_Virtual_Addr = 0x40000570 ); +PROVIDE( Cache_Get_Memory_BaseAddr = 0x40000574 ); +PROVIDE( Cache_Get_Memory_Addr = 0x40000578 ); +PROVIDE( Cache_Get_Memory_value = 0x4000057c ); +/* Data (.data, .bss, .rodata) */ +PROVIDE( rom_cache_op_cb = 0x3fcdffd8 ); +PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd4 ); + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_get_apb_freq = 0x40000580; +ets_get_cpu_frequency = 0x40000584; +ets_update_cpu_frequency = 0x40000588; +ets_get_printf_channel = 0x4000058c; +ets_get_xtal_div = 0x40000590; +ets_set_xtal_div = 0x40000594; +ets_get_xtal_freq = 0x40000598; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_input_get = 0x4000059c; +gpio_matrix_in = 0x400005a0; +gpio_matrix_out = 0x400005a4; +gpio_output_disable = 0x400005a8; +gpio_output_enable = 0x400005ac; +gpio_output_set = 0x400005b0; +gpio_pad_hold = 0x400005b4; +gpio_pad_input_disable = 0x400005b8; +gpio_pad_input_enable = 0x400005bc; +gpio_pad_pulldown = 0x400005c0; +gpio_pad_pullup = 0x400005c4; +gpio_pad_select_gpio = 0x400005c8; +gpio_pad_set_drv = 0x400005cc; +gpio_pad_unhold = 0x400005d0; +gpio_pin_wakeup_disable = 0x400005d4; +gpio_pin_wakeup_enable = 0x400005d8; +gpio_bypass_matrix_in = 0x400005dc; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x400005e0; +esprv_intc_int_set_threshold = 0x400005e4; +esprv_intc_int_enable = 0x400005e8; +esprv_intc_int_disable = 0x400005ec; +esprv_intc_int_set_type = 0x400005f0; +intr_matrix_set = 0x400005f4; +ets_intr_lock = 0x400005f8; +ets_intr_unlock = 0x400005fc; +PROVIDE( intr_handler_set = 0x40000600 ); +ets_isr_attach = 0x40000604; +ets_isr_mask = 0x40000608; +ets_isr_unmask = 0x4000060c; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x40000610; +MD5Init = 0x40000614; +MD5Update = 0x40000618; +MD5Final = 0x4000061c; +hmac_md5_vector = 0x40000620; +hmac_md5 = 0x40000624; +crc32_le = 0x40000628; +crc32_be = 0x4000062c; +crc16_le = 0x40000630; +crc16_be = 0x40000634; +crc8_le = 0x40000638; +crc8_be = 0x4000063c; +esp_crc8 = 0x40000640; +ets_sha_enable = 0x40000644; +ets_sha_disable = 0x40000648; +ets_sha_get_state = 0x4000064c; +ets_sha_init = 0x40000650; +ets_sha_process = 0x40000654; +ets_sha_starts = 0x40000658; +ets_sha_update = 0x4000065c; +ets_sha_finish = 0x40000660; +ets_sha_clone = 0x40000664; +ets_hmac_enable = 0x40000668; +ets_hmac_disable = 0x4000066c; +ets_hmac_calculate_message = 0x40000670; +ets_hmac_calculate_downstream = 0x40000674; +ets_hmac_invalidate_downstream = 0x40000678; +ets_jtag_enable_temporarily = 0x4000067c; +ets_aes_enable = 0x40000680; +ets_aes_disable = 0x40000684; +ets_aes_setkey = 0x40000688; +ets_aes_block = 0x4000068c; +ets_bigint_enable = 0x40000690; +ets_bigint_disable = 0x40000694; +ets_bigint_multiply = 0x40000698; +ets_bigint_modmult = 0x4000069c; +ets_bigint_modexp = 0x400006a0; +ets_bigint_wait_finish = 0x400006a4; +ets_bigint_getz = 0x400006a8; +ets_ds_enable = 0x400006ac; +ets_ds_disable = 0x400006b0; +ets_ds_start_sign = 0x400006b4; +ets_ds_is_busy = 0x400006b8; +ets_ds_finish_sign = 0x400006bc; +ets_ds_encrypt_params = 0x400006c0; +ets_aes_setkey_dec = 0x400006c4; +ets_aes_setkey_enc = 0x400006c8; +ets_mgf1_sha256 = 0x400006cc; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x400006d0; +ets_efuse_program = 0x400006d4; +ets_efuse_clear_program_registers = 0x400006d8; +ets_efuse_write_key = 0x400006dc; +ets_efuse_get_read_register_address = 0x400006e0; +ets_efuse_get_key_purpose = 0x400006e4; +ets_efuse_key_block_unused = 0x400006e8; +ets_efuse_find_unused_key_block = 0x400006ec; +ets_efuse_rs_calculate = 0x400006f0; +ets_efuse_count_unused_key_blocks = 0x400006f4; +ets_efuse_secure_boot_enabled = 0x400006f8; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400006fc; +ets_efuse_cache_encryption_enabled = 0x40000700; +ets_efuse_download_modes_disabled = 0x40000704; +ets_efuse_find_purpose = 0x40000708; +ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x4000070c; +ets_efuse_force_send_resume = 0x40000710; +ets_efuse_get_flash_delay_us = 0x40000714; +ets_efuse_get_mac = 0x40000718; +ets_efuse_get_spiconfig = 0x4000071c; +ets_efuse_usb_print_is_disabled = 0x40000720; +/*ets_efuse_get_uart_print_channel = 0x40000724;*/ +ets_efuse_usb_serial_jtag_print_is_disabled = 0x40000724; +ets_efuse_get_uart_print_control = 0x40000728; +ets_efuse_get_wp_pad = 0x4000072c; +ets_efuse_legacy_spi_boot_mode_disabled = 0x40000730; +ets_efuse_security_download_modes_enabled = 0x40000734; +ets_efuse_set_timing = 0x40000738; +ets_efuse_jtag_disabled = 0x4000073c; +ets_efuse_usb_download_mode_disabled = 0x40000740; +ets_efuse_usb_module_disabled = 0x40000744; +ets_efuse_usb_device_disabled = 0x40000748; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x4000074c; +ets_rsa_pss_verify = 0x40000750; +ets_secure_boot_verify_bootloader_with_keys = 0x40000754; +ets_secure_boot_verify_signature = 0x40000758; +ets_secure_boot_read_key_digests = 0x4000075c; +ets_secure_boot_revoke_public_key_digest = 0x40000760; + + +/*************************************** + Group usb_uart + ***************************************/ + +/* Functions */ +PROVIDE( usb_uart_rx_one_char = 0x400008cc ); +PROVIDE( usb_uart_rx_one_char_block = 0x400008d0 ); +PROVIDE( usb_uart_tx_flush = 0x400008d4 ); +PROVIDE( usb_uart_tx_one_char = 0x400008d8 ); +/* Data (.data, .bss, .rodata) */ +PROVIDE( g_uart_print = 0x3fcdffd1 ); +PROVIDE( g_usb_print = 0x3fcdffd0 ); + + +/*************************************** + Group bluetooth + ***************************************/ + +/* Functions */ +bt_rf_coex_get_dft_cfg = 0x400008dc; +bt_rf_coex_hooks_p_set = 0x400008e0; +btdm_con_maxevtime_cal_impl = 0x400008e4; +btdm_controller_get_compile_version_impl = 0x400008e8; +btdm_controller_rom_data_init = 0x400008ec; +btdm_dis_privacy_err_report_impl = 0x400008f0; +btdm_disable_adv_delay_impl = 0x400008f4; +btdm_enable_scan_continue_impl = 0x400008f8; +btdm_enable_scan_forever_impl = 0x400008fc; +btdm_get_power_state_impl = 0x40000900; +btdm_get_prevent_sleep_flag_impl = 0x40000904; +btdm_power_state_active_impl = 0x40000908; +btdm_switch_phy_coded_impl = 0x4000090c; +hci_acl_data_handler = 0x40000910; +hci_disconnect_cmd_handler = 0x40000914; +hci_le_con_upd_cmd_handler = 0x40000918; +hci_le_ltk_req_neg_reply_cmd_handler = 0x4000091c; +hci_le_ltk_req_reply_cmd_handler = 0x40000920; +hci_le_rd_chnl_map_cmd_handler = 0x40000924; +hci_le_rd_phy_cmd_handler = 0x40000928; +hci_le_rd_rem_feats_cmd_handler = 0x4000092c; +hci_le_rem_con_param_req_neg_reply_cmd_handler = 0x40000930; +hci_le_rem_con_param_req_reply_cmd_handler = 0x40000934; +hci_le_set_data_len_cmd_handler = 0x40000938; +hci_le_set_phy_cmd_handler = 0x4000093c; +hci_le_start_enc_cmd_handler = 0x40000940; +hci_rd_auth_payl_to_cmd_handler = 0x40000944; +hci_rd_rem_ver_info_cmd_handler = 0x40000948; +hci_rd_rssi_cmd_handler = 0x4000094c; +hci_rd_tx_pwr_lvl_cmd_handler = 0x40000950; +hci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40000954; +hci_vs_set_pref_slave_latency_cmd_handler = 0x40000958; +hci_wr_auth_payl_to_cmd_handler = 0x4000095c; +ll_channel_map_ind_handler = 0x40000960; +ll_connection_param_req_handler = 0x40000964; +ll_connection_param_rsp_handler = 0x40000968; +ll_connection_update_ind_handler = 0x4000096c; +ll_enc_req_handler = 0x40000970; +ll_enc_rsp_handler = 0x40000974; +ll_feature_req_handler = 0x40000978; +ll_feature_rsp_handler = 0x4000097c; +ll_length_req_handler = 0x40000980; +ll_length_rsp_handler = 0x40000984; +ll_min_used_channels_ind_handler = 0x40000988; +ll_pause_enc_req_handler = 0x4000098c; +ll_pause_enc_rsp_handler = 0x40000990; +ll_phy_req_handler = 0x40000994; +ll_phy_rsp_handler = 0x40000998; +ll_phy_update_ind_handler = 0x4000099c; +ll_ping_req_handler = 0x400009a0; +ll_ping_rsp_handler = 0x400009a4; +ll_slave_feature_req_handler = 0x400009a8; +ll_start_enc_req_handler = 0x400009ac; +ll_start_enc_rsp_handler = 0x400009b0; +ll_terminate_ind_handler = 0x400009b4; +ll_version_ind_handler = 0x400009b8; +llc_auth_payl_nearly_to_handler = 0x400009bc; +llc_auth_payl_real_to_handler = 0x400009c0; +llc_encrypt_ind_handler = 0x400009c4; +llc_hci_command_handler_wrapper = 0x400009c8; +llc_ll_connection_param_req_pdu_send = 0x400009cc; +llc_ll_connection_param_rsp_pdu_send = 0x400009d0; +llc_ll_connection_update_ind_pdu_send = 0x400009d4; +llc_ll_enc_req_pdu_send = 0x400009d8; +llc_ll_enc_rsp_pdu_send = 0x400009dc; +llc_ll_feature_req_pdu_send = 0x400009e0; +llc_ll_feature_rsp_pdu_send = 0x400009e4; +llc_ll_length_req_pdu_send = 0x400009e8; +llc_ll_length_rsp_pdu_send = 0x400009ec; +llc_ll_pause_enc_req_pdu_send = 0x400009f0; +llc_ll_pause_enc_rsp_pdu_send = 0x400009f4; +llc_ll_phy_req_pdu_send = 0x400009f8; +llc_ll_phy_rsp_pdu_send = 0x400009fc; +llc_ll_ping_req_pdu_send = 0x40000a00; +llc_ll_ping_rsp_pdu_send = 0x40000a04; +llc_ll_start_enc_req_pdu_send = 0x40000a08; +llc_ll_start_enc_rsp_pdu_send = 0x40000a0c; +llc_ll_terminate_ind_pdu_send = 0x40000a10; +llc_ll_unknown_rsp_pdu_send = 0x40000a14; +llc_llcp_ch_map_update_ind_pdu_send = 0x40000a18; +llc_llcp_phy_upd_ind_pdu_send = 0x40000a1c; +llc_llcp_version_ind_pdu_send = 0x40000a20; +llc_op_ch_map_upd_ind_handler = 0x40000a24; +llc_op_con_upd_ind_handler = 0x40000a28; +llc_op_disconnect_ind_handler = 0x40000a2c; +llc_op_dl_upd_ind_handler = 0x40000a30; +llc_op_encrypt_ind_handler = 0x40000a34; +llc_op_feats_exch_ind_handler = 0x40000a38; +llc_op_le_ping_ind_handler = 0x40000a3c; +llc_op_phy_upd_ind_handler = 0x40000a40; +llc_op_ver_exch_ind_handler = 0x40000a44; +llc_stopped_ind_handler = 0x40000a48; +lld_acl_rx_ind_handler = 0x40000a4c; +lld_acl_tx_cfm_handler = 0x40000a50; +lld_adv_end_ind_handler = 0x40000a54; +lld_adv_rep_ind_handler = 0x40000a58; +lld_ch_map_upd_cfm_handler = 0x40000a5c; +lld_con_estab_ind_handler = 0x40000a60; +lld_con_evt_sd_evt_time_set = 0x40000a64; +lld_con_offset_upd_ind_handler = 0x40000a68; +lld_con_param_upd_cfm_handler = 0x40000a6c; +lld_disc_ind_handler = 0x40000a70; +lld_init_end_ind_handler = 0x40000a74; +lld_llcp_rx_ind_handler_wrapper = 0x40000a78; +lld_llcp_tx_cfm_handler = 0x40000a7c; +lld_per_adv_end_ind_handler = 0x40000a80; +lld_per_adv_rep_ind_handler = 0x40000a84; +lld_per_adv_rx_end_ind_handler = 0x40000a88; +lld_phy_coded_500k_get = 0x40000a8c; +lld_phy_upd_cfm_handler = 0x40000a90; +lld_scan_end_ind_handler = 0x40000a94; +lld_scan_req_ind_handler = 0x40000a98; +lld_sync_start_req_handler = 0x40000a9c; +lld_test_end_ind_handler = 0x40000aa0; +lld_update_rxbuf_handler = 0x40000aa4; +llm_ch_map_update_ind_handler = 0x40000aa8; +llm_hci_command_handler_wrapper = 0x40000aac; +llm_scan_period_to_handler = 0x40000ab0; +r_Add2SelfBigHex256 = 0x40000ab4; +r_AddBigHex256 = 0x40000ab8; +r_AddBigHexModP256 = 0x40000abc; +r_AddP256 = 0x40000ac0; +r_AddPdiv2_256 = 0x40000ac4; +r_GF_Jacobian_Point_Addition256 = 0x40000ac8; +r_GF_Jacobian_Point_Double256 = 0x40000acc; +r_GF_Point_Jacobian_To_Affine256 = 0x40000ad0; +r_MultiplyBigHexByUint32_256 = 0x40000ad4; +r_MultiplyBigHexModP256 = 0x40000ad8; +r_MultiplyByU16ModP256 = 0x40000adc; +r_SubtractBigHex256 = 0x40000ae0; +r_SubtractBigHexMod256 = 0x40000ae4; +r_SubtractBigHexUint32_256 = 0x40000ae8; +r_SubtractFromSelfBigHex256 = 0x40000aec; +r_SubtractFromSelfBigHexSign256 = 0x40000af0; +r_aes_alloc = 0x40000af4; +r_aes_ccm_continue = 0x40000af8; +r_aes_ccm_process_e = 0x40000afc; +r_aes_ccm_xor_128_lsb = 0x40000b00; +r_aes_ccm_xor_128_msb = 0x40000b04; +r_aes_cmac_continue = 0x40000b08; +r_aes_cmac_start = 0x40000b0c; +r_aes_k1_continue = 0x40000b10; +r_aes_k2_continue = 0x40000b14; +r_aes_k3_continue = 0x40000b18; +r_aes_k4_continue = 0x40000b1c; +r_aes_shift_left_128 = 0x40000b20; +r_aes_start = 0x40000b24; +r_aes_xor_128 = 0x40000b28; +r_assert_err = 0x40000b2c; +r_assert_param = 0x40000b30; +r_assert_warn = 0x40000b34; +r_bigHexInversion256 = 0x40000b38; +r_ble_sw_cca_check_isr = 0x40000b3c; +r_ble_util_buf_acl_tx_alloc = 0x40000b40; +r_ble_util_buf_acl_tx_elt_get = 0x40000b44; +r_ble_util_buf_acl_tx_free = 0x40000b48; +r_ble_util_buf_acl_tx_free_in_isr = 0x40000b4c; +r_ble_util_buf_adv_tx_alloc = 0x40000b50; +r_ble_util_buf_adv_tx_free = 0x40000b54; +r_ble_util_buf_adv_tx_free_in_isr = 0x40000b58; +r_ble_util_buf_env_deinit = 0x40000b5c; +r_ble_util_buf_env_init = 0x40000b60; +r_ble_util_buf_get_rx_buf_nb = 0x40000b64; +r_ble_util_buf_get_rx_buf_size = 0x40000b68; +r_ble_util_buf_llcp_tx_alloc = 0x40000b6c; +r_ble_util_buf_llcp_tx_free = 0x40000b70; +r_ble_util_buf_rx_alloc = 0x40000b74; +r_ble_util_buf_rx_alloc_in_isr = 0x40000b78; +r_ble_util_buf_rx_free = 0x40000b7c; +r_ble_util_buf_rx_free_in_isr = 0x40000b80; +r_ble_util_buf_set_rx_buf_nb = 0x40000b84; +r_ble_util_buf_set_rx_buf_size = 0x40000b88; +r_ble_util_data_rx_buf_reset = 0x40000b8c; +r_bt_bb_get_intr_mask = 0x40000b90; +r_bt_bb_intr_clear = 0x40000b94; +r_bt_bb_intr_mask_set = 0x40000b98; +r_bt_rf_coex_cfg_set = 0x40000ba0; +r_bt_rf_coex_conn_dynamic_pti_en_get = 0x40000ba4; +r_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x40000bac; +r_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x40000bb0; +r_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40000bb4; +r_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x40000bb8; +r_bt_rf_coex_pti_table_get = 0x40000bbc; +r_bt_rf_coex_st_param_get = 0x40000bc0; +r_bt_rf_coex_st_param_set = 0x40000bc4; +r_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x40000bc8; +r_bt_rma_apply_rule_cs_fmt = 0x40000bcc; +r_bt_rma_apply_rule_cs_idx = 0x40000bd0; +r_bt_rma_configure = 0x40000bd4; +r_bt_rma_deregister_rule_cs_fmt = 0x40000bd8; +r_bt_rma_deregister_rule_cs_idx = 0x40000bdc; +r_bt_rma_get_ant_by_act = 0x40000be0; +r_bt_rma_init = 0x40000be4; +r_bt_rma_register_rule_cs_fmt = 0x40000be8; +r_bt_rma_register_rule_cs_idx = 0x40000bec; +r_bt_rtp_apply_rule_cs_fmt = 0x40000bf0; +r_bt_rtp_apply_rule_cs_idx = 0x40000bf4; +r_bt_rtp_deregister_rule_cs_fmt = 0x40000bf8; +r_bt_rtp_deregister_rule_cs_idx = 0x40000bfc; +r_bt_rtp_init = 0x40000c04; +r_bt_rtp_register_rule_cs_fmt = 0x40000c08; +r_bt_rtp_register_rule_cs_idx = 0x40000c0c; +r_btdm_isr = 0x40000c10; +r_cali_phase_match_p = 0x40000c20; +r_cmp_abs_time = 0x40000c24; +r_cmp_dest_id = 0x40000c28; +r_cmp_timer_id = 0x40000c2c; +r_co_bdaddr_compare = 0x40000c30; +r_co_ble_pkt_dur_in_us = 0x40000c34; +r_co_list_extract = 0x40000c38; +r_co_list_extract_after = 0x40000c3c; +r_co_list_extract_sublist = 0x40000c40; +r_co_list_find = 0x40000c44; +r_co_list_init = 0x40000c48; +r_co_list_insert_after = 0x40000c4c; +r_co_list_insert_before = 0x40000c50; +r_co_list_merge = 0x40000c54; +r_co_list_pool_init = 0x40000c58; +r_co_list_pop_front = 0x40000c5c; +r_co_list_push_back = 0x40000c60; +r_co_list_push_back_sublist = 0x40000c64; +r_co_list_push_front = 0x40000c68; +r_co_list_size = 0x40000c6c; +r_co_nb_good_le_channels = 0x40000c70; +r_co_util_pack = 0x40000c74; +r_co_util_read_array_size = 0x40000c78; +r_co_util_unpack = 0x40000c7c; +r_dbg_env_deinit = 0x40000c80; +r_dbg_env_init = 0x40000c84; +r_dbg_platform_reset_complete = 0x40000c88; +r_dl_upd_proc_start = 0x40000c8c; +r_dump_data = 0x40000c90; +r_ecc_abort_key256_generation = 0x40000c94; +r_ecc_gen_new_public_key = 0x40000c98; +r_ecc_gen_new_secret_key = 0x40000c9c; +r_ecc_generate_key256 = 0x40000ca0; +r_ecc_get_debug_Keys = 0x40000ca4; +r_ecc_init = 0x40000ca8; +r_ecc_is_valid_point = 0x40000cac; +r_ecc_multiplication_event_handler = 0x40000cb0; +r_ecc_point_multiplication_win_256 = 0x40000cb4; +r_emi_alloc_em_mapping_by_offset = 0x40000cb8; +r_emi_base_reg_lut_show = 0x40000cbc; +r_emi_em_base_reg_show = 0x40000cc0; +r_emi_free_em_mapping_by_offset = 0x40000cc4; +r_emi_get_em_mapping_idx_by_offset = 0x40000cc8; +r_emi_get_mem_addr_by_offset = 0x40000ccc; +r_emi_overwrite_em_mapping_by_offset = 0x40000cd0; +r_esp_vendor_hci_command_handler = 0x40000cd4; +r_get_stack_usage = 0x40000cd8; +r_h4tl_acl_hdr_rx_evt_handler = 0x40000cdc; +r_h4tl_cmd_hdr_rx_evt_handler = 0x40000ce0; +r_h4tl_cmd_pld_rx_evt_handler = 0x40000ce4; +r_h4tl_eif_io_event_post = 0x40000ce8; +r_h4tl_eif_register = 0x40000cec; +r_h4tl_init = 0x40000cf0; +r_h4tl_out_of_sync = 0x40000cf4; +r_h4tl_out_of_sync_check = 0x40000cf8; +r_h4tl_read_hdr = 0x40000cfc; +r_h4tl_read_next_out_of_sync = 0x40000d00; +r_h4tl_read_payl = 0x40000d04; +r_h4tl_read_start = 0x40000d08; +r_h4tl_rx_acl_hdr_extract = 0x40000d0c; +r_h4tl_rx_cmd_hdr_extract = 0x40000d10; +r_h4tl_rx_done = 0x40000d14; +r_h4tl_start = 0x40000d18; +r_h4tl_stop = 0x40000d1c; +r_h4tl_tx_done = 0x40000d20; +r_h4tl_tx_evt_handler = 0x40000d24; +r_h4tl_write = 0x40000d28; +r_hci_acl_tx_data_alloc = 0x40000d2c; +r_hci_acl_tx_data_received = 0x40000d30; +r_hci_basic_cmd_send_2_controller = 0x40000d34; +r_hci_ble_adv_report_filter_check = 0x40000d38; +r_hci_ble_adv_report_tx_check = 0x40000d3c; +r_hci_ble_conhdl_register = 0x40000d40; +r_hci_ble_conhdl_unregister = 0x40000d44; +r_hci_build_acl_data = 0x40000d48; +r_hci_build_cc_evt = 0x40000d4c; +r_hci_build_cs_evt = 0x40000d50; +r_hci_build_evt = 0x40000d54; +r_hci_build_le_evt = 0x40000d58; +r_hci_cmd_get_max_param_size = 0x40000d5c; +r_hci_cmd_received = 0x40000d60; +r_hci_cmd_reject = 0x40000d64; +r_hci_evt_mask_check = 0x40000d68; +r_hci_evt_mask_set = 0x40000d6c; +r_hci_fc_acl_buf_size_set = 0x40000d70; +r_hci_fc_acl_en = 0x40000d74; +r_hci_fc_acl_packet_sent = 0x40000d78; +r_hci_fc_check_host_available_nb_acl_packets = 0x40000d7c; +r_hci_fc_host_nb_acl_pkts_complete = 0x40000d80; +r_hci_fc_init = 0x40000d84; +r_hci_look_for_cmd_desc = 0x40000d88; +r_hci_look_for_evt_desc = 0x40000d8c; +r_hci_look_for_le_evt_desc = 0x40000d90; +r_hci_look_for_le_evt_desc_esp = 0x40000d94; +r_hci_pack_bytes = 0x40000d98; +r_hci_send_2_controller = 0x40000da0; +r_hci_send_2_host = 0x40000da4; +r_hci_tl_c2h_data_flow_on = 0x40000da8; +r_hci_tl_cmd_hdr_rx_evt_handler = 0x40000dac; +r_hci_tl_cmd_pld_rx_evt_handler = 0x40000db0; +r_hci_tl_get_pkt = 0x40000db4; +r_hci_tl_hci_pkt_handler = 0x40000db8; +r_hci_tl_hci_tx_done_evt_handler = 0x40000dbc; +r_hci_tl_inc_nb_h2c_cmd_pkts = 0x40000dc0; +r_hci_tl_save_pkt = 0x40000dc4; +r_hci_tl_send = 0x40000dc8; +r_hci_tx_done = 0x40000dcc; +r_hci_tx_start = 0x40000dd0; +r_hci_tx_trigger = 0x40000dd4; +r_isValidSecretKey_256 = 0x40000dd8; +r_ke_check_malloc = 0x40000ddc; +r_ke_event_callback_set = 0x40000de0; +r_ke_event_clear = 0x40000de4; +r_ke_event_flush = 0x40000de8; +r_ke_event_get = 0x40000dec; +r_ke_event_get_all = 0x40000df0; +r_ke_event_init = 0x40000df4; +r_ke_event_schedule = 0x40000df8; +r_ke_event_set = 0x40000dfc; +r_ke_flush = 0x40000e00; +r_ke_free = 0x40000e04; +r_ke_handler_search = 0x40000e08; +r_ke_init = 0x40000e0c; +r_ke_is_free = 0x40000e10; +r_ke_malloc = 0x40000e14; +r_ke_mem_init = 0x40000e18; +r_ke_mem_is_empty = 0x40000e1c; +r_ke_mem_is_in_heap = 0x40000e20; +r_ke_msg_alloc = 0x40000e24; +r_ke_msg_dest_id_get = 0x40000e28; +r_ke_msg_discard = 0x40000e2c; +r_ke_msg_forward = 0x40000e30; +r_ke_msg_forward_new_id = 0x40000e34; +r_ke_msg_free = 0x40000e38; +r_ke_msg_in_queue = 0x40000e3c; +r_ke_msg_save = 0x40000e40; +r_ke_msg_send = 0x40000e44; +r_ke_msg_send_basic = 0x40000e48; +r_ke_msg_src_id_get = 0x40000e4c; +r_ke_queue_extract = 0x40000e50; +r_ke_queue_insert = 0x40000e54; +r_ke_sleep_check = 0x40000e58; +r_ke_state_get = 0x40000e5c; +r_ke_state_set = 0x40000e60; +r_ke_task_check = 0x40000e64; +r_ke_task_create = 0x40000e68; +r_ke_task_delete = 0x40000e6c; +r_ke_task_handler_get = 0x40000e70; +r_ke_task_init = 0x40000e74; +r_ke_task_msg_flush = 0x40000e78; +r_ke_task_saved_update = 0x40000e7c; +r_ke_time = 0x40000e84; +r_ke_time_cmp = 0x40000e88; +r_ke_time_past = 0x40000e8c; +r_ke_timer_active = 0x40000e90; +r_ke_timer_adjust_all = 0x40000e94; +r_ke_timer_clear = 0x40000e98; +r_ke_timer_init = 0x40000e9c; +r_ke_timer_schedule = 0x40000ea0; +r_ke_timer_set = 0x40000ea4; +r_led_init = 0x40000ea8; +r_led_set_all = 0x40000eac; +r_llc_aes_res_cb = 0x40000eb0; +r_llc_ch_map_up_proc_err_cb = 0x40000eb4; +r_llc_cleanup = 0x40000eb8; +r_llc_cmd_cmp_send = 0x40000ebc; +r_llc_cmd_stat_send = 0x40000ec0; +r_llc_con_move_cbk = 0x40000ec4; +r_llc_con_plan_set_update = 0x40000ec8; +r_llc_con_upd_param_in_range = 0x40000ecc; +r_llc_disconnect = 0x40000ed0; +r_llc_disconnect_end = 0x40000ed4; +r_llc_disconnect_proc_continue = 0x40000ed8; +r_llc_disconnect_proc_err_cb = 0x40000edc; +r_llc_dl_chg_check = 0x40000ee0; +r_llc_dle_proc_err_cb = 0x40000ee4; +r_llc_feats_exch_proc_err_cb = 0x40000ee8; +r_llc_hci_cmd_handler_tab_p_get = 0x40000eec; +r_llc_hci_con_param_req_evt_send = 0x40000ef4; +r_llc_hci_con_upd_info_send = 0x40000ef8; +r_llc_hci_disconnected_dis = 0x40000efc; +r_llc_hci_dl_upd_info_send = 0x40000f00; +r_llc_hci_enc_evt_send = 0x40000f04; +r_llc_hci_feats_info_send = 0x40000f08; +r_llc_hci_le_phy_upd_cmp_evt_send = 0x40000f0c; +r_llc_hci_ltk_request_evt_send = 0x40000f10; +r_llc_hci_nb_cmp_pkts_evt_send = 0x40000f14; +r_llc_hci_version_info_send = 0x40000f18; +r_llc_init_term_proc = 0x40000f1c; +r_llc_iv_skd_rand_gen = 0x40000f20; +r_llc_le_ping_proc_continue = 0x40000f24; +r_llc_le_ping_proc_err_cb = 0x40000f28; +r_llc_le_ping_restart = 0x40000f2c; +r_llc_le_ping_set = 0x40000f30; +r_llc_ll_pause_enc_rsp_ack_handler = 0x40000f34; +r_llc_ll_reject_ind_ack_handler = 0x40000f38; +r_llc_ll_reject_ind_pdu_send = 0x40000f3c; +r_llc_ll_start_enc_rsp_ack_handler = 0x40000f40; +r_llc_ll_terminate_ind_ack = 0x40000f44; +r_llc_ll_unknown_ind_handler = 0x40000f48; +r_llc_llcp_send = 0x40000f4c; +r_llc_llcp_state_set = 0x40000f50; +r_llc_llcp_trans_timer_set = 0x40000f54; +r_llc_llcp_tx_check = 0x40000f58; +r_llc_loc_ch_map_proc_continue = 0x40000f5c; +r_llc_loc_con_upd_proc_err_cb = 0x40000f64; +r_llc_loc_dl_upd_proc_continue = 0x40000f68; +r_llc_loc_encrypt_proc_continue = 0x40000f6c; +r_llc_loc_encrypt_proc_err_cb = 0x40000f70; +r_llc_loc_feats_exch_proc_continue = 0x40000f74; +r_llc_loc_phy_upd_proc_err_cb = 0x40000f7c; +r_llc_msg_handler_tab_p_get = 0x40000f80; +r_llc_pref_param_compute = 0x40000f84; +r_llc_proc_collision_check = 0x40000f88; +r_llc_proc_err_ind = 0x40000f8c; +r_llc_proc_get = 0x40000f90; +r_llc_proc_id_get = 0x40000f94; +r_llc_proc_reg = 0x40000f98; +r_llc_proc_state_get = 0x40000f9c; +r_llc_proc_state_set = 0x40000fa0; +r_llc_proc_timer_pause_set = 0x40000fa4; +r_llc_proc_timer_set = 0x40000fa8; +r_llc_proc_unreg = 0x40000fac; +r_llc_rem_ch_map_proc_continue = 0x40000fb0; +r_llc_rem_con_upd_proc_err_cb = 0x40000fb8; +r_llc_rem_dl_upd_proc = 0x40000fbc; +r_llc_rem_encrypt_proc_continue = 0x40000fc0; +r_llc_rem_encrypt_proc_err_cb = 0x40000fc4; +r_llc_rem_phy_upd_proc_continue = 0x40000fc8; +r_llc_rem_phy_upd_proc_err_cb = 0x40000fcc; +r_llc_role_get = 0x40000fd0; +r_llc_sk_gen = 0x40000fd4; +r_llc_start = 0x40000fd8; +r_llc_stop = 0x40000fdc; +r_llc_ver_exch_loc_proc_continue = 0x40000fe0; +r_llc_ver_proc_err_cb = 0x40000fe4; +r_llcp_pdu_handler_tab_p_get = 0x40000fe8; +r_lld_aa_gen = 0x40000fec; +r_lld_adv_adv_data_set = 0x40000ff0; +r_lld_adv_adv_data_update = 0x40000ff4; +r_lld_adv_aux_ch_idx_set = 0x40000ff8; +r_lld_adv_aux_evt_canceled_cbk = 0x40000ffc; +r_lld_adv_aux_evt_start_cbk = 0x40001000; +r_lld_adv_coex_check_ext_adv_synced = 0x40001004; +r_lld_adv_coex_env_reset = 0x40001008; +r_lld_adv_duration_update = 0x4000100c; +r_lld_adv_dynamic_pti_process = 0x40001010; +r_lld_adv_end = 0x40001014; +r_lld_adv_evt_canceled_cbk = 0x40001018; +r_lld_adv_evt_start_cbk = 0x4000101c; +r_lld_adv_ext_chain_construct = 0x40001020; +r_lld_adv_ext_pkt_prepare = 0x40001024; +r_lld_adv_frm_cbk = 0x40001028; +r_lld_adv_frm_isr = 0x4000102c; +r_lld_adv_frm_skip_isr = 0x40001030; +r_lld_adv_init = 0x40001034; +r_lld_adv_pkt_rx = 0x40001038; +r_lld_adv_pkt_rx_connect_ind = 0x4000103c; +r_lld_adv_pkt_rx_send_scan_req_evt = 0x40001040; +r_lld_adv_rand_addr_update = 0x40001044; +r_lld_adv_restart = 0x40001048; +r_lld_adv_scan_rsp_data_set = 0x4000104c; +r_lld_adv_scan_rsp_data_update = 0x40001050; +r_lld_adv_set_tx_power = 0x40001054; +r_lld_adv_start = 0x40001058; +r_lld_adv_stop = 0x4000105c; +r_lld_adv_sync_info_set = 0x40001060; +r_lld_adv_sync_info_update = 0x40001064; +r_lld_calc_aux_rx = 0x40001068; +r_lld_cca_alloc = 0x4000106c; +r_lld_cca_data_reset = 0x40001070; +r_lld_cca_free = 0x40001074; +r_lld_ch_assess_data_get = 0x40001078; +r_lld_ch_idx_get = 0x4000107c; +r_lld_ch_map_set = 0x40001080; +r_lld_channel_assess = 0x40001084; +r_lld_con_activity_act_offset_compute = 0x40001088; +r_lld_con_activity_offset_compute = 0x4000108c; +r_lld_con_ch_map_update = 0x40001090; +r_lld_con_cleanup = 0x40001094; +r_lld_con_current_tx_power_get = 0x40001098; +r_lld_con_data_flow_set = 0x4000109c; +r_lld_con_data_len_update = 0x400010a0; +r_lld_con_data_tx = 0x400010a4; +r_lld_con_enc_key_load = 0x400010a8; +r_lld_con_event_counter_get = 0x400010ac; +r_lld_con_evt_canceled_cbk = 0x400010b0; +r_lld_con_evt_duration_min_get = 0x400010b4; +r_lld_con_evt_max_eff_time_cal = 0x400010b8; +r_lld_con_evt_sd_evt_time_get = 0x400010bc; +r_lld_con_evt_start_cbk = 0x400010c0; +r_lld_con_evt_time_update = 0x400010c4; +r_lld_con_free_all_tx_buf = 0x400010c8; +r_lld_con_frm_cbk = 0x400010cc; +r_lld_con_frm_isr = 0x400010d0; +r_lld_con_frm_skip_isr = 0x400010d4; +r_lld_con_init = 0x400010d8; +r_lld_con_llcp_tx = 0x400010dc; +r_lld_con_max_lat_calc = 0x400010e0; +r_lld_con_offset_get = 0x400010e4; +r_lld_con_param_update = 0x400010e8; +r_lld_con_phys_update = 0x400010ec; +r_lld_con_pref_slave_evt_dur_set = 0x400010f0; +r_lld_con_pref_slave_latency_set = 0x400010f4; +r_lld_con_rssi_get = 0x400010f8; +r_lld_con_rx = 0x400010fc; +r_lld_con_rx_channel_assess = 0x40001100; +r_lld_con_rx_enc = 0x40001104; +r_lld_con_rx_isr = 0x40001108; +r_lld_con_rx_link_info_check = 0x4000110c; +r_lld_con_rx_llcp_check = 0x40001110; +r_lld_con_rx_sync_time_update = 0x40001114; +r_lld_con_set_tx_power = 0x4000111c; +r_lld_con_start = 0x40001120; +r_lld_con_tx = 0x40001128; +r_lld_con_tx_enc = 0x4000112c; +r_lld_con_tx_isr = 0x40001130; +r_lld_con_tx_len_update = 0x40001134; +r_lld_con_tx_len_update_for_intv = 0x40001138; +r_lld_con_tx_len_update_for_rate = 0x4000113c; +r_lld_con_tx_prog = 0x40001140; +r_lld_conn_dynamic_pti_process = 0x40001144; +r_lld_continue_scan_rx_isr_end_process = 0x40001148; +r_lld_ext_scan_dynamic_pti_process = 0x4000114c; +r_lld_hw_cca_end_isr = 0x40001150; +r_lld_hw_cca_evt_handler = 0x40001154; +r_lld_hw_cca_isr = 0x40001158; +r_lld_init_cal_anchor_point = 0x4000115c; +r_lld_init_compute_winoffset = 0x40001160; +r_lld_init_connect_req_pack = 0x40001164; +r_lld_init_end = 0x40001168; +r_lld_init_evt_canceled_cbk = 0x4000116c; +r_lld_init_evt_start_cbk = 0x40001170; +r_lld_init_frm_cbk = 0x40001174; +r_lld_init_frm_eof_isr = 0x40001178; +r_lld_init_frm_skip_isr = 0x4000117c; +r_lld_init_init = 0x40001180; +r_lld_init_process_pkt_rx = 0x40001184; +r_lld_init_process_pkt_rx_adv_ext_ind = 0x40001188; +r_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x4000118c; +r_lld_init_process_pkt_rx_aux_connect_rsp = 0x40001190; +r_lld_init_process_pkt_tx = 0x40001194; +r_lld_init_process_pkt_tx_cal_con_timestamp = 0x40001198; +r_lld_init_sched = 0x4000119c; +r_lld_init_set_tx_power = 0x400011a0; +r_lld_init_start = 0x400011a4; +r_lld_init_stop = 0x400011a8; +r_lld_instant_proc_end = 0x400011ac; +r_lld_per_adv_ch_map_update = 0x400011b4; +r_lld_per_adv_chain_construct = 0x400011b8; +r_lld_per_adv_cleanup = 0x400011bc; +r_lld_per_adv_coex_env_reset = 0x400011c0; +r_lld_per_adv_data_set = 0x400011c4; +r_lld_per_adv_data_update = 0x400011c8; +r_lld_per_adv_dynamic_pti_process = 0x400011cc; +r_lld_per_adv_evt_canceled_cbk = 0x400011d0; +r_lld_per_adv_evt_start_cbk = 0x400011d4; +r_lld_per_adv_ext_pkt_prepare = 0x400011d8; +r_lld_per_adv_frm_cbk = 0x400011dc; +r_lld_per_adv_frm_isr = 0x400011e0; +r_lld_per_adv_frm_skip_isr = 0x400011e4; +r_lld_per_adv_init = 0x400011e8; +r_lld_per_adv_init_info_get = 0x400011ec; +r_lld_per_adv_list_add = 0x400011f0; +r_lld_per_adv_list_rem = 0x400011f4; +r_lld_per_adv_set_tx_power = 0x400011fc; +r_lld_per_adv_start = 0x40001200; +r_lld_per_adv_stop = 0x40001204; +r_lld_per_adv_sync_info_get = 0x40001208; +r_lld_process_cca_data = 0x4000120c; +r_lld_ral_search = 0x40001210; +r_lld_read_clock = 0x40001214; +r_lld_res_list_add = 0x40001218; +r_lld_res_list_is_empty = 0x40001220; +r_lld_res_list_local_rpa_get = 0x40001224; +r_lld_res_list_peer_rpa_get = 0x40001228; +r_lld_res_list_peer_update = 0x4000122c; +r_lld_res_list_priv_mode_update = 0x40001230; +r_lld_reset_reg = 0x40001238; +r_lld_rpa_renew = 0x4000123c; +r_lld_rpa_renew_evt_canceled_cbk = 0x40001240; +r_lld_rpa_renew_evt_start_cbk = 0x40001244; +r_lld_rpa_renew_instant_cbk = 0x40001248; +r_lld_rxdesc_check = 0x4000124c; +r_lld_rxdesc_free = 0x40001250; +r_lld_scan_create_sync = 0x40001254; +r_lld_scan_create_sync_cancel = 0x40001258; +r_lld_scan_end = 0x4000125c; +r_lld_scan_evt_canceled_cbk = 0x40001260; +r_lld_scan_evt_start_cbk = 0x40001264; +r_lld_scan_frm_cbk = 0x40001268; +r_lld_scan_frm_eof_isr = 0x4000126c; +r_lld_scan_frm_rx_isr = 0x40001270; +r_lld_scan_frm_skip_isr = 0x40001274; +r_lld_scan_init = 0x40001278; +r_lld_scan_params_update = 0x4000127c; +r_lld_scan_process_pkt_rx_aux_adv_ind = 0x40001288; +r_lld_scan_process_pkt_rx_aux_chain_ind = 0x4000128c; +r_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40001290; +r_lld_scan_process_pkt_rx_ext_adv = 0x40001294; +r_lld_scan_process_pkt_rx_ext_adv_ind = 0x40001298; +r_lld_scan_process_pkt_rx_legacy_adv = 0x4000129c; +r_lld_scan_restart = 0x400012a0; +r_lld_scan_sched = 0x400012a4; +r_lld_scan_set_tx_power = 0x400012a8; +r_lld_scan_start = 0x400012ac; +r_lld_scan_stop = 0x400012b0; +r_lld_scan_sync_accept = 0x400012b4; +r_lld_scan_sync_info_unpack = 0x400012b8; +r_lld_scan_trunc_ind = 0x400012bc; +r_lld_sw_cca_evt_handler = 0x400012c0; +r_lld_sw_cca_isr = 0x400012c4; +r_lld_sync_ch_map_update = 0x400012c8; +r_lld_sync_cleanup = 0x400012cc; +r_lld_sync_evt_canceled_cbk = 0x400012d0; +r_lld_sync_evt_start_cbk = 0x400012d4; +r_lld_sync_frm_cbk = 0x400012d8; +r_lld_sync_frm_eof_isr = 0x400012dc; +r_lld_sync_frm_rx_isr = 0x400012e0; +r_lld_sync_frm_skip_isr = 0x400012e4; +r_lld_sync_init = 0x400012e8; +r_lld_sync_process_pkt_rx = 0x400012ec; +r_lld_sync_process_pkt_rx_aux_sync_ind = 0x400012f0; +r_lld_sync_process_pkt_rx_pkt_check = 0x400012f4; +r_lld_sync_scan_dynamic_pti_process = 0x400012f8; +r_lld_sync_sched = 0x400012fc; +r_lld_sync_start = 0x40001300; +r_lld_sync_stop = 0x40001304; +r_lld_sync_trunc_ind = 0x40001308; +r_lld_test_cleanup = 0x4000130c; +r_lld_test_evt_canceled_cbk = 0x40001310; +r_lld_test_evt_start_cbk = 0x40001314; +r_lld_test_freq2chnl = 0x40001318; +r_lld_test_frm_cbk = 0x4000131c; +r_lld_test_frm_isr = 0x40001320; +r_lld_test_init = 0x40001324; +r_lld_test_rx_isr = 0x40001328; +r_lld_test_set_tx_power = 0x4000132c; +r_lld_test_start = 0x40001330; +r_lld_test_stop = 0x40001334; +r_lld_update_rxbuf = 0x40001338; +r_lld_update_rxbuf_isr = 0x4000133c; +r_lld_white_list_add = 0x40001340; +r_lld_white_list_rem = 0x40001344; +r_llm_activity_free_get = 0x40001348; +r_llm_activity_free_set = 0x4000134c; +r_llm_activity_syncing_get = 0x40001350; +r_llm_adv_con_len_check = 0x40001354; +r_llm_adv_hdl_to_id = 0x40001358; +r_llm_adv_rep_flow_control_check = 0x4000135c; +r_llm_adv_rep_flow_control_update = 0x40001360; +r_llm_adv_reports_list_check = 0x40001364; +r_llm_adv_set_all_release = 0x40001368; +r_llm_adv_set_dft_params = 0x4000136c; +r_llm_adv_set_release = 0x40001370; +r_llm_aes_res_cb = 0x40001374; +r_llm_ble_update_adv_flow_control = 0x40001378; +r_llm_ch_map_update = 0x4000137c; +r_llm_cmd_cmp_send = 0x40001380; +r_llm_cmd_stat_send = 0x40001384; +r_llm_dev_list_empty_entry = 0x40001388; +r_llm_dev_list_search = 0x4000138c; +r_llm_env_adv_dup_filt_deinit = 0x40001390; +r_llm_env_adv_dup_filt_init = 0x40001394; +r_llm_init_ble_adv_report_flow_contol = 0x40001398; +r_llm_is_dev_connected = 0x4000139c; +r_llm_is_dev_synced = 0x400013a0; +r_llm_is_non_con_act_ongoing_check = 0x400013a4; +r_llm_is_wl_accessible = 0x400013a8; +r_llm_le_evt_mask_check = 0x400013ac; +r_llm_link_disc = 0x400013b4; +r_llm_master_ch_map_get = 0x400013b8; +r_llm_msg_handler_tab_p_get = 0x400013bc; +r_llm_no_activity = 0x400013c0; +r_llm_per_adv_slot_dur = 0x400013c4; +r_llm_plan_elt_get = 0x400013c8; +r_llm_rx_path_comp_get = 0x400013cc; +r_llm_scan_start = 0x400013d0; +r_llm_scan_sync_acad_attach = 0x400013d4; +r_llm_scan_sync_acad_detach = 0x400013d8; +r_llm_send_adv_lost_event_to_host = 0x400013dc; +r_llm_tx_path_comp_get = 0x400013e0; +r_misc_deinit = 0x400013e4; +r_misc_free_em_buf_in_isr = 0x400013e8; +r_misc_init = 0x400013ec; +r_misc_msg_handler_tab_p_get = 0x400013f0; +r_notEqual256 = 0x400013f4; +r_phy_upd_proc_start = 0x400013f8; +r_platform_reset = 0x400013fc; +r_rf_em_init = 0x40001404; +r_rf_force_agc_enable = 0x40001408; +r_rf_reg_rd = 0x4000140c; +r_rf_reg_wr = 0x40001410; +r_rf_reset = 0x40001414; +r_rf_rssi_convert = 0x40001418; +r_rf_rw_v9_le_disable = 0x4000141c; +r_rf_rw_v9_le_enable = 0x40001420; +r_rf_sleep = 0x40001424; +r_rf_util_cs_fmt_convert = 0x40001430; +r_rw_crypto_aes_ccm = 0x40001434; +r_rw_crypto_aes_encrypt = 0x40001438; +r_rw_crypto_aes_init = 0x4000143c; +r_rw_crypto_aes_k1 = 0x40001440; +r_rw_crypto_aes_k2 = 0x40001444; +r_rw_crypto_aes_k3 = 0x40001448; +r_rw_crypto_aes_k4 = 0x4000144c; +r_rw_crypto_aes_rand = 0x40001450; +r_rw_crypto_aes_result_handler = 0x40001454; +r_rw_crypto_aes_s1 = 0x40001458; +r_rw_cryto_aes_cmac = 0x4000145c; +r_rw_v9_init_em_radio_table = 0x40001460; +r_rwble_sleep_enter = 0x40001468; +r_rwble_sleep_wakeup_end = 0x4000146c; +r_rwbtdm_isr_wrapper = 0x40001470; +r_rwip_active_check = 0x40001474; +r_rwip_aes_encrypt = 0x40001478; +r_rwip_assert = 0x4000147c; +r_rwip_crypt_evt_handler = 0x40001480; +r_rwip_crypt_isr_handler = 0x40001484; +r_rwip_eif_get = 0x40001488; +r_rwip_half_slot_2_lpcycles = 0x4000148c; +r_rwip_hus_2_lpcycles = 0x40001490; +r_rwip_isr = 0x40001494; +r_rwip_lpcycles_2_hus = 0x40001498; +r_rwip_prevent_sleep_clear = 0x4000149c; +r_rwip_prevent_sleep_set = 0x400014a0; +r_rwip_schedule = 0x400014a4; +r_rwip_sleep = 0x400014a8; +r_rwip_sw_int_handler = 0x400014ac; +r_rwip_sw_int_req = 0x400014b0; +r_rwip_time_get = 0x400014b4; +r_rwip_timer_10ms_handler = 0x400014b8; +r_rwip_timer_10ms_set = 0x400014bc; +r_rwip_timer_hs_handler = 0x400014c0; +r_rwip_timer_hs_set = 0x400014c4; +r_rwip_timer_hus_handler = 0x400014c8; +r_rwip_timer_hus_set = 0x400014cc; +r_rwip_wakeup = 0x400014d0; +r_rwip_wakeup_end = 0x400014d4; +r_rwip_wlcoex_set = 0x400014d8; +r_sch_alarm_clear = 0x400014dc; +r_sch_alarm_init = 0x400014e0; +r_sch_alarm_prog = 0x400014e4; +r_sch_alarm_set = 0x400014e8; +r_sch_alarm_timer_isr = 0x400014ec; +r_sch_arb_conflict_check = 0x400014f0; +r_sch_arb_elt_cancel = 0x400014f4; +r_sch_arb_init = 0x400014fc; +r_sch_arb_insert = 0x40001500; +r_sch_arb_prog_timer = 0x40001504; +r_sch_arb_remove = 0x40001508; +r_sch_arb_sw_isr = 0x4000150c; +r_sch_plan_chk = 0x40001510; +r_sch_plan_clock_wrap_offset_update = 0x40001514; +r_sch_plan_init = 0x40001518; +r_sch_plan_interval_req = 0x4000151c; +r_sch_plan_offset_max_calc = 0x40001520; +r_sch_plan_offset_req = 0x40001524; +r_sch_plan_position_range_compute = 0x40001528; +r_sch_plan_rem = 0x4000152c; +r_sch_plan_req = 0x40001530; +r_sch_prog_init = 0x4000153c; +r_sch_prog_push = 0x40001540; +r_sch_prog_rx_isr = 0x40001544; +r_sch_prog_skip_isr = 0x40001548; +r_sch_prog_tx_isr = 0x4000154c; +r_sch_slice_bg_add = 0x40001550; +r_sch_slice_bg_remove = 0x40001554; +r_sch_slice_compute = 0x40001558; +r_sch_slice_fg_add = 0x4000155c; +r_sch_slice_fg_remove = 0x40001560; +r_sch_slice_init = 0x40001564; +r_sch_slice_per_add = 0x40001568; +r_sch_slice_per_remove = 0x4000156c; +r_sdk_config_get_bt_sleep_enable = 0x40001570; +r_sdk_config_get_hl_derived_opts = 0x40001574; +r_sdk_config_get_opts = 0x40001578; +r_sdk_config_get_priv_opts = 0x4000157c; +r_sdk_config_set_bt_sleep_enable = 0x40001580; +r_sdk_config_set_hl_derived_opts = 0x40001584; +r_sdk_config_set_opts = 0x40001588; +r_specialModP256 = 0x4000158c; +r_unloaded_area_init = 0x40001590; +r_vhci_flow_off = 0x40001594; +r_vhci_flow_on = 0x40001598; +r_vhci_notify_host_send_available = 0x4000159c; +r_vhci_send_to_host = 0x400015a0; +r_vnd_hci_command_handler = 0x400015a4; +r_vshci_init = 0x400015a8; +vnd_hci_command_handler_wrapper = 0x400015ac; +/* Data (.data, .bss, .rodata) */ +bt_rf_coex_cfg_p = 0x3fcdffcc; +bt_rf_coex_hooks_p = 0x3fcdffc8; +btdm_env_p = 0x3fcdffc4; +g_rw_controller_task_handle = 0x3fcdffc0; +g_rw_init_sem = 0x3fcdffbc; +g_rw_schd_queue = 0x3fcdffb8; +lld_init_env = 0x3fcdffb4; +lld_rpa_renew_env = 0x3fcdffb0; +lld_scan_env = 0x3fcdffac; +lld_scan_sync_env = 0x3fcdffa8; +lld_test_env = 0x3fcdffa4; +p_ble_util_buf_env = 0x3fcdffa0; +p_lld_env = 0x3fcdff9c; +p_llm_env = 0x3fcdff98; +r_h4tl_eif_p = 0x3fcdff94; +r_hli_funcs_p = 0x3fcdff90; +r_ip_funcs_p = 0x3fcdff8c; +r_modules_funcs_p = 0x3fcdff88; +r_osi_funcs_p = 0x3fcdff84; +r_plf_funcs_p = 0x3fcdff80; +vhci_env_p = 0x3fcdff7c; +aa_gen = 0x3fcdff78; +aes_env = 0x3fcdff6c; +bt_rf_coex_cfg_cb = 0x3fcdff1c; +btdm_pwr_state = 0x3fcdff18; +btdm_slp_err = 0x3fcdff14; +ecc_env = 0x3fcdff0c; +esp_handler = 0x3fcdff04; +esp_vendor_cmd = 0x3fcdfefc; +g_adv_delay_dis = 0x3fcdfef8; +g_conflict_elt = 0x3fcdfef4; +g_eif_api = 0x3fcdfee4; +g_event_empty = 0x3fcdfed8; +g_llc_state = 0x3fcdfecc; +g_llm_state = 0x3fcdfec8; +g_max_evt_env = 0x3fcdfec4; +g_misc_state = 0x3fcdfec0; +g_rma_rule_db = 0x3fcdfea4; +g_rtp_rule_db = 0x3fcdfe88; +g_scan_forever = 0x3fcdfe85; +g_time_msb = 0x3fcdfe84; +h4tl_env = 0x3fcdfe5c; +hci_env = 0x3fcdfe38; +hci_ext_host = 0x3fcdfe34; +hci_fc_env = 0x3fcdfe2c; +hci_tl_env = 0x3fcdfe00; +ke_env = 0x3fcdfdd0; +ke_event_env = 0x3fcdfd90; +ke_task_env = 0x3fcdfd14; +llc_env = 0x3fcdfcec; +lld_adv_env = 0x3fcdfcc4; +lld_con_env = 0x3fcdfc9c; +lld_exp_sync_pos_tab = 0x3fcdfc94; +lld_per_adv_env = 0x3fcdfc6c; +lld_sync_env = 0x3fcdfc44; +llm_le_adv_flow_env = 0x3fcdfc38; +rw_sleep_enable = 0x3fcdfc34; +rwble_env = 0x3fcdfc2c; +rwip_env = 0x3fcdfc10; +rwip_param = 0x3fcdfc04; +rwip_prog_delay = 0x3fcdfc00; +rwip_rf = 0x3fcdfbc8; +sch_alarm_env = 0x3fcdfbc0; +sch_arb_env = 0x3fcdfbac; +sch_plan_env = 0x3fcdfba4; +sch_prog_env = 0x3fcdfaa0; +sch_slice_env = 0x3fcdfa40; +sch_slice_params = 0x3fcdfa38; +timer_env = 0x3fcdfa30; +unloaded_area = 0x3fcdfa2c; +vshci_state = 0x3fcdfa28; +TASK_DESC_LLC = 0x3fcdfa1c; +TASK_DESC_LLM = 0x3fcdfa10; +TASK_DESC_VSHCI = 0x3fcdfa04; +co_default_bdaddr = 0x3fcdf9fc; +dbg_assert_block = 0x3fcdf9f8; +g_bt_plf_log_level = 0x3fcdf9f4; +hci_cmd_desc_tab_vs_esp = 0x3fcdf9d0; +hci_command_handler_tab_esp = 0x3fcdf9b8; +privacy_en = 0x3fcdf9b4; +sdk_cfg_priv_opts = 0x3fcdf96c; +BasePoint_x_256 = 0x3ff1ffdc; +BasePoint_y_256 = 0x3ff1ffbc; +DebugE256PublicKey_x = 0x3ff1ff9c; +DebugE256PublicKey_y = 0x3ff1ff7c; +DebugE256SecretKey = 0x3ff1ff5c; +ECC_4Win_Look_up_table = 0x3ff1f7a0; +LLM_AA_CT1 = 0x3ff1f79c; +LLM_AA_CT2 = 0x3ff1f798; +RF_TX_PW_CONV_TBL = 0x3ff1f790; +TASK_DESC_MISC = 0x3ff1f784; +adv_evt_prop2type = 0x3ff1f768; +adv_evt_type2prop = 0x3ff1f760; +aes_cmac_zero = 0x3ff1f750; +aes_k2_salt = 0x3ff1f740; +aes_k3_id64 = 0x3ff1f738; +aes_k3_salt = 0x3ff1f728; +aes_k4_id6 = 0x3ff1f724; +aes_k4_salt = 0x3ff1f714; +bigHexP256 = 0x3ff1f6e8; +byte_tx_time = 0x3ff1f6e0; +co_null_bdaddr = 0x3ff1f6d8; +co_phy_mask_to_rate = 0x3ff1f6d0; +co_phy_mask_to_value = 0x3ff1f6c8; +co_phy_to_rate = 0x3ff1f6c4; +co_phy_value_to_mask = 0x3ff1f6c0; +co_rate_to_byte_dur_us = 0x3ff1f6b8; +co_rate_to_phy = 0x3ff1f6b0; +co_rate_to_phy_mask = 0x3ff1f6ac; +co_sca2ppm = 0x3ff1f69c; +coef_B = 0x3ff1f670; +connect_req_dur_tab = 0x3ff1f668; +ecc_Jacobian_InfinityPoint256 = 0x3ff1f5e4; +em_base_reg_lut = 0x3ff1f518; +fixed_tx_time = 0x3ff1f510; +h4tl_msgtype2hdrlen = 0x3ff1f508; +hci_cmd_desc_root_tab = 0x3ff1f4d8; +hci_cmd_desc_tab_ctrl_bb = 0x3ff1f46c; +hci_cmd_desc_tab_info_par = 0x3ff1f43c; +hci_cmd_desc_tab_le = 0x3ff1f0a0; +hci_cmd_desc_tab_lk_ctrl = 0x3ff1f088; +hci_cmd_desc_tab_stat_par = 0x3ff1f07c; +hci_cmd_desc_tab_vs = 0x3ff1f040; +hci_evt_desc_tab = 0x3ff1eff8; +hci_evt_le_desc_tab = 0x3ff1ef58; +hci_evt_le_desc_tab_esp = 0x3ff1ef50; +hci_rsvd_evt_msk = 0x3ff1ef48; +lld_aux_phy_to_rate = 0x3ff1ef44; +lld_init_max_aux_dur_tab = 0x3ff1ef3c; +lld_scan_map_legacy_pdu_to_evt_type = 0x3ff1ef34; +lld_scan_max_aux_dur_tab = 0x3ff1ef2c; +lld_sync_max_aux_dur_tab = 0x3ff1ef24; +llm_local_le_feats = 0x3ff1ef1c; +llm_local_le_states = 0x3ff1ef14; +llm_local_supp_cmds = 0x3ff1eeec; +maxSecretKey_256 = 0x3ff1eecc; +max_data_tx_time = 0x3ff1eec4; +one_bits = 0x3ff1eeb4; +rwip_coex_cfg = 0x3ff1eeac; +rwip_priority = 0x3ff1ee94; +veryBigHexP256 = 0x3ff1ee48; + +/* bluetooth hook funcs */ +r_llc_loc_encrypt_proc_continue_hook = 0x40001c60; +r_llc_loc_phy_upd_proc_continue_hook = 0x40001c64; +r_llc_rem_phy_upd_proc_continue_hook = 0x40001c68; +r_lld_scan_frm_eof_isr_hook = 0x40001c6c; +r_lld_scan_evt_start_cbk_hook = 0x40001c70; +r_lld_scan_process_pkt_rx_ext_adv_hook = 0x40001c78; +r_lld_scan_sched_hook = 0x40001c7c; +r_lld_adv_evt_start_cbk_hook = 0x40001c84; +r_lld_adv_aux_evt_start_cbk_hook = 0x40001c88; +r_lld_adv_frm_isr_hook = 0x40001c8c; +r_lld_adv_start_init_evt_param_hook = 0x40001c90; +r_lld_con_evt_canceled_cbk_hook = 0x40001c94; +r_lld_con_frm_isr_hook = 0x40001c98; +r_lld_con_tx_hook = 0x40001c9c; +r_lld_con_rx_hook = 0x40001ca0; +r_lld_con_evt_start_cbk_hook = 0x40001ca4; +r_lld_con_tx_prog_new_packet_hook = 0x40001cac; +r_lld_init_frm_eof_isr_hook = 0x40001cb0; +r_lld_init_evt_start_cbk_hook = 0x40001cb4; +r_lld_init_sched_hook = 0x40001cbc; +r_lld_init_process_pkt_tx_hook = 0x40001cc0; +r_lld_per_adv_evt_start_cbk_hook = 0x40001cc4; +r_lld_per_adv_frm_isr_hook = 0x40001cc8; +r_lld_per_adv_start_hook = 0x40001ccc; +r_lld_sync_frm_eof_isr_hook = 0x40001cd0; +r_lld_sync_evt_start_cbk_hook = 0x40001cd4; +r_lld_sync_start_hook = 0x40001cd8; +r_lld_sync_process_pkt_rx_pkt_check_hook = 0x40001cdc; +r_sch_arb_insert_hook = 0x40001ce0; +r_sch_plan_offset_req_hook = 0x40001ce4; + +/*************************************** + Group rom_pp + ***************************************/ + +/* Functions */ +esp_pp_rom_version_get = 0x400015b0; +RC_GetBlockAckTime = 0x400015b4; +ebuf_list_remove = 0x400015b8; +/*esf_buf_alloc = 0x400015bc;*/ +GetAccess = 0x400015c8; +hal_mac_is_low_rate_enabled = 0x400015cc; +hal_mac_tx_get_blockack = 0x400015d0; +/* hal_mac_tx_set_ppdu = 0x400015d4;*/ +ic_get_trc = 0x400015d8; +/* ic_mac_deinit = 0x400015dc; */ +ic_mac_init = 0x400015e0; +ic_interface_enabled = 0x400015e4; +is_lmac_idle = 0x400015e8; +/*lmacAdjustTimestamp = 0x400015ec;*/ +lmacDiscardAgedMSDU = 0x400015f0; +/*lmacDiscardMSDU = 0x400015f4;*/ +lmacEndFrameExchangeSequence = 0x400015f8; +lmacIsIdle = 0x400015fc; +lmacIsLongFrame = 0x40001600; +/*lmacMSDUAged = 0x40001604;*/ +lmacPostTxComplete = 0x40001608; +lmacProcessAllTxTimeout = 0x4000160c; +lmacProcessCollisions = 0x40001610; +lmacProcessRxSucData = 0x40001614; +lmacReachLongLimit = 0x40001618; +lmacReachShortLimit = 0x4000161c; +lmacRecycleMPDU = 0x40001620; +lmacRxDone = 0x40001624; +/*lmacSetTxFrame = 0x40001628;*/ +/*lmacTxFrame = 0x40001630;*/ +mac_tx_set_duration = 0x40001634; +/* mac_tx_set_htsig = 0x40001638;*/ +mac_tx_set_plcp0 = 0x4000163c; +/* mac_tx_set_plcp1 = 0x40001640;*/ +mac_tx_set_plcp2 = 0x40001644; +/* pm_check_state = 0x40001648; */ +pm_disable_dream_timer = 0x4000164c; +pm_disable_sleep_delay_timer = 0x40001650; +pm_dream = 0x40001654; +pm_mac_wakeup = 0x40001658; +pm_mac_sleep = 0x4000165c; +pm_enable_active_timer = 0x40001660; +pm_enable_sleep_delay_timer = 0x40001664; +pm_local_tsf_process = 0x40001668; +pm_set_beacon_filter = 0x4000166c; +pm_is_in_wifi_slice_threshold = 0x40001670; +pm_is_waked = 0x40001674; +pm_keep_alive = 0x40001678; +/* pm_on_beacon_rx = 0x4000167c; */ +pm_on_data_rx = 0x40001680; +pm_on_tbtt = 0x40001684; +/* pm_parse_beacon = 0x40001688;*/ +/* pm_process_tim = 0x4000168c; */ +/*pm_rx_beacon_process = 0x40001690;*/ +/* pm_rx_data_process = 0x40001694; */ +/*pm_sleep = 0x40001698;*/ +pm_sleep_for = 0x4000169c; +/* pm_tbtt_process = 0x400016a0; */ +ppAMPDU2Normal = 0x400016a4; +/*ppAssembleAMPDU = 0x400016a8;*/ +ppCalFrameTimes = 0x400016ac; +ppCalSubFrameLength = 0x400016b0; +/*ppCalTxAMPDULength = 0x400016b4;*/ +ppCheckTxAMPDUlength = 0x400016b8; +ppDequeueRxq_Locked = 0x400016bc; +ppDequeueTxQ = 0x400016c0; +ppEmptyDelimiterLength = 0x400016c4; +ppEnqueueRxq = 0x400016c8; +ppEnqueueTxDone = 0x400016cc; +ppGetTxQFirstAvail_Locked = 0x400016d0; +ppGetTxframe = 0x400016d4; +ppProcessRxPktHdr = 0x400016e0; +ppProcessTxQ = 0x400016e4; +ppRecordBarRRC = 0x400016e8; +lmacRequestTxopQueue = 0x400016ec; +lmacReleaseTxopQueue = 0x400016f0; +ppRecycleAmpdu = 0x400016f4; +ppRecycleRxPkt = 0x400016f8; +ppResortTxAMPDU = 0x400016fc; +ppResumeTxAMPDU = 0x40001700; +/* ppRxFragmentProc = 0x40001704; */ +/* ppRxPkt = 0x40001708; */ +ppRxProtoProc = 0x4000170c; +ppSearchTxQueue = 0x40001710; +ppSearchTxframe = 0x40001714; +ppSelectNextQueue = 0x40001718; +ppSubFromAMPDU = 0x4000171c; +ppTask = 0x40001720; +ppTxPkt = 0x40001724; +ppTxProtoProc = 0x40001728; +ppTxqUpdateBitmap = 0x4000172c; +pp_coex_tx_request = 0x40001730; +pp_hdrsize = 0x40001734; +pp_post = 0x40001738; +pp_process_hmac_waiting_txq = 0x4000173c; +rcGetAmpduSched = 0x40001740; +rcUpdateRxDone = 0x40001744; +rc_get_trc = 0x40001748; +rc_get_trc_by_index = 0x4000174c; +rcAmpduLowerRate = 0x40001750; +rcampduuprate = 0x40001754; +rcClearCurAMPDUSched = 0x40001758; +rcClearCurSched = 0x4000175c; +rcClearCurStat = 0x40001760; +rcLowerSched = 0x40001768; +rcSetTxAmpduLimit = 0x4000176c; +/* rcTxUpdatePer = 0x40001770;*/ +rcUpdateAckSnr = 0x40001774; +/*rcUpdateRate = 0x40001778;*/ +/* rcUpdateTxDone = 0x4000177c; */ +rcUpdateTxDoneAmpdu2 = 0x40001780; +rcUpSched = 0x40001784; +rssi_margin = 0x40001788; +rx11NRate2AMPDULimit = 0x4000178c; +TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001790; +TRC_AMPDU_PER_UP_THRESHOLD = 0x40001794; +trc_calc_duration = 0x40001798; +trc_isTxAmpduOperational = 0x4000179c; +trc_onAmpduOp = 0x400017a0; +TRC_PER_IS_GOOD = 0x400017a4; +trc_SetTxAmpduState = 0x400017a8; +trc_tid_isTxAmpduOperational = 0x400017ac; +trcAmpduSetState = 0x400017b0; +wDev_AppendRxBlocks = 0x400017b8; +wDev_DiscardFrame = 0x400017bc; +wDev_GetNoiseFloor = 0x400017c0; +wDev_IndicateAmpdu = 0x400017c4; +/*wDev_IndicateFrame = 0x400017c8;*/ +wdev_bank_store = 0x400017cc; +wdev_bank_load = 0x400017d0; +wdev_mac_reg_load = 0x400017d4; +wdev_mac_reg_store = 0x400017d8; +wdev_mac_special_reg_load = 0x400017dc; +wdev_mac_special_reg_store = 0x400017e0; +wdev_mac_wakeup = 0x400017e4; +wdev_mac_sleep = 0x400017e8; +hal_mac_is_dma_enable = 0x400017ec; +/*wDev_ProcessFiq = 0x400017f0;*/ +/*wDev_ProcessRxSucData = 0x400017f4;*/ +wdevProcessRxSucDataAll = 0x400017f8; +wdev_csi_len_align = 0x400017fc; +ppDequeueTxDone_Locked = 0x40001800; +/*pm_tx_data_done_process = 0x40001808;*/ +config_is_cache_tx_buf_enabled = 0x4000180c; +//ppMapWaitTxq = 0x40001810; +ppProcessWaitingQueue = 0x40001814; +ppDisableQueue = 0x40001818; +pm_allow_tx = 0x4000181c; +/* Data (.data, .bss, .rodata) */ +our_instances_ptr = 0x3ff1ee44; +pTxRx = 0x3fcdf968; +lmacConfMib_ptr = 0x3fcdf964; +our_wait_eb = 0x3fcdf960; +our_tx_eb = 0x3fcdf95c; +pp_wdev_funcs = 0x3fcdf958; +g_osi_funcs_p = 0x3fcdf954; +wDevCtrl_ptr = 0x3fcdf950; +g_wdev_last_desc_reset_ptr = 0x3ff1ee40; +wDevMacSleep_ptr = 0x3fcdf94c; +g_lmac_cnt_ptr = 0x3fcdf948; +our_controls_ptr = 0x3ff1ee3c; +pp_sig_cnt_ptr = 0x3fcdf944; +g_eb_list_desc_ptr = 0x3fcdf940; +s_fragment_ptr = 0x3fcdf93c; +if_ctrl_ptr = 0x3fcdf938; +g_intr_lock_mux = 0x3fcdf934; +g_wifi_global_lock = 0x3fcdf930; +s_wifi_queue = 0x3fcdf92c; +pp_task_hdl = 0x3fcdf928; +s_pp_task_create_sem = 0x3fcdf924; +s_pp_task_del_sem = 0x3fcdf920; +g_wifi_menuconfig_ptr = 0x3fcdf91c; +xphyQueue = 0x3fcdf918; +ap_no_lr_ptr = 0x3fcdf914; +rc11BSchedTbl_ptr = 0x3fcdf910; +rc11NSchedTbl_ptr = 0x3fcdf90c; +rcLoRaSchedTbl_ptr = 0x3fcdf908; +BasicOFDMSched_ptr = 0x3fcdf904; +trc_ctl_ptr = 0x3fcdf900; +g_pm_cnt_ptr = 0x3fcdf8fc; +g_pm_ptr = 0x3fcdf8f8; +g_pm_cfg_ptr = 0x3fcdf8f4; +g_esp_mesh_quick_funcs_ptr = 0x3fcdf8f0; +g_txop_queue_status_ptr = 0x3fcdf8ec; +g_mac_sleep_en_ptr = 0x3fcdf8e8; +g_mesh_is_root_ptr = 0x3fcdf8e4; +g_mesh_topology_ptr = 0x3fcdf8e0; +g_mesh_init_ps_type_ptr = 0x3fcdf8dc; +g_mesh_is_started_ptr = 0x3fcdf8d8; +g_config_func = 0x3fcdf8d4; +g_net80211_tx_func = 0x3fcdf8d0; +g_timer_func = 0x3fcdf8cc; +s_michael_mic_failure_cb = 0x3fcdf8c8; +wifi_sta_rx_probe_req = 0x3fcdf8c4; +g_tx_done_cb_func = 0x3fcdf8c0; +g_per_conn_trc = 0x3fcdf874; +s_encap_amsdu_func = 0x3fcdf870; + + +/*************************************** + Group rom_net80211 + ***************************************/ + +/* Functions */ +esp_net80211_rom_version_get = 0x40001820; +ampdu_dispatch = 0x40001824; +ampdu_dispatch_all = 0x40001828; +ampdu_dispatch_as_many_as_possible = 0x4000182c; +ampdu_dispatch_movement = 0x40001830; +ampdu_dispatch_upto = 0x40001834; +chm_is_at_home_channel = 0x40001838; +cnx_node_is_existing = 0x4000183c; +cnx_node_search = 0x40001840; +ic_ebuf_recycle_rx = 0x40001844; +ic_ebuf_recycle_tx = 0x40001848; +ic_reset_rx_ba = 0x4000184c; +ieee80211_align_eb = 0x40001850; +ieee80211_ampdu_reorder = 0x40001854; +ieee80211_ampdu_start_age_timer = 0x40001858; +/*ieee80211_encap_esfbuf = 0x4000185c;*/ +ieee80211_is_tx_allowed = 0x40001860; +ieee80211_output_pending_eb = 0x40001864; +/*ieee80211_output_process = 0x40001868;*/ +ieee80211_set_tx_desc = 0x4000186c; +rom_sta_input = 0x40001870; +wifi_get_macaddr = 0x40001874; +wifi_rf_phy_disable = 0x40001878; +wifi_rf_phy_enable = 0x4000187c; +ic_ebuf_alloc = 0x40001880; +ieee80211_classify = 0x40001884; +ieee80211_copy_eb_header = 0x40001888; +ieee80211_recycle_cache_eb = 0x4000188c; +ieee80211_search_node = 0x40001890; +roundup2 = 0x40001894; +ieee80211_crypto_encap = 0x40001898; +/* ieee80211_crypto_decap = 0x4000189c; */ +/* ieee80211_decap = 0x400018a0; */ +ieee80211_set_tx_pti = 0x400018a4; +wifi_is_started = 0x400018a8; +/* Data (.data, .bss, .rodata) */ +net80211_funcs = 0x3fcdf86c; +g_scan = 0x3fcdf868; +g_chm = 0x3fcdf864; +g_ic_ptr = 0x3fcdf860; +g_hmac_cnt_ptr = 0x3fcdf85c; +g_tx_cacheq_ptr = 0x3fcdf858; +s_netstack_free = 0x3fcdf854; +mesh_rxcb = 0x3fcdf850; +sta_rxcb = 0x3fcdf84c; + + +/*************************************** + Group rom_coexist + ***************************************/ + +/* Functions */ +esp_coex_rom_version_get = 0x400018ac; +coex_bt_release = 0x400018b0; +coex_bt_request = 0x400018b4; +coex_core_ble_conn_dyn_prio_get = 0x400018b8; +coex_core_event_duration_get = 0x400018bc; +coex_core_pti_get = 0x400018c0; +coex_core_release = 0x400018c4; +coex_core_request = 0x400018c8; +coex_core_status_get = 0x400018cc; +/*coex_core_timer_idx_get = 0x400018d0;*/ +coex_event_duration_get = 0x400018d4; +coex_hw_timer_disable = 0x400018d8; +coex_hw_timer_enable = 0x400018dc; +coex_hw_timer_set = 0x400018e0; +coex_schm_interval_set = 0x400018e4; +coex_schm_lock = 0x400018e8; +coex_schm_unlock = 0x400018ec; +coex_status_get = 0x400018f0; +coex_wifi_release = 0x400018f4; +esp_coex_ble_conn_dynamic_prio_get = 0x400018f8; +/* Data (.data, .bss, .rodata) */ +coex_env_ptr = 0x3fcdf848; +coex_pti_tab_ptr = 0x3fcdf844; +coex_schm_env_ptr = 0x3fcdf840; +coexist_funcs = 0x3fcdf83c; +g_coa_funcs_p = 0x3fcdf838; +g_coex_param_ptr = 0x3fcdf834; + + +/*************************************** + Group rom_phy + ***************************************/ + +/* Functions */ +phy_get_romfuncs = 0x400018fc; +rom_abs_temp = 0x40001900; +rom_bb_bss_cbw40_dig = 0x40001904; +rom_bb_wdg_test_en = 0x40001908; +rom_bb_wdt_get_status = 0x4000190c; +rom_bb_wdt_int_enable = 0x40001910; +rom_bb_wdt_rst_enable = 0x40001914; +rom_bb_wdt_timeout_clear = 0x40001918; +rom_cbw2040_cfg = 0x4000191c; +rom_check_noise_floor = 0x40001920; +rom_chip_i2c_readReg = 0x40001924; +rom_chip_i2c_writeReg = 0x40001928; +rom_correct_rf_ana_gain = 0x4000192c; +rom_dc_iq_est = 0x40001930; +rom_disable_agc = 0x40001934; +rom_en_pwdet = 0x40001938; +rom_enable_agc = 0x4000193c; +rom_get_bbgain_db = 0x40001940; +rom_get_data_sat = 0x40001944; +rom_get_i2c_read_mask = 0x40001948; +rom_get_pwctrl_correct = 0x4000194c; +rom_get_rf_gain_qdb = 0x40001950; +rom_i2c_readReg = 0x40001954; +rom_i2c_readReg_Mask = 0x40001958; +rom_i2c_writeReg = 0x4000195c; +rom_i2c_writeReg_Mask = 0x40001960; +/* rom_index_to_txbbgain = 0x40001964; */ +rom_iq_est_disable = 0x40001968; +rom_iq_est_enable = 0x4000196c; +rom_linear_to_db = 0x40001970; +rom_loopback_mode_en = 0x40001974; +rom_mhz2ieee = 0x40001978; +rom_noise_floor_auto_set = 0x4000197c; +rom_pbus_debugmode = 0x40001980; +rom_pbus_force_mode = 0x40001984; +rom_pbus_force_test = 0x40001988; +rom_pbus_rd = 0x4000198c; +rom_pbus_rd_addr = 0x40001990; +rom_pbus_rd_shift = 0x40001994; +rom_pbus_set_dco = 0x40001998; +rom_pbus_set_rxgain = 0x4000199c; +rom_pbus_workmode = 0x400019a0; +rom_pbus_xpd_rx_off = 0x400019a4; +rom_pbus_xpd_rx_on = 0x400019a8; +rom_pbus_xpd_tx_off = 0x400019ac; +/* rom_pbus_xpd_tx_on = 0x400019b0; */ +rom_phy_byte_to_word = 0x400019b4; +rom_phy_disable_cca = 0x400019b8; +rom_phy_enable_cca = 0x400019bc; +rom_phy_get_noisefloor = 0x400019c0; +rom_phy_get_rx_freq = 0x400019c4; +rom_phy_set_bbfreq_init = 0x400019c8; +rom_pow_usr = 0x400019cc; +rom_pwdet_sar2_init = 0x400019d0; +rom_read_hw_noisefloor = 0x400019d4; +rom_read_sar_dout = 0x400019d8; +rom_set_cal_rxdc = 0x400019dc; +rom_set_chan_cal_interp = 0x400019e0; +rom_set_loopback_gain = 0x400019e4; +rom_set_noise_floor = 0x400019e8; +rom_set_rxclk_en = 0x400019ec; +/* rom_set_tx_dig_gain = 0x400019f0; */ +/* rom_set_txcap_reg = 0x400019f4; */ +rom_set_txclk_en = 0x400019f8; +rom_spur_cal = 0x400019fc; +rom_spur_reg_write_one_tone = 0x40001a00; +rom_target_power_add_backoff = 0x40001a04; +rom_tx_pwctrl_bg_init = 0x40001a08; +/* rom_txbbgain_to_index = 0x40001a0c; */ +rom_wifi_11g_rate_chg = 0x40001a10; +rom_write_gain_mem = 0x40001a14; +chip726_phyrom_version = 0x40001a18; +rom_disable_wifi_agc = 0x40001a1c; +rom_enable_wifi_agc = 0x40001a20; +rom_set_tx_gain_table = 0x40001a24; +rom_bt_index_to_bb = 0x40001a28; +rom_bt_bb_to_index = 0x40001a2c; +rom_wr_bt_tx_atten = 0x40001a30; +rom_wr_bt_tx_gain_mem = 0x40001a34; +rom_spur_coef_cfg = 0x40001a38; +rom_bb_bss_cbw40 = 0x40001a3c; +rom_set_cca = 0x40001a40; +rom_tx_paon_set = 0x40001a44; +rom_i2cmst_reg_init = 0x40001a48; +rom_iq_corr_enable = 0x40001a4c; +rom_fe_reg_init = 0x40001a50; +/* rom_agc_reg_init = 0x40001a54; */ +/* rom_bb_reg_init = 0x40001a58; */ +rom_mac_enable_bb = 0x40001a5c; +rom_bb_wdg_cfg = 0x40001a60; +rom_force_txon = 0x40001a64; +rom_fe_txrx_reset = 0x40001a68; +rom_set_rx_comp = 0x40001a6c; +/* rom_set_pbus_reg = 0x40001a70; */ +rom_write_chan_freq = 0x40001a74; +/* rom_phy_xpd_rf = 0x40001a78; */ +rom_set_xpd_sar = 0x40001a7c; +rom_write_dac_gain2 = 0x40001a80; +rom_rtc_sar2_init = 0x40001a84; +rom_get_target_power_offset = 0x40001a88; +/* rom_write_txrate_power_offset = 0x40001a8c; */ +rom_get_rate_fcc_index = 0x40001a90; +rom_get_rate_target_power = 0x40001a94; +rom_write_wifi_dig_gain = 0x40001a98; +rom_bt_correct_rf_ana_gain = 0x40001a9c; +rom_pkdet_vol_start = 0x40001aa0; +rom_read_sar2_code = 0x40001aa4; +rom_get_sar2_vol = 0x40001aa8; +rom_get_pll_vol = 0x40001aac; +rom_get_phy_target_power = 0x40001ab0; +/* rom_temp_to_power = 0x40001ab4; */ +rom_phy_track_pll_cap = 0x40001ab8; +rom_phy_pwdet_always_en = 0x40001abc; +rom_phy_pwdet_onetime_en = 0x40001ac0; +rom_get_i2c_mst0_mask = 0x40001ac4; +rom_get_i2c_hostid = 0x40001ac8; +rom_enter_critical_phy = 0x40001acc; +rom_exit_critical_phy = 0x40001ad0; +rom_chip_i2c_readReg_org = 0x40001ad4; +rom_i2c_paral_set_mst0 = 0x40001ad8; +rom_i2c_paral_set_read = 0x40001adc; +rom_i2c_paral_read = 0x40001ae0; +rom_i2c_paral_write = 0x40001ae4; +rom_i2c_paral_write_num = 0x40001ae8; +rom_i2c_paral_write_mask = 0x40001aec; +rom_bb_bss_cbw40_ana = 0x40001af0; +rom_chan_to_freq = 0x40001af4; +/* rom_open_i2c_xpd = 0x40001af8; */ +rom_dac_rate_set = 0x40001afc; +/* rom_tsens_read_init = 0x40001b00; */ +/* rom_tsens_code_read = 0x40001b04; */ +rom_tsens_index_to_dac = 0x40001b08; +rom_tsens_index_to_offset = 0x40001b0c; +/* rom_tsens_dac_cal = 0x40001b10; */ +rom_code_to_temp = 0x40001b14; +rom_write_pll_cap_mem = 0x40001b18; +rom_pll_correct_dcap = 0x40001b1c; +rom_phy_en_hw_set_freq = 0x40001b20; +rom_phy_dis_hw_set_freq = 0x40001b24; +/* rom_pll_vol_cal = 0x40001b28; */ diff --git a/targets/esp8266.json b/targets/esp8266.json new file mode 100644 index 00000000..bb02c3db --- /dev/null +++ b/targets/esp8266.json @@ -0,0 +1,18 @@ +{ + "inherits": ["xtensa"], + "cpu": "esp8266", + "features": "+debug,+density,+exception,+extendedl32r,+highpriinterrupts,+interrupt,+mul32,+nsa,+prid,+regprotect,+rvector,+timerint", + "build-tags": ["esp8266", "esp"], + "scheduler": "tasks", + "linker": "ld.lld", + "default-stack-size": 2048, + "rtlib": "compiler-rt", + "libc": "picolibc", + "linkerscript": "targets/esp8266.ld", + "extra-files": [ + "src/device/esp/esp8266.S", + "src/internal/task/task_stack_esp8266.S" + ], + "binary-format": "esp8266", + "flash-command": "esptool.py --chip=esp8266 --port {port} write_flash 0x00000 {bin} -fm qio" +} diff --git a/targets/esp8266.ld b/targets/esp8266.ld new file mode 100644 index 00000000..9cbc42c1 --- /dev/null +++ b/targets/esp8266.ld @@ -0,0 +1,109 @@ +/* Linker script for the ESP8266 */ + +MEMORY +{ + /* Data RAM. Allows byte access. */ + DRAM (rw) : ORIGIN = 0x3FFE8000, LENGTH = 80K + /* Instruction RAM. */ + IRAM (x) : ORIGIN = 0x40100000, LENGTH = 32K +} + +/* The entry point. It is set in the image flashed to the chip, so must be + * defined. + */ +ENTRY(main) + +SECTIONS +{ + /* Mutable global variables. + */ + .data : ALIGN(4) + { + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + } >DRAM + + /* Constant global variables. + * Note that they still need to be loaded in RAM because the ESP8266 doesn't + * allow byte access to flash. + */ + .rodata : ALIGN(4) + { + *(.rodata) + *(.rodata.*) + } >DRAM + + /* Global variables that are mutable and zero-initialized. + */ + .bss (NOLOAD) : ALIGN(4) + { + . = ALIGN (4); + _sbss = ABSOLUTE(.); + *(.bss) + *(.bss.*) + . = ALIGN (4); + _ebss = ABSOLUTE(.); + } >DRAM + + /* Constant literals and code. Loaded into IRAM for now. Eventually, most + * code should be executed directly from flash. + * Note that literals must be before code for the l32r instruction to work. + */ + .text : ALIGN(4) + { + *(.literal .text) + *(.literal.* .text.*) + } >IRAM +} + +_globals_start = _sdata; +_globals_end = _ebss; +_heap_start = _ebss; +_heap_end = ORIGIN(DRAM) + LENGTH(DRAM); + +/* It appears that the stack is set to 0x3ffffff0 when main is called. + * Be conservative and scan all the way up to the end of the RAM. + */ +_stack_top = 0x40000000; + +/* Functions normally provided by a libc. + * Source: + * https://github.com/espressif/ESP8266_NONOS_SDK/blob/master/ld/eagle.rom.addr.v6.ld + */ +memcpy = 0x4000df48; +memmove = 0x4000e04c; +memset = 0x4000e190; + +/* Compiler runtime functions provided by the ROM. + * Source: + * https://github.com/espressif/ESP8266_NONOS_SDK/blob/master/ld/eagle.rom.addr.v6.ld + */ +__adddf3 = 0x4000c538; +__addsf3 = 0x4000c180; +__divdf3 = 0x4000cb94; +__divdi3 = 0x4000ce60; +__divsi3 = 0x4000dc88; +__extendsfdf2 = 0x4000cdfc; +__fixdfsi = 0x4000ccb8; +__fixunsdfsi = 0x4000cd00; +__fixunssfsi = 0x4000c4c4; +__floatsidf = 0x4000e2f0; +__floatsisf = 0x4000e2ac; +__floatunsidf = 0x4000e2e8; +__floatunsisf = 0x4000e2a4; +__muldf3 = 0x4000c8f0; +__muldi3 = 0x40000650; +__mulsf3 = 0x4000c3dc; +__subdf3 = 0x4000c688; +__subsf3 = 0x4000c268; +__truncdfsf2 = 0x4000cd5c; +__udivdi3 = 0x4000d310; +__udivsi3 = 0x4000e21c; +__umoddi3 = 0x4000d770; +__umodsi3 = 0x4000e268; +__umulsidi3 = 0x4000dcf0; + +/* Proprietary ROM function needed for proper clock configuration. + */ +rom_i2c_writeReg = 0x400072d8; diff --git a/targets/fe310.json b/targets/fe310.json new file mode 100644 index 00000000..cd92c4fb --- /dev/null +++ b/targets/fe310.json @@ -0,0 +1,6 @@ +{ + "inherits": ["riscv32"], + "cpu": "sifive-e31", + "features": "+32bit,+a,+c,+m,+zmmul,-b,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-f,-h,-relax,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xesppie,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b", + "build-tags": ["fe310", "sifive"] +} diff --git a/targets/feather-m0-express.json b/targets/feather-m0-express.json new file mode 100644 index 00000000..5f5214e1 --- /dev/null +++ b/targets/feather-m0-express.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["feather_m0_express"], + "serial": "usb", + "serial-port": ["239a:801b"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["FEATHERBOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/feather-m0.json b/targets/feather-m0.json new file mode 100644 index 00000000..fa965db6 --- /dev/null +++ b/targets/feather-m0.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["feather_m0"], + "serial": "usb", + "serial-port": ["239a:801b", "239a:800b"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["FEATHERBOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/feather-m4-can.json b/targets/feather-m4-can.json new file mode 100644 index 00000000..91ede189 --- /dev/null +++ b/targets/feather-m4-can.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsame51j19a"], + "build-tags": ["feather_m4_can"], + "serial": "usb", + "serial-port": ["239a:80cd"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["FTHRCANBOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/feather-m4.json b/targets/feather-m4.json new file mode 100644 index 00000000..66eac03d --- /dev/null +++ b/targets/feather-m4.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd51j19a"], + "build-tags": ["feather_m4"], + "serial": "usb", + "serial-port": ["239a:8022"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["FEATHERBOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/feather-nrf52840-sense.json b/targets/feather-nrf52840-sense.json new file mode 100644 index 00000000..8a4e862a --- /dev/null +++ b/targets/feather-nrf52840-sense.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["feather_nrf52840_sense"], + "serial-port": ["239a:8087", "239a:8088"], + "msd-volume-name": ["FTHRSNSBOOT"] +} diff --git a/targets/feather-nrf52840.json b/targets/feather-nrf52840.json new file mode 100644 index 00000000..bd4c488d --- /dev/null +++ b/targets/feather-nrf52840.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["feather_nrf52840"], + "serial-port": ["239a:8029", "239a:802a"], + "msd-volume-name": ["FTHR840BOOT"] +} diff --git a/targets/feather-rp2040-boot-stage2.S b/targets/feather-rp2040-boot-stage2.S new file mode 100644 index 00000000..fad30890 --- /dev/null +++ b/targets/feather-rp2040-boot-stage2.S @@ -0,0 +1,17 @@ +// Adafruit Feather RP2040 Stage 2 Bootloader + +// +// This file defines the parameters specific to the flash-chip found +// on the Adafruit Feather RP2040. The generic implementation is in +// rp2040-boot-stage2.S +// + +#define BOARD_PICO_FLASH_SPI_CLKDIV 4 +#define BOARD_CMD_READ 0xe7 +#define BOARD_QUAD_OK 1 +#define BOARD_QUAD_ENABLE_STATUS_BYTE 2 +#define BOARD_QUAD_ENABLE_BIT_MASK 2 +#define BOARD_SPLIT_STATUS_WRITE 1 +#define BOARD_WAIT_CYCLES 2 + +#include "rp2040-boot-stage2.S" diff --git a/targets/feather-rp2040.json b/targets/feather-rp2040.json new file mode 100644 index 00000000..871cdb45 --- /dev/null +++ b/targets/feather-rp2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["239a:80f1"], + "build-tags": ["feather_rp2040"], + "ldflags": [ + "--defsym=__flash_size=8192K" + ], + "extra-files": [ + "targets/feather-rp2040-boot-stage2.S" + ] +} diff --git a/targets/feather-stm32f405.json b/targets/feather-stm32f405.json new file mode 100644 index 00000000..3d824d1e --- /dev/null +++ b/targets/feather-stm32f405.json @@ -0,0 +1,15 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["feather_stm32f405", "stm32f405", "stm32f4", "stm32"], + "serial": "uart", + "automatic-stack-size": false, + "linkerscript": "targets/stm32f405.ld", + "extra-files": [ + "src/device/stm32/stm32f405.s" + ], + "flash-method": "command", + "flash-command": "dfu-util --alt 0 --dfuse-address 0x08000000 --download {bin}", + "openocd-transport": "swd", + "openocd-interface": "jlink", + "openocd-target": "stm32f4x" +} diff --git a/targets/gameboy-advance.json b/targets/gameboy-advance.json new file mode 100644 index 00000000..72ab6e3a --- /dev/null +++ b/targets/gameboy-advance.json @@ -0,0 +1,28 @@ +{ + "llvm-target": "armv4t-unknown-unknown-eabi", + "cpu": "arm7tdmi", + "features": "+armv4t,+strict-align,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-dsp,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-hwdiv,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-neon,-pacbti,-ras,-sb,-sha2,-thumb-mode,-vfp2,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp", + "build-tags": ["gameboyadvance", "arm7tdmi", "baremetal", "linux", "arm"], + "goos": "linux", + "goarch": "arm", + "linker": "ld.lld", + "rtlib": "compiler-rt", + "libc": "picolibc", + "cflags": [ + "-Werror", + "-fshort-enums", + "-fomit-frame-pointer", + "-fno-exceptions", "-fno-unwind-tables", "-fno-asynchronous-unwind-tables", + "-ffunction-sections", "-fdata-sections" + ], + "ldflags": [ + "--gc-sections" + ], + "linkerscript": "targets/gameboy-advance.ld", + "extra-files": [ + "targets/gameboy-advance.s", + "src/runtime/asm_arm.S" + ], + "gdb": ["gdb-multiarch"], + "emulator": "mgba -3 {}" +} diff --git a/targets/gameboy-advance.ld b/targets/gameboy-advance.ld new file mode 100644 index 00000000..566f78ea --- /dev/null +++ b/targets/gameboy-advance.ld @@ -0,0 +1,84 @@ +OUTPUT_ARCH(arm) +ENTRY(_start) + +/* Note: iwram is reduced by 96 bytes because the last part of that RAM + * (starting at 0x03007FA0) is used for interrupt handling. + */ +MEMORY { + ewram : ORIGIN = 0x02000000, LENGTH = 256K /* on-board work RAM (2 wait states) */ + iwram : ORIGIN = 0x03000000, LENGTH = 32K-96 /* in-chip work RAM (faster) */ + rom : ORIGIN = 0x08000000, LENGTH = 32M /* flash ROM */ +} + +__stack_size_irq = 1K; +__stack_size_usr = 2K; + +SECTIONS +{ + .text : + { + KEEP (*(.init)) + *(.text) + *(.text.*) + . = ALIGN(4); + } >rom + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + } >rom + + /* Put the stack at the bottom of RAM, so that the application will + * crash on stack overflow instead of silently corrupting memory. + * See: http://blog.japaric.io/stack-overflow-protection/ */ + .stack (NOLOAD) : + { + . = ALIGN(4); + _stack_top_irq = .; + . += __stack_size_irq; + _stack_top = .; + . += __stack_size_usr; + } >iwram + + /* Start address (in flash) of .data, used by startup code. */ + _sidata = LOADADDR(.data); + + /* Globals with initial value */ + .data : + { + . = ALIGN(4); + _sdata = .; /* used by startup code */ + *(.data) + *(.data.*) + *(.iwram .iwram.*) + . = ALIGN(4); + _edata = .; /* used by startup code */ + } >iwram AT>rom + + /* Zero-initialized globals */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* used by startup code */ + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* used by startup code */ + } >iwram + + /DISCARD/ : + { + *(.ARM.exidx) /* causes 'no memory region specified' error in lld */ + *(.ARM.exidx.*) /* causes spurious 'undefined reference' errors */ + } +} + +/* For the memory allocator. */ +_heap_start = ORIGIN(ewram); +_heap_end = ORIGIN(ewram) + LENGTH(ewram); +_globals_start = _sdata; +_globals_end = _ebss; diff --git a/targets/gameboy-advance.s b/targets/gameboy-advance.s new file mode 100644 index 00000000..7da6f741 --- /dev/null +++ b/targets/gameboy-advance.s @@ -0,0 +1,77 @@ +.section .init +.global _start +.align +.arm + +_start: + b start_vector + + // ROM header + .byte 0x24,0xff,0xae,0x51,0x69,0x9a,0xa2,0x21,0x3d,0x84,0x82,0x0a,0x84,0xe4,0x09,0xad + .byte 0x11,0x24,0x8b,0x98,0xc0,0x81,0x7f,0x21,0xa3,0x52,0xbe,0x19,0x93,0x09,0xce,0x20 + .byte 0x10,0x46,0x4a,0x4a,0xf8,0x27,0x31,0xec,0x58,0xc7,0xe8,0x33,0x82,0xe3,0xce,0xbf + .byte 0x85,0xf4,0xdf,0x94,0xce,0x4b,0x09,0xc1,0x94,0x56,0x8a,0xc0,0x13,0x72,0xa7,0xfc + .byte 0x9f,0x84,0x4d,0x73,0xa3,0xca,0x9a,0x61,0x58,0x97,0xa3,0x27,0xfc,0x03,0x98,0x76 + .byte 0x23,0x1d,0xc7,0x61,0x03,0x04,0xae,0x56,0xbf,0x38,0x84,0x00,0x40,0xa7,0x0e,0xfd + .byte 0xff,0x52,0xfe,0x03,0x6f,0x95,0x30,0xf1,0x97,0xfb,0xc0,0x85,0x60,0xd6,0x80,0x25 + .byte 0xa9,0x63,0xbe,0x03,0x01,0x4e,0x38,0xe2,0xf9,0xa2,0x34,0xff,0xbb,0x3e,0x03,0x44 + .byte 0x78,0x00,0x90,0xcb,0x88,0x11,0x3a,0x94,0x65,0xc0,0x7c,0x63,0x87,0xf0,0x3c,0xaf + .byte 0xd6,0x25,0xe4,0x8b,0x38,0x0a,0xac,0x72,0x21,0xd4,0xf8,0x07 + + // Game title + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + + // Game code + .byte 0x00,0x00,0x00,0x00 + + // Maker code + .byte 0x00,0x00 + + // Fixed value + .byte 0x96 + + // Main unit code + .byte 0x00 + + // Device type (0x00 retail, 0x80 debug) + .byte 0x00 + + // Reserved + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00 + + // Software version + .byte 0x00 + + // Complement check + .byte 0x51 + + // Reserved area + .space 98 + +start_vector: + // Configure stacks + mov r0, #0x12 // Switch to IRQ Mode + msr cpsr, r0 + ldr sp, =_stack_top_irq // Set IRQ stack + mov r0, #0x1f // Switch to System Mode + msr cpsr, r0 + ldr sp, =_stack_top // Set user stack + + // Configure interrupt handler + mov r0, #0x4000000 // REG_BASE + ldr r1, =handleInterruptARM + str r1, [r0, #-4] // actually storing to 0x03007FFC due to mirroring + + // Enable interrupts + mov r1, #1 + str r1, [r0, #0x208] // 0x04000208 Interrupt Master Enable + + // Jump to user code (switching to Thumb mode) + ldr r3, =main + bx r3 + +// Small interrupt handler that immediately jumps to a function defined in the +// program (in Thumb) for further processing. +handleInterruptARM: + ldr r0, =handleInterrupt + bx r0 diff --git a/targets/gemma-m0.json b/targets/gemma-m0.json new file mode 100644 index 00000000..7bced2a3 --- /dev/null +++ b/targets/gemma-m0.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd21e18a"], + "build-tags": ["gemma_m0"], + "serial": "usb", + "serial-port": ["239a:801e"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["GEMMABOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/gnse.json b/targets/gnse.json new file mode 100644 index 00000000..5453c7f9 --- /dev/null +++ b/targets/gnse.json @@ -0,0 +1,12 @@ +{ + "inherits": [ + "stm32wl5x_cm4" + ], + "build-tags": [ + "gnse" + ], + "serial": "uart", + "flash-method": "openocd", + "openocd-interface": "stlink", + "openocd-target": "stm32wlx" +} diff --git a/targets/gobadge.json b/targets/gobadge.json new file mode 100644 index 00000000..527d02d5 --- /dev/null +++ b/targets/gobadge.json @@ -0,0 +1,3 @@ +{ + "inherits": ["pybadge"] +} diff --git a/targets/gopher-badge.json b/targets/gopher-badge.json new file mode 100644 index 00000000..ec50b303 --- /dev/null +++ b/targets/gopher-badge.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:0003"], + "build-tags": ["gopher_badge"], + "ldflags": [ + "--defsym=__flash_size=8M" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/gopherbot.json b/targets/gopherbot.json new file mode 100644 index 00000000..30c54df8 --- /dev/null +++ b/targets/gopherbot.json @@ -0,0 +1,3 @@ +{ + "inherits": ["circuitplay-express"] +} diff --git a/targets/gopherbot2.json b/targets/gopherbot2.json new file mode 100644 index 00000000..1c48ef71 --- /dev/null +++ b/targets/gopherbot2.json @@ -0,0 +1,3 @@ +{ + "inherits": ["circuitplay-bluefruit"] +} diff --git a/targets/grandcentral-m4.json b/targets/grandcentral-m4.json new file mode 100644 index 00000000..c1413515 --- /dev/null +++ b/targets/grandcentral-m4.json @@ -0,0 +1,11 @@ +{ + "inherits": ["atsamd51p20a"], + "build-tags": ["grandcentral_m4"], + "serial": "usb", + "serial-port": ["239a:8031"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["GCM4BOOT"], + "msd-firmware-name": "firmware.uf2", + "openocd-interface": "jlink" +} diff --git a/targets/hifive1b.json b/targets/hifive1b.json new file mode 100644 index 00000000..6f0ec6c2 --- /dev/null +++ b/targets/hifive1b.json @@ -0,0 +1,10 @@ +{ + "inherits": ["fe310"], + "build-tags": ["hifive1b"], + "serial": "uart", + "linkerscript": "targets/hifive1b.ld", + "flash-method": "msd", + "msd-volume-name": ["HiFive"], + "msd-firmware-name": "firmware.hex", + "jlink-device": "fe310" +} diff --git a/targets/hifive1b.ld b/targets/hifive1b.ld new file mode 100644 index 00000000..29ec78ad --- /dev/null +++ b/targets/hifive1b.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x20010000, LENGTH = 0x6a120 + RAM (xrw) : ORIGIN = 0x80000000, LENGTH = 0x4000 +} + +_stack_size = 2K; + +INCLUDE "targets/riscv.ld" diff --git a/targets/hw-651-s110v8.json b/targets/hw-651-s110v8.json new file mode 100644 index 00000000..50030cec --- /dev/null +++ b/targets/hw-651-s110v8.json @@ -0,0 +1,3 @@ +{ + "inherits": ["hw-651", "nrf51-s110v8"] +} diff --git a/targets/hw-651.json b/targets/hw-651.json new file mode 100644 index 00000000..a5ed5eeb --- /dev/null +++ b/targets/hw-651.json @@ -0,0 +1,7 @@ +{ + "inherits": ["nrf51"], + "build-tags": ["hw_651"], + "serial": "uart", + "flash-method": "openocd", + "openocd-interface": "cmsis-dap" +} diff --git a/targets/itsybitsy-m0.json b/targets/itsybitsy-m0.json new file mode 100644 index 00000000..d8b4d5d4 --- /dev/null +++ b/targets/itsybitsy-m0.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["itsybitsy_m0"], + "serial": "usb", + "serial-port": ["239a:800f", "239a:8012"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["ITSYBOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/itsybitsy-m4.json b/targets/itsybitsy-m4.json new file mode 100644 index 00000000..0134e2f3 --- /dev/null +++ b/targets/itsybitsy-m4.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd51g19a"], + "build-tags": ["itsybitsy_m4"], + "serial": "usb", + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "serial-port": ["239a:802b"], + "msd-volume-name": ["ITSYM4BOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/itsybitsy-nrf52840.json b/targets/itsybitsy-nrf52840.json new file mode 100644 index 00000000..d294ae5b --- /dev/null +++ b/targets/itsybitsy-nrf52840.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["itsybitsy_nrf52840"], + "serial-port": ["239A:8052", "239A:8051"], + "msd-volume-name": ["ITSY840BOOT"] +} diff --git a/targets/k210.json b/targets/k210.json new file mode 100644 index 00000000..2140f459 --- /dev/null +++ b/targets/k210.json @@ -0,0 +1,6 @@ +{ + "inherits": ["riscv64"], + "features": "+64bit,+a,+c,+d,+f,+m,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-h,-relax,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xesppie,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b", + "build-tags": ["k210", "kendryte"], + "code-model": "medium" +} diff --git a/targets/kb2040.json b/targets/kb2040.json new file mode 100644 index 00000000..1fc045b5 --- /dev/null +++ b/targets/kb2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["239a:8106"], + "build-tags": ["kb2040"], + "ldflags": [ + "--defsym=__flash_size=8192K" + ], + "extra-files": [ + "targets/qtpy-rp2040-boot-stage2.S" + ] +} diff --git a/targets/lgt92.json b/targets/lgt92.json new file mode 100644 index 00000000..aadcc6c4 --- /dev/null +++ b/targets/lgt92.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "stm32l0x2" + ], + "build-tags": [ + "lgt92" + ], + "serial": "uart", + "linkerscript": "targets/stm32l072czt6.ld", + "flash-method": "openocd", + "openocd-interface": "stlink", + "openocd-target": "stm32l0" +} diff --git a/targets/lm3s6965.ld b/targets/lm3s6965.ld new file mode 100644 index 00000000..7ac5730e --- /dev/null +++ b/targets/lm3s6965.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000, LENGTH = 256K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/lorae5.json b/targets/lorae5.json new file mode 100644 index 00000000..9b33125c --- /dev/null +++ b/targets/lorae5.json @@ -0,0 +1,12 @@ +{ + "inherits": [ + "stm32wle5" + ], + "build-tags": [ + "lorae5" + ], + "serial": "uart", + "flash-method": "openocd", + "openocd-interface": "stlink-v2", + "openocd-target": "stm32wlx" +} \ No newline at end of file diff --git a/targets/m5paper.json b/targets/m5paper.json new file mode 100644 index 00000000..9ee5d43b --- /dev/null +++ b/targets/m5paper.json @@ -0,0 +1,5 @@ +{ + "inherits": ["esp32"], + "build-tags": ["m5paper"], + "serial-port": ["1a86:55d4"] +} diff --git a/targets/m5stack-core2.json b/targets/m5stack-core2.json new file mode 100644 index 00000000..1bb4c9e3 --- /dev/null +++ b/targets/m5stack-core2.json @@ -0,0 +1,5 @@ +{ + "inherits": ["esp32"], + "build-tags": ["m5stack_core2"], + "serial-port": ["10c4:ea60"] +} diff --git a/targets/m5stack.json b/targets/m5stack.json new file mode 100644 index 00000000..af3632b4 --- /dev/null +++ b/targets/m5stack.json @@ -0,0 +1,5 @@ +{ + "inherits": ["esp32"], + "build-tags": ["m5stack"], + "serial-port": ["10c4:ea60"] +} diff --git a/targets/m5stamp-c3.json b/targets/m5stamp-c3.json new file mode 100644 index 00000000..6c50abfb --- /dev/null +++ b/targets/m5stamp-c3.json @@ -0,0 +1,7 @@ +{ + "inherits": ["esp32c3"], + "build-tags": ["m5stamp_c3"], + "serial": "uart", + "serial-port": ["1a86:55d4"] +} + diff --git a/targets/m5stick-c.json b/targets/m5stick-c.json new file mode 100644 index 00000000..5553683e --- /dev/null +++ b/targets/m5stick-c.json @@ -0,0 +1,5 @@ +{ + "inherits": ["esp32"], + "build-tags": ["m5stick_c"], + "serial-port": ["0403:6001"] +} diff --git a/targets/macropad-rp2040-boot-stage2.S b/targets/macropad-rp2040-boot-stage2.S new file mode 100644 index 00000000..52c6affd --- /dev/null +++ b/targets/macropad-rp2040-boot-stage2.S @@ -0,0 +1,17 @@ +// Adafruit MacroPad RP2040 Stage 2 Bootloader + +// +// This file defines the parameters specific to the flash-chip found +// on the Adafruit MacroPad RP2040. The generic implementation is in +// rp2040-boot-stage2.S +// + +#define BOARD_PICO_FLASH_SPI_CLKDIV 4 +#define BOARD_CMD_READ 0xeb +#define BOARD_QUAD_OK 1 +#define BOARD_QUAD_ENABLE_STATUS_BYTE 2 +#define BOARD_QUAD_ENABLE_BIT_MASK 2 +#define BOARD_SPLIT_STATUS_WRITE 0 +#define BOARD_WAIT_CYCLES 4 + +#include "rp2040-boot-stage2.S" diff --git a/targets/macropad-rp2040.json b/targets/macropad-rp2040.json new file mode 100644 index 00000000..59db5b2a --- /dev/null +++ b/targets/macropad-rp2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "build-tags": ["macropad_rp2040"], + "serial-port": ["239a:8107"], + "ldflags": [ + "--defsym=__flash_size=8M" + ], + "extra-files": [ + "targets/macropad-rp2040-boot-stage2.S" + ] +} diff --git a/targets/maixbit.json b/targets/maixbit.json new file mode 100644 index 00000000..8f621616 --- /dev/null +++ b/targets/maixbit.json @@ -0,0 +1,7 @@ +{ + "inherits": ["k210"], + "build-tags": ["maixbit"], + "serial": "uart", + "linkerscript": "targets/maixbit.ld", + "flash-command": "kflash -p {port} --noansi --verbose {bin}" +} diff --git a/targets/maixbit.ld b/targets/maixbit.ld new file mode 100644 index 00000000..015a9bea --- /dev/null +++ b/targets/maixbit.ld @@ -0,0 +1,65 @@ + +MEMORY +{ + RAM (xrw) : ORIGIN = 0x80000000, LENGTH = 6M +} + +_stack_size = 2K; + +SECTIONS +{ + .text : + { + . = ALIGN(16); + KEEP(*(.init)) + . = ALIGN(16); + *(.text.handleInterruptASM) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + . = ALIGN(16); + } >RAM + + + /* Start address (in flash) of .data, used by startup code. */ + _sidata = LOADADDR(.data); + + /* Globals with initial value */ + .data : + { + . = ALIGN(16); + /* see https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register */ + PROVIDE( __global_pointer$ = . + (4K / 2) ); + _sdata = .; /* used by startup code */ + *(.sdata) + *(.data .data.*) + . = ALIGN(16); + _edata = .; /* used by startup code */ + } >RAM + + /* Zero-initialized globals */ + .bss : + { + . = ALIGN(16); + _sbss = .; /* used by startup code */ + *(.sbss) + *(.bss .bss.*) + *(COMMON) + . = ALIGN(16); + _ebss = .; /* used by startup code */ + } >RAM + + /DISCARD/ : + { + *(.eh_frame) /* causes 'no memory region specified' error in lld */ + } +} + +PROVIDE(_stack_top = ORIGIN(RAM) + LENGTH(RAM)); + +/* For the memory allocator. */ +_heap_start = _ebss; +_heap_end = ORIGIN(RAM) + LENGTH(RAM) - _stack_size; +_globals_start = _sdata; +_globals_end = _ebss; diff --git a/targets/makerfabs-esp32c3spi35.json b/targets/makerfabs-esp32c3spi35.json new file mode 100644 index 00000000..850f8c3e --- /dev/null +++ b/targets/makerfabs-esp32c3spi35.json @@ -0,0 +1,4 @@ +{ + "inherits": ["esp32c3"], + "build-tags": ["makerfabs_esp32c3spi35"] +} diff --git a/targets/matrixportal-m4.json b/targets/matrixportal-m4.json new file mode 100644 index 00000000..c1f27a4a --- /dev/null +++ b/targets/matrixportal-m4.json @@ -0,0 +1,13 @@ +{ + "inherits": ["atsamd51j19a"], + "build-tags": ["matrixportal_m4", "ninafw"], + "serial": "usb", + "serial-port": ["239a:80c9", "239a:80ca"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["MATRIXBOOT"], + "msd-firmware-name": "firmware.uf2", + "openocd-transport": "swd", + "openocd-interface": "jlink", + "openocd-target": "atsame5x" +} diff --git a/targets/mch2022.json b/targets/mch2022.json new file mode 100644 index 00000000..5ac58aac --- /dev/null +++ b/targets/mch2022.json @@ -0,0 +1,4 @@ +{ + "inherits": ["esp32"], + "build-tags": ["mch2022"] +} diff --git a/targets/mdbt50qrx-uf2.json b/targets/mdbt50qrx-uf2.json new file mode 100644 index 00000000..17a29b33 --- /dev/null +++ b/targets/mdbt50qrx-uf2.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["mdbt50qrx"], + "serial-port": ["239a:810b", "239a:810c"], + "msd-volume-name": ["MDBT50QBOOT"] +} diff --git a/targets/metro-m4-airlift.json b/targets/metro-m4-airlift.json new file mode 100644 index 00000000..38658427 --- /dev/null +++ b/targets/metro-m4-airlift.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd51j19a"], + "build-tags": ["metro_m4_airlift", "ninafw"], + "serial": "usb", + "serial-port": ["239A:8037"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["METROM4BOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/microbit-s110v8.json b/targets/microbit-s110v8.json new file mode 100644 index 00000000..c5d34c5c --- /dev/null +++ b/targets/microbit-s110v8.json @@ -0,0 +1,4 @@ +{ + "inherits": ["microbit", "nrf51-s110v8"], + "flash-method": "openocd" +} diff --git a/targets/microbit-v2-s113v7.json b/targets/microbit-v2-s113v7.json new file mode 100644 index 00000000..76d701de --- /dev/null +++ b/targets/microbit-v2-s113v7.json @@ -0,0 +1,4 @@ +{ + "inherits": ["microbit-v2", "nrf52833-s113v7"], + "flash-method": "openocd" +} diff --git a/targets/microbit-v2-s140v7.json b/targets/microbit-v2-s140v7.json new file mode 100644 index 00000000..500bacba --- /dev/null +++ b/targets/microbit-v2-s140v7.json @@ -0,0 +1,4 @@ +{ + "inherits": ["microbit-v2", "nrf52833-s140v7"], + "flash-method": "openocd" +} diff --git a/targets/microbit-v2.json b/targets/microbit-v2.json new file mode 100644 index 00000000..6cb78b90 --- /dev/null +++ b/targets/microbit-v2.json @@ -0,0 +1,9 @@ +{ + "inherits": ["nrf52833"], + "build-tags": ["microbit_v2"], + "serial": "uart", + "flash-method": "msd", + "openocd-interface": "cmsis-dap", + "msd-volume-name": ["MICROBIT"], + "msd-firmware-name": "firmware.hex" +} diff --git a/targets/microbit.json b/targets/microbit.json new file mode 100644 index 00000000..2478cf5c --- /dev/null +++ b/targets/microbit.json @@ -0,0 +1,9 @@ +{ + "inherits": ["nrf51"], + "build-tags": ["microbit"], + "serial": "uart", + "flash-method": "msd", + "openocd-interface": "cmsis-dap", + "msd-volume-name": ["MICROBIT"], + "msd-firmware-name": "firmware.hex" +} diff --git a/targets/mimxrt1062-teensy40.ld b/targets/mimxrt1062-teensy40.ld new file mode 100644 index 00000000..70a717b7 --- /dev/null +++ b/targets/mimxrt1062-teensy40.ld @@ -0,0 +1,107 @@ +MEMORY +{ + ITCM (rwx): ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512 Kib */ + DTCM (rwx): ORIGIN = 0x20000000, LENGTH = 0x00080000 /* 512 Kib */ + RAM (rwx): ORIGIN = 0x20200000, LENGTH = 0x00080000 /* 512 Kib */ + FLASH (rx): ORIGIN = 0x60000000, LENGTH = 0x001FFFF0 /* 1984 Kib */ +} + +ENTRY(Reset_Handler); + +_stack_size = 4K; + +SECTIONS +{ + .text : ALIGN(8) { + + FILL(0xFFFFFFFF); + + /* place flash config at beginning of flash device */ + KEEP(*(.flash_config)); + + /* IVT must be located at +4 Kbyte offset from base address of flash. */ + . = ORIGIN(FLASH) + 0x1000; + KEEP(*(.ivt)); + + . = ORIGIN(FLASH) + 0x1020; + KEEP(*(.boot_data)); + + . = ORIGIN(FLASH) + 0x2000; + + _svectors = ABSOLUTE(.); + KEEP(*(.isr_vector)); + . = ALIGN(8); + + *(.text.Reset_Handler); + . = ALIGN(8); + + _stext = .; + *(.text*); + *(.rodata* .constdata*); + . = ALIGN(8); + _etext = .; + + } > FLASH + + .tinygo_stacksizes : ALIGN(8) { + + *(.tinygo_stacksizes); + . = ALIGN(8); + + } > FLASH + + .text.padding (NOLOAD) : { + + . = ALIGN(32768); + + } > ITCM + + .stack (NOLOAD) : { + + . = ALIGN(8); + . += _stack_size; + _stack_top = .; + + } > DTCM + + .data : ALIGN(8) { + + FILL(0xFFFFFFFF); + + _sdata = .; + *(.data*); + . = ALIGN(8); + _edata = .; + + } > DTCM AT > FLASH + + .bss : ALIGN(8) { + + _sbss = .; + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + + } > DTCM AT > DTCM + + /DISCARD/ : { + + *(.ARM.exidx*); /* causes spurious 'undefined reference' errors */ + + } + + _sidata = LOADADDR(.data); + + _heap_start = ORIGIN(RAM); + _heap_end = ORIGIN(RAM) + LENGTH(RAM); + + _globals_start = _sdata; + _globals_end = _ebss; + + _image_size = SIZEOF(.text) + SIZEOF(.tinygo_stacksizes) + SIZEOF(.data); + + /* TODO: link .text to ITCM */ + _itcm_blocks = (0 + 0x7FFF) >> 15; + _flexram_cfg = 0xAAAAAAAA | ((1 << (_itcm_blocks * 2)) - 1); +} diff --git a/targets/mksnanov3.json b/targets/mksnanov3.json new file mode 100644 index 00000000..fc57a71d --- /dev/null +++ b/targets/mksnanov3.json @@ -0,0 +1,13 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["mksnanov3", "stm32f407", "stm32f4", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32f407.ld", + "extra-files": [ + "src/device/stm32/stm32f407.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink", + "openocd-target": "stm32f4x", + "openocd-commands": ["stm32f4x.cpu configure -event reset-init { adapter speed 1800 }"] +} diff --git a/targets/nano-33-ble-s140v6-uf2.json b/targets/nano-33-ble-s140v6-uf2.json new file mode 100644 index 00000000..9dfc9b80 --- /dev/null +++ b/targets/nano-33-ble-s140v6-uf2.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["nano_33_ble"], + "serial-port": ["239a:8063", "239a:0063"], + "msd-volume-name": ["NANO33BOOT"] +} diff --git a/targets/nano-33-ble-s140v7-uf2.json b/targets/nano-33-ble-s140v7-uf2.json new file mode 100644 index 00000000..4c95c330 --- /dev/null +++ b/targets/nano-33-ble-s140v7-uf2.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v7-uf2"], + "build-tags": ["nano_33_ble"], + "serial-port": ["239a:8063", "239a:0063"], + "msd-volume-name": ["NANO33BOOT"] +} diff --git a/targets/nano-33-ble-s140v7.json b/targets/nano-33-ble-s140v7.json new file mode 100644 index 00000000..e78c370e --- /dev/null +++ b/targets/nano-33-ble-s140v7.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nano-33-ble", "nrf52840-s140v7"], + "flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset", + "flash-1200-bps-reset": "false", + "openocd-interface": "jlink" +} diff --git a/targets/nano-33-ble.json b/targets/nano-33-ble.json new file mode 100644 index 00000000..83a4ff10 --- /dev/null +++ b/targets/nano-33-ble.json @@ -0,0 +1,9 @@ +{ + "inherits": ["nrf52840"], + "build-tags": ["nano_33_ble", "nrf52840_reset_bossa"], + "flash-command": "bossac_arduino2 -d -i -e -w -v -R --port={port} {bin}", + "serial-port": ["2341:805a", "2341:005a"], + "serial": "usb", + "flash-1200-bps-reset": "true", + "linkerscript": "targets/nano-33-ble.ld" +} diff --git a/targets/nano-33-ble.ld b/targets/nano-33-ble.ld new file mode 100644 index 00000000..cc533ea9 --- /dev/null +++ b/targets/nano-33-ble.ld @@ -0,0 +1,14 @@ + +/* + See also + https://github.com/arduino/ArduinoCore-mbed/blob/master/variants/ARDUINO_NANO33BLE/linker_script.ld +*/ +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x10000, LENGTH = 0xf0000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/nano-rp2040.json b/targets/nano-rp2040.json new file mode 100644 index 00000000..85eed28d --- /dev/null +++ b/targets/nano-rp2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2341:005e"], + "build-tags": ["nano_rp2040", "ninafw", "ninafw_machine_init"], + "ldflags": [ + "--defsym=__flash_size=16M" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/nicenano.json b/targets/nicenano.json new file mode 100644 index 00000000..f775ab6d --- /dev/null +++ b/targets/nicenano.json @@ -0,0 +1,5 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["nicenano"], + "msd-volume-name": ["NICENANO"] +} diff --git a/targets/nintendoswitch.json b/targets/nintendoswitch.json new file mode 100644 index 00000000..f83f8fcc --- /dev/null +++ b/targets/nintendoswitch.json @@ -0,0 +1,35 @@ +{ + "llvm-target": "aarch64", + "cpu": "cortex-a57", + "features": "+aes,+crc,+fp-armv8,+neon,+perfmon,+sha2,+v8a,-fmv", + "build-tags": ["nintendoswitch", "arm64"], + "scheduler": "tasks", + "goos": "linux", + "goarch": "arm64", + "linker": "ld.lld", + "rtlib": "compiler-rt", + "libc": "picolibc", + "gc": "conservative", + "relocation-model": "pic", + "default-stack-size": 2048, + "cflags": [ + "-target", "aarch64-unknown-none", + "-fPIE", + "-Werror", + "-fshort-enums", + "-fomit-frame-pointer", + "-fno-exceptions", "-fno-unwind-tables", "-fno-asynchronous-unwind-tables", + "-ffunction-sections", "-fdata-sections" + ], + "ldflags": [ + "-pie", + "-z", "notext" + ], + "linkerscript": "targets/nintendoswitch.ld", + "extra-files": [ + "targets/nintendoswitch.s", + "src/internal/task/task_stack_arm64.S", + "src/runtime/asm_arm64.S", + "src/runtime/runtime_nintendoswitch.S" + ] +} diff --git a/targets/nintendoswitch.ld b/targets/nintendoswitch.ld new file mode 100644 index 00000000..b8e9f5d9 --- /dev/null +++ b/targets/nintendoswitch.ld @@ -0,0 +1,85 @@ +PHDRS +{ + text PT_LOAD FLAGS(5) /* Read | Execute */; + rodata PT_LOAD FLAGS(4) /* Read */; + data PT_LOAD FLAGS(6) /* Read | Write */; + bss PT_LOAD FLAGS(6) /* Read | Write */; + dynamic PT_DYNAMIC; +} + +SECTIONS +{ + /* Code and file header */ + . = 0; + + .text : ALIGN(0x1000) { + HIDDEN(__text_start = .); + KEEP(*(.text.jmp)) + + . = 0x80; + KEEP(*(.text.start)) + + *(.text .text.*) + *(.plt .plt.*) + + HIDDEN(__text_end = .); + HIDDEN(__text_size = . - __text_start); + } + + /* Read-only sections */ + . = ALIGN(0x1000); + + HIDDEN(__rodata_start = .); + .rodata : { *(.rodata .rodata.*) } :rodata + + .mod0 : { + KEEP(crt0.nso.o(.data.mod0)) + KEEP(crt0.nro.o(.data.mod0)) + KEEP(crt0.lib.nro.o(.data.mod0)) + } + + .dynsym : { *(.dynsym) } :rodata + .dynstr : { *(.dynstr) } :rodata + .rela.dyn : { *(.rela.*) } :rodata + + HIDDEN(__rodata_end = .); + HIDDEN(__rodata_size = . - __rodata_start); + + /* Read-write sections */ + . = ALIGN(0x1000); + + .data : { + HIDDEN(__data_start = .); + + *(.data .data.*) + *(.got .got.*) + *(.got.plt .got.plt.*) + + HIDDEN(__data_end = .); + HIDDEN(__data_size = . - __data_start); + } :data + + .dynamic : { + HIDDEN(__dynamic_start = .); + *(.dynamic) + } + + /* BSS section */ + . = ALIGN(0x1000); + .bss : { + HIDDEN(__bss_start = .); + + *(.bss .bss.*) + *(COMMON) + . = ALIGN(8); + + HIDDEN(__bss_end = .); + HIDDEN(__bss_size = . - __bss_start); + } : bss + + /DISCARD/ : + { + *(.eh_frame) /* This is probably unnecessary and bloats the binary. */ + *(.eh_frame_hdr) + } +} diff --git a/targets/nintendoswitch.s b/targets/nintendoswitch.s new file mode 100644 index 00000000..48edc857 --- /dev/null +++ b/targets/nintendoswitch.s @@ -0,0 +1,126 @@ +// For more information on the .nro file format, see: +// https://switchbrew.org/wiki/NRO + +.section .text.jmp, "x" +.global _start +_start: + b start + .word _mod_header - _start + .ascii "HOMEBREW" + + .ascii "NRO0" // magic + .word 0 // version (always 0) + .word __bss_start - _start // total NRO file size + .word 0 // flags (unused) + + // segment headers + .word __text_start - _start + .word __text_size + .word __rodata_start - _start + .word __rodata_size + .word __data_start - _start + .word __data_size + .word __bss_size + .word 0 + + // ModuleId (not supported) + . = 0x50; // skip 32 bytes + + .word 0 // DSO Module Offset (unused) + .word 0 // reserved (unused) + +.section .data.mod0 + .word 0, 8 + +.global _mod_header +_mod_header: + .ascii "MOD0" + .word __dynamic_start - _mod_header + .word __bss_start - _mod_header + .word __bss_end - _mod_header + .word 0, 0 // eh_frame_hdr start/end + .word 0 // runtime-generated module object offset + +.section .text.start, "x" +.global start +start: + // save lr + mov x7, x30 + + // get aslr base + bl +4 + sub x6, x30, #0x88 + + // context ptr and main thread handle + mov x25, x0 + mov x26, x1 + + // Save ASLR Base to use later + mov x0, x6 + + adrp x4, _saved_return_address + str x7, [x4, #:lo12:_saved_return_address] + + adrp x4, _context + str x25, [x4, #:lo12:_context] + + adrp x4, _main_thread + str x26, [x4, #:lo12:_main_thread] + + // store stack pointer + mov x26, sp + adrp x4, _stack_top + str x26, [x4, #:lo12:_stack_top] + + // clear .bss + adrp x5, __bss_start + add x5, x5, #:lo12:__bss_start + adrp x6, __bss_end + add x6, x6, #:lo12:__bss_end + +bssloop: + cmp x5, x6 + b.eq run + str xzr, [x5] + add x5, x5, 8 + b bssloop + +run: + // process .dynamic section + // ASLR base on x0 + adrp x1, _DYNAMIC + add x1, x1, #:lo12:_DYNAMIC + bl __dynamic_loader + + // call entrypoint + b main + +.global __nx_exit +.type __nx_exit, %function +__nx_exit: + // Exit code in x0 + + // restore stack pointer + mov sp, x1 + + // jump back to loader + br x2 + +.section .data.horizon +.align 8 +.global _saved_return_address // Saved return address. + // This might be different than null when coming from launcher +_saved_return_address: + .dword 0 +.global _context // Homebrew Launcher Context + // This might be different than null when not coming from launcher +_context: + .dword 0 + +.global _main_thread +_main_thread: + .dword 0 + +.global _stack_top +_stack_top: + .dword 0 diff --git a/targets/nodemcu.json b/targets/nodemcu.json new file mode 100644 index 00000000..c8c6c403 --- /dev/null +++ b/targets/nodemcu.json @@ -0,0 +1,5 @@ +{ + "inherits": ["esp8266"], + "build-tags": ["nodemcu"], + "serial": "uart" +} diff --git a/targets/nrf51-s110v8.json b/targets/nrf51-s110v8.json new file mode 100644 index 00000000..5f3ad3ff --- /dev/null +++ b/targets/nrf51-s110v8.json @@ -0,0 +1,4 @@ +{ + "build-tags": ["softdevice", "s110v8"], + "linkerscript": "targets/nrf51-s110v8.ld" +} diff --git a/targets/nrf51-s110v8.ld b/targets/nrf51-s110v8.ld new file mode 100644 index 00000000..44b40828 --- /dev/null +++ b/targets/nrf51-s110v8.ld @@ -0,0 +1,12 @@ + +MEMORY +{ + /* This SoftDevice requires 96K flash and 8K RAM according to the release + * notes of version 8.0.0 */ + FLASH_TEXT (rw) : ORIGIN = 0x00000000 + 96K, LENGTH = 256K - 96K + RAM (xrw) : ORIGIN = 0x20000000 + 8K, LENGTH = 16K - 8K +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf51.json b/targets/nrf51.json new file mode 100644 index 00000000..714e2c55 --- /dev/null +++ b/targets/nrf51.json @@ -0,0 +1,16 @@ +{ + "inherits": ["cortex-m0"], + "build-tags": ["nrf51822", "nrf51", "nrf"], + "cflags": [ + "-DNRF51", + "-I{root}/lib/CMSIS/CMSIS/Include", + "-I{root}/lib/nrfx/mdk" + ], + "linkerscript": "targets/nrf51.ld", + "extra-files": [ + "lib/nrfx/mdk/system_nrf51.c", + "src/device/nrf/nrf51.s" + ], + "openocd-transport": "swd", + "openocd-target": "nrf51" +} diff --git a/targets/nrf51.ld b/targets/nrf51.ld new file mode 100644 index 00000000..442ae1b0 --- /dev/null +++ b/targets/nrf51.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000, LENGTH = 256K /* .text */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52-s132v6.json b/targets/nrf52-s132v6.json new file mode 100644 index 00000000..3d11e226 --- /dev/null +++ b/targets/nrf52-s132v6.json @@ -0,0 +1,4 @@ +{ + "build-tags": ["softdevice", "s132v6"], + "linkerscript": "targets/nrf52-s132v6.ld" +} diff --git a/targets/nrf52-s132v6.ld b/targets/nrf52-s132v6.ld new file mode 100644 index 00000000..82175d2a --- /dev/null +++ b/targets/nrf52-s132v6.ld @@ -0,0 +1,13 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000 + 0x00026000 , LENGTH = 512K - 0x00026000 /* .text */ + RAM (xrw) : ORIGIN = 0x20000000 + 0x000039c0, LENGTH = 64K - 0x000039c0 +} + +_stack_size = 4K; + +/* This value is needed by the Nordic SoftDevice. */ +__app_ram_base = ORIGIN(RAM); + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52.json b/targets/nrf52.json new file mode 100644 index 00000000..3248ef73 --- /dev/null +++ b/targets/nrf52.json @@ -0,0 +1,16 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["nrf52", "nrf"], + "cflags": [ + "-DNRF52832_XXAA", + "-I{root}/lib/CMSIS/CMSIS/Include", + "-I{root}/lib/nrfx/mdk" + ], + "linkerscript": "targets/nrf52.ld", + "extra-files": [ + "lib/nrfx/mdk/system_nrf52.c", + "src/device/nrf/nrf52.s" + ], + "openocd-transport": "swd", + "openocd-target": "nrf51" +} diff --git a/targets/nrf52.ld b/targets/nrf52.ld new file mode 100644 index 00000000..6d573993 --- /dev/null +++ b/targets/nrf52.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000, LENGTH = 512K /* .text */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52833-s113v7.json b/targets/nrf52833-s113v7.json new file mode 100644 index 00000000..3e79e83e --- /dev/null +++ b/targets/nrf52833-s113v7.json @@ -0,0 +1,7 @@ +{ + "build-tags": ["softdevice", "s113v7"], + "linkerscript": "targets/nrf52833-s113v7.ld", + "ldflags": [ + "--defsym=__softdevice_stack=0x700" + ] +} diff --git a/targets/nrf52833-s113v7.ld b/targets/nrf52833-s113v7.ld new file mode 100644 index 00000000..c6913792 --- /dev/null +++ b/targets/nrf52833-s113v7.ld @@ -0,0 +1,14 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000 + 0x1C000, LENGTH = 0x80000 - 0x1C000 + RAM (xrw) : ORIGIN = 0x20000000 + 0x1e20, LENGTH = 0x20000 - 0x1e20 +} + +_stack_size = 4K + __softdevice_stack; + +/* These values are needed for the Nordic SoftDevice. */ +__app_ram_base = ORIGIN(RAM); +__softdevice_stack = DEFINED(__softdevice_stack) ? __softdevice_stack : 0; + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52833-s140v7.json b/targets/nrf52833-s140v7.json new file mode 100644 index 00000000..6c6323d4 --- /dev/null +++ b/targets/nrf52833-s140v7.json @@ -0,0 +1,7 @@ +{ + "build-tags": ["softdevice", "s140v7"], + "linkerscript": "targets/nrf52833-s140v7.ld", + "ldflags": [ + "--defsym=__softdevice_stack=0x700" + ] +} diff --git a/targets/nrf52833-s140v7.ld b/targets/nrf52833-s140v7.ld new file mode 100644 index 00000000..d47f5ecd --- /dev/null +++ b/targets/nrf52833-s140v7.ld @@ -0,0 +1,14 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000 + 0x00027000, LENGTH = 0x80000 - 0x00027000 + RAM (xrw) : ORIGIN = 0x20000000 + 0x000039c0, LENGTH = 0x20000 - 0x000039c0 +} + +_stack_size = 4K + __softdevice_stack; + +/* These values are needed for the Nordic SoftDevice. */ +__app_ram_base = ORIGIN(RAM); +__softdevice_stack = DEFINED(__softdevice_stack) ? __softdevice_stack : 0; + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52833.json b/targets/nrf52833.json new file mode 100644 index 00000000..54304dbc --- /dev/null +++ b/targets/nrf52833.json @@ -0,0 +1,16 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["nrf52833", "nrf"], + "cflags": [ + "-DNRF52833_XXAA", + "-I{root}/lib/CMSIS/CMSIS/Include", + "-I{root}/lib/nrfx/mdk" + ], + "linkerscript": "targets/nrf52833.ld", + "extra-files": [ + "lib/nrfx/mdk/system_nrf52833.c", + "src/device/nrf/nrf52833.s" + ], + "openocd-transport": "swd", + "openocd-target": "nrf52" +} diff --git a/targets/nrf52833.ld b/targets/nrf52833.ld new file mode 100644 index 00000000..99cfc119 --- /dev/null +++ b/targets/nrf52833.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000, LENGTH = 0x80000 + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x20000 +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52840-mdk-usb-dongle.json b/targets/nrf52840-mdk-usb-dongle.json new file mode 100644 index 00000000..5f34a243 --- /dev/null +++ b/targets/nrf52840-mdk-usb-dongle.json @@ -0,0 +1,5 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["nrf52840_mdk_usb_dongle"], + "msd-volume-name": ["MDK-DONGLE"] +} diff --git a/targets/nrf52840-mdk.json b/targets/nrf52840-mdk.json new file mode 100644 index 00000000..03528e50 --- /dev/null +++ b/targets/nrf52840-mdk.json @@ -0,0 +1,7 @@ +{ + "inherits": ["nrf52840"], + "build-tags": ["nrf52840_mdk"], + "serial": "usb", + "flash-method": "openocd", + "openocd-interface": "cmsis-dap" +} diff --git a/targets/nrf52840-s140v6-uf2-generic.json b/targets/nrf52840-s140v6-uf2-generic.json new file mode 100644 index 00000000..034f5933 --- /dev/null +++ b/targets/nrf52840-s140v6-uf2-generic.json @@ -0,0 +1,5 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["nrf52840_generic"], + "serial-port": ["1209:9090"] +} diff --git a/targets/nrf52840-s140v6-uf2.json b/targets/nrf52840-s140v6-uf2.json new file mode 100644 index 00000000..111c40c4 --- /dev/null +++ b/targets/nrf52840-s140v6-uf2.json @@ -0,0 +1,10 @@ +{ + "build-tags": ["nrf52840_reset_uf2", "softdevice", "s140v6"], + "linkerscript": "targets/nrf52840-s140v6-uf2.ld", + "serial": "usb", + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-firmware-name": "firmware.uf2", + "binary-format": "uf2", + "uf2-family-id": "0xADA52840" +} diff --git a/targets/nrf52840-s140v6-uf2.ld b/targets/nrf52840-s140v6-uf2.ld new file mode 100644 index 00000000..42ac1c4f --- /dev/null +++ b/targets/nrf52840-s140v6-uf2.ld @@ -0,0 +1,13 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000+0x26000, LENGTH = 0xED000-0x26000 /* SoftDevice S140. See https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/hathach-memory-map. Application starts at 0x26000; user data starts at 0xED000 */ + RAM (xrw) : ORIGIN = 0x20004180, LENGTH = 0x20040000-0x20004180 +} + +_stack_size = 2K; + +/* This value is needed by the Nordic SoftDevice. */ +__app_ram_base = ORIGIN(RAM); + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52840-s140v7-uf2.json b/targets/nrf52840-s140v7-uf2.json new file mode 100644 index 00000000..206e446e --- /dev/null +++ b/targets/nrf52840-s140v7-uf2.json @@ -0,0 +1,11 @@ +{ + "inherits": ["nrf52840-s140v7"], + "build-tags": ["nrf52840_reset_uf2"], + "linkerscript": "targets/nrf52840-s140v7-uf2.ld", + "serial": "usb", + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-firmware-name": "firmware.uf2", + "binary-format": "uf2", + "uf2-family-id": "0xADA52840" +} diff --git a/targets/nrf52840-s140v7-uf2.ld b/targets/nrf52840-s140v7-uf2.ld new file mode 100644 index 00000000..4fee8518 --- /dev/null +++ b/targets/nrf52840-s140v7-uf2.ld @@ -0,0 +1,17 @@ +/* + See also + https://github.com/Seeed-Studio/ArduinoCore-mbed/blob/master/variants/SEEED_XIAO_NRF52840_SENSE/linker_script.ld +*/ +MEMORY +{ + FLASH_TEXT (rx) : ORIGIN = 0x27000, LENGTH = 0xED000 - 0x27000 + RAM (rwx) : ORIGIN = 0x20006000, LENGTH = 0x3A000 +} + +_stack_size = 4K + __softdevice_stack; + +/* This value is needed by the Nordic SoftDevice. */ +__app_ram_base = ORIGIN(RAM); +__softdevice_stack = DEFINED(__softdevice_stack) ? __softdevice_stack : 0; + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52840-s140v7.json b/targets/nrf52840-s140v7.json new file mode 100644 index 00000000..cc9c62cd --- /dev/null +++ b/targets/nrf52840-s140v7.json @@ -0,0 +1,7 @@ +{ + "build-tags": ["softdevice", "s140v7"], + "linkerscript": "targets/nrf52840-s140v7.ld", + "ldflags": [ + "--defsym=__softdevice_stack=0x700" + ] +} diff --git a/targets/nrf52840-s140v7.ld b/targets/nrf52840-s140v7.ld new file mode 100644 index 00000000..b1291540 --- /dev/null +++ b/targets/nrf52840-s140v7.ld @@ -0,0 +1,14 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000 + 0x00027000, LENGTH = 1M - 0x00027000 + RAM (xrw) : ORIGIN = 0x20000000 + 0x000039c0, LENGTH = 256K - 0x000039c0 +} + +_stack_size = 4K + __softdevice_stack; + +/* This value is needed by the Nordic SoftDevice. */ +__app_ram_base = ORIGIN(RAM); +__softdevice_stack = DEFINED(__softdevice_stack) ? __softdevice_stack : 0; + +INCLUDE "targets/arm.ld" diff --git a/targets/nrf52840.json b/targets/nrf52840.json new file mode 100644 index 00000000..9d86a650 --- /dev/null +++ b/targets/nrf52840.json @@ -0,0 +1,16 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["nrf52840", "nrf"], + "cflags": [ + "-DNRF52840_XXAA", + "-I{root}/lib/CMSIS/CMSIS/Include", + "-I{root}/lib/nrfx/mdk" + ], + "linkerscript": "targets/nrf52840.ld", + "extra-files": [ + "lib/nrfx/mdk/system_nrf52840.c", + "src/device/nrf/nrf52840.s" + ], + "openocd-transport": "swd", + "openocd-target": "nrf51" +} diff --git a/targets/nrf52840.ld b/targets/nrf52840.ld new file mode 100644 index 00000000..3f766a91 --- /dev/null +++ b/targets/nrf52840.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00000000, LENGTH = 1M + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/nucleo-f103rb.json b/targets/nucleo-f103rb.json new file mode 100644 index 00000000..723c5eef --- /dev/null +++ b/targets/nucleo-f103rb.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m3"], + "build-tags": ["nucleof103rb", "stm32f103", "stm32f1","stm32"], + "serial": "uart", + "linkerscript": "targets/stm32f103rb.ld", + "extra-files": [ + "src/device/stm32/stm32f103.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink-v2-1", + "openocd-target": "stm32f1x" +} diff --git a/targets/nucleo-f722ze.json b/targets/nucleo-f722ze.json new file mode 100644 index 00000000..f426b332 --- /dev/null +++ b/targets/nucleo-f722ze.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m7"], + "build-tags": ["nucleof722ze", "stm32f7x2", "stm32f7", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32f7x2zetx.ld", + "extra-files": [ + "src/device/stm32/stm32f7x2.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink-v2-1", + "openocd-target": "stm32f7x" +} diff --git a/targets/nucleo-l031k6.json b/targets/nucleo-l031k6.json new file mode 100644 index 00000000..eed8f38f --- /dev/null +++ b/targets/nucleo-l031k6.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m0"], + "build-tags": ["nucleol031k6", "stm32l031", "stm32l0x1", "stm32l0", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32l031k6.ld", + "extra-files": [ + "src/device/stm32/stm32l0x1.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink", + "openocd-target": "stm32l0" +} \ No newline at end of file diff --git a/targets/nucleo-l432kc.json b/targets/nucleo-l432kc.json new file mode 100644 index 00000000..028b034b --- /dev/null +++ b/targets/nucleo-l432kc.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["nucleol432kc", "stm32l432", "stm32l4x2", "stm32l4", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32l4x2.ld", + "extra-files": [ + "src/device/stm32/stm32l4x2.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink-v2-1", + "openocd-target": "stm32l4x" + } \ No newline at end of file diff --git a/targets/nucleo-l476rg.json b/targets/nucleo-l476rg.json new file mode 100644 index 00000000..73eddee8 --- /dev/null +++ b/targets/nucleo-l476rg.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["nucleol476rg", "stm32l476", "stm32l4x6", "stm32l4", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32l4x6.ld", + "extra-files": [ + "src/device/stm32/stm32l4x6.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink-v2-1", + "openocd-target": "stm32l4x" + } diff --git a/targets/nucleo-l552ze.json b/targets/nucleo-l552ze.json new file mode 100644 index 00000000..9ee43680 --- /dev/null +++ b/targets/nucleo-l552ze.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m33"], + "build-tags": ["nucleol552ze", "stm32l552", "stm32l5x2", "stm32l5", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32l5x2xe.ld", + "extra-files": [ + "src/device/stm32/stm32l552.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink", + "openocd-target": "stm32l5x" + } \ No newline at end of file diff --git a/targets/nucleo-wl55jc.json b/targets/nucleo-wl55jc.json new file mode 100644 index 00000000..3e4f8ca1 --- /dev/null +++ b/targets/nucleo-wl55jc.json @@ -0,0 +1,12 @@ +{ + "inherits": [ + "stm32wl5x_cm4" + ], + "build-tags": [ + "nucleowl55jc" + ], + "serial": "uart", + "flash-method": "openocd", + "openocd-interface": "stlink", + "openocd-target": "stm32wlx" +} diff --git a/targets/nxpmk66f18.ld b/targets/nxpmk66f18.ld new file mode 100644 index 00000000..acbe5a16 --- /dev/null +++ b/targets/nxpmk66f18.ld @@ -0,0 +1,38 @@ + +/* Unused, but here to silence a linker warning. */ +ENTRY(Reset_Handler) + +/* define memory layout */ +MEMORY +{ + FLASH_TEXT (rx) : ORIGIN = 0x00000000, LENGTH = 1024K + RAM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 256K +} + +_stack_size = 2K; + +/* define output sections */ +SECTIONS +{ + /* Program code and read-only data goes to FLASH_TEXT. */ + .text : + { + /* vector table MUST start at 0x0 */ + . = 0; + KEEP(*(.isr_vector)) + + /* flash configuration MUST be at 0x400 */ + . = 0x400; + KEEP(*(.flash_config)) + + /* everything else */ + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + + } >FLASH_TEXT = 0xFF +} + +INCLUDE "targets/arm.ld" diff --git a/targets/p1am-100.json b/targets/p1am-100.json new file mode 100644 index 00000000..f22f740a --- /dev/null +++ b/targets/p1am-100.json @@ -0,0 +1,6 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["p1am_100"], + "flash-command": "bossac -d -i -e -w -v -R --port={port} --offset=0x2000 {bin}", + "flash-1200-bps-reset": "true" +} diff --git a/targets/particle-3rd-gen.json b/targets/particle-3rd-gen.json new file mode 100644 index 00000000..ef39a734 --- /dev/null +++ b/targets/particle-3rd-gen.json @@ -0,0 +1,7 @@ +{ + "inherits": ["nrf52840"], + "build-tags": ["particle_3rd_gen"], + "serial": "uart", + "flash-method": "openocd", + "openocd-interface": "cmsis-dap" +} diff --git a/targets/particle-argon.json b/targets/particle-argon.json new file mode 100644 index 00000000..a23233bb --- /dev/null +++ b/targets/particle-argon.json @@ -0,0 +1,4 @@ +{ + "inherits": ["particle-3rd-gen"], + "build-tags": ["particle_argon"] +} diff --git a/targets/particle-boron.json b/targets/particle-boron.json new file mode 100644 index 00000000..2b737393 --- /dev/null +++ b/targets/particle-boron.json @@ -0,0 +1,4 @@ +{ + "inherits": ["particle-3rd-gen"], + "build-tags": ["particle_boron"] +} diff --git a/targets/particle-xenon.json b/targets/particle-xenon.json new file mode 100644 index 00000000..d93425d7 --- /dev/null +++ b/targets/particle-xenon.json @@ -0,0 +1,4 @@ +{ + "inherits": ["particle-3rd-gen"], + "build-tags": ["particle_xenon"] +} diff --git a/targets/pca10031.json b/targets/pca10031.json new file mode 100644 index 00000000..8af365cc --- /dev/null +++ b/targets/pca10031.json @@ -0,0 +1,7 @@ +{ + "inherits": ["nrf51"], + "build-tags": ["pca10031"], + "serial": "uart", + "flash-command": "nrfjprog -f nrf51 --sectorerase --program {hex} --reset", + "openocd-interface": "cmsis-dap" +} diff --git a/targets/pca10040-s132v6.json b/targets/pca10040-s132v6.json new file mode 100644 index 00000000..3b03bb1b --- /dev/null +++ b/targets/pca10040-s132v6.json @@ -0,0 +1,3 @@ +{ + "inherits": ["pca10040", "nrf52-s132v6"] +} diff --git a/targets/pca10040.json b/targets/pca10040.json new file mode 100644 index 00000000..b751b3bd --- /dev/null +++ b/targets/pca10040.json @@ -0,0 +1,9 @@ +{ + "inherits": ["nrf52"], + "build-tags": ["pca10040"], + "serial": "uart", + "flash-method": "openocd", + "flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset", + "openocd-interface": "jlink", + "openocd-transport": "swd" +} diff --git a/targets/pca10056-s140v6-uf2.json b/targets/pca10056-s140v6-uf2.json new file mode 100644 index 00000000..341a6204 --- /dev/null +++ b/targets/pca10056-s140v6-uf2.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["pca10056"], + "serial-port": ["239a:0x0029"], + "msd-volume-name": ["NRF52BOOT"] +} diff --git a/targets/pca10056-s140v7.json b/targets/pca10056-s140v7.json new file mode 100644 index 00000000..7419ae94 --- /dev/null +++ b/targets/pca10056-s140v7.json @@ -0,0 +1,3 @@ +{ + "inherits": ["pca10056", "nrf52840-s140v7"] +} diff --git a/targets/pca10056.json b/targets/pca10056.json new file mode 100644 index 00000000..de660b44 --- /dev/null +++ b/targets/pca10056.json @@ -0,0 +1,11 @@ +{ + "inherits": ["nrf52840"], + "build-tags": ["pca10056"], + "serial": "uart", + "flash-method": "command", + "flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset", + "msd-volume-name": ["JLINK"], + "msd-firmware-name": "firmware.hex", + "openocd-interface": "jlink", + "openocd-transport": "swd" +} diff --git a/targets/pca10059-s140v7.json b/targets/pca10059-s140v7.json new file mode 100644 index 00000000..ca302c37 --- /dev/null +++ b/targets/pca10059-s140v7.json @@ -0,0 +1,3 @@ +{ + "inherits": ["pca10059", "nrf52840-s140v7"] +} diff --git a/targets/pca10059.json b/targets/pca10059.json new file mode 100644 index 00000000..b5286e98 --- /dev/null +++ b/targets/pca10059.json @@ -0,0 +1,8 @@ +{ + "inherits": ["nrf52840"], + "build-tags": ["pca10059"], + "serial": "usb", + "linkerscript": "targets/pca10059.ld", + "binary-format": "nrf-dfu", + "flash-command": "nrfutil dfu usb-serial -pkg {zip} -p {port} -b 115200" +} diff --git a/targets/pca10059.ld b/targets/pca10059.ld new file mode 100644 index 00000000..18eb10de --- /dev/null +++ b/targets/pca10059.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x00001000, LENGTH = 0xDF000 + RAM (xrw) : ORIGIN = 0x20000008, LENGTH = 0x3FFF8 +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" diff --git a/targets/pga2350.json b/targets/pga2350.json new file mode 100644 index 00000000..5afe89ec --- /dev/null +++ b/targets/pga2350.json @@ -0,0 +1,7 @@ +{ + "inherits": ["rp2350b"], + "build-tags": ["pga2350"], + "ldflags": [ + "--defsym=__flash_size=16M" + ] +} \ No newline at end of file diff --git a/targets/pico-boot-stage2.S b/targets/pico-boot-stage2.S new file mode 100644 index 00000000..88dd5517 --- /dev/null +++ b/targets/pico-boot-stage2.S @@ -0,0 +1,17 @@ +// Raspberry Pi Pico Stage 2 Bootloader + +// +// This file defines the parameters specific to the flash-chip found +// on the official Pico boards. The generic implementation is in +// rp2040-boot-stage2.S +// + +#define BOARD_PICO_FLASH_SPI_CLKDIV 2 +#define BOARD_CMD_READ 0xeb +#define BOARD_QUAD_OK 1 +#define BOARD_QUAD_ENABLE_STATUS_BYTE 2 +#define BOARD_QUAD_ENABLE_BIT_MASK 2 +#define BOARD_SPLIT_STATUS_WRITE 0 +#define BOARD_WAIT_CYCLES 4 + +#include "rp2040-boot-stage2.S" \ No newline at end of file diff --git a/targets/pico-plus2.json b/targets/pico-plus2.json new file mode 100644 index 00000000..307c1b72 --- /dev/null +++ b/targets/pico-plus2.json @@ -0,0 +1,11 @@ +{ + "inherits": [ + "rp2350b" + ], + "build-tags": ["pico_plus2"], + "ldflags": [ + "--defsym=__flash_size=16M" + ], + "serial-port": ["2e8a:000F"], + "default-stack-size": 8192 +} diff --git a/targets/pico-w.json b/targets/pico-w.json new file mode 100644 index 00000000..0eff1afc --- /dev/null +++ b/targets/pico-w.json @@ -0,0 +1,4 @@ +{ + "inherits": ["pico"], + "build-tags": ["pico-w", "cyw43439"] +} diff --git a/targets/pico.json b/targets/pico.json new file mode 100644 index 00000000..cfc20565 --- /dev/null +++ b/targets/pico.json @@ -0,0 +1,14 @@ +{ + "inherits": [ + "rp2040" + ], + "build-tags": ["pico"], + "serial-port": ["2e8a:000A"], + "default-stack-size": 8192, + "ldflags": [ + "--defsym=__flash_size=2048K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/pico2-w.json b/targets/pico2-w.json new file mode 100644 index 00000000..0f134964 --- /dev/null +++ b/targets/pico2-w.json @@ -0,0 +1,4 @@ +{ + "inherits": ["pico2"], + "build-tags": ["pico2-w", "cyw43439"] +} diff --git a/targets/pico2.json b/targets/pico2.json new file mode 100644 index 00000000..af156d54 --- /dev/null +++ b/targets/pico2.json @@ -0,0 +1,11 @@ +{ + "inherits": [ + "rp2350" + ], + "build-tags": ["pico2"], + "serial-port": ["2e8a:000A"], + "default-stack-size": 8192, + "ldflags": [ + "--defsym=__flash_size=4M" + ] +} diff --git a/targets/pinetime.json b/targets/pinetime.json new file mode 100644 index 00000000..1ba8a0e7 --- /dev/null +++ b/targets/pinetime.json @@ -0,0 +1,9 @@ +{ + "inherits": ["nrf52"], + "build-tags": ["pinetime"], + "serial": "none", + "flash-method": "openocd", + "flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset", + "openocd-interface": "jlink", + "openocd-transport": "swd" +} diff --git a/targets/pybadge.json b/targets/pybadge.json new file mode 100644 index 00000000..b41f87ad --- /dev/null +++ b/targets/pybadge.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd51j19a"], + "build-tags": ["pybadge", "ninafw"], + "serial": "usb", + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "serial-port": ["239a:8033"], + "msd-volume-name": ["PYBADGEBOOT"], + "msd-firmware-name": "arcade.uf2" +} diff --git a/targets/pygamer.json b/targets/pygamer.json new file mode 100644 index 00000000..cbd1abf9 --- /dev/null +++ b/targets/pygamer.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd51j19a"], + "build-tags": ["pygamer"], + "serial": "usb", + "serial-port": ["239a:803d", "239a:803e"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["PYGAMERBOOT"], + "msd-firmware-name": "arcade.uf2" +} diff --git a/targets/pyportal.json b/targets/pyportal.json new file mode 100644 index 00000000..dbd4ed37 --- /dev/null +++ b/targets/pyportal.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd51j20a"], + "build-tags": ["pyportal", "ninafw", "ninafw_machine_init"], + "serial": "usb", + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "serial-port": ["239a:8035", "239a:8036"], + "msd-volume-name": ["PORTALBOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/qtpy-esp32c3.json b/targets/qtpy-esp32c3.json new file mode 100644 index 00000000..b893a11b --- /dev/null +++ b/targets/qtpy-esp32c3.json @@ -0,0 +1,4 @@ +{ + "inherits": ["esp32c3"], + "build-tags": ["qtpy_esp32c3"] +} diff --git a/targets/qtpy-rp2040-boot-stage2.S b/targets/qtpy-rp2040-boot-stage2.S new file mode 100644 index 00000000..78f74412 --- /dev/null +++ b/targets/qtpy-rp2040-boot-stage2.S @@ -0,0 +1,17 @@ +// Adafruit QT Py RP2040 Stage 2 Bootloader + +// +// This file defines the parameters specific to the flash-chip found +// on the Adafruit QT Py RP2040. The generic implementation is in +// rp2040-boot-stage2.S +// + +#define BOARD_PICO_FLASH_SPI_CLKDIV 2 +#define BOARD_CMD_READ 0xe7 +#define BOARD_QUAD_OK 1 +#define BOARD_QUAD_ENABLE_STATUS_BYTE 2 +#define BOARD_QUAD_ENABLE_BIT_MASK 2 +#define BOARD_SPLIT_STATUS_WRITE 1 +#define BOARD_WAIT_CYCLES 2 + +#include "rp2040-boot-stage2.S" diff --git a/targets/qtpy-rp2040.json b/targets/qtpy-rp2040.json new file mode 100644 index 00000000..394d83aa --- /dev/null +++ b/targets/qtpy-rp2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["239a:80f7"], + "build-tags": ["qtpy_rp2040"], + "ldflags": [ + "--defsym=__flash_size=8192K" + ], + "extra-files": [ + "targets/qtpy-rp2040-boot-stage2.S" + ] +} diff --git a/targets/qtpy.json b/targets/qtpy.json new file mode 100644 index 00000000..49a67901 --- /dev/null +++ b/targets/qtpy.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd21e18a"], + "build-tags": ["qtpy"], + "serial": "usb", + "serial-port": ["239a:80cb"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["QTPY_BOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/rak4631.json b/targets/rak4631.json new file mode 100644 index 00000000..cbd82213 --- /dev/null +++ b/targets/rak4631.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v6-uf2"], + "build-tags": ["rak4631"], + "serial-port": ["239a:8029"], + "msd-volume-name": ["RAK4631"] +} diff --git a/targets/reelboard-s140v7.json b/targets/reelboard-s140v7.json new file mode 100644 index 00000000..4d1adfc0 --- /dev/null +++ b/targets/reelboard-s140v7.json @@ -0,0 +1,4 @@ +{ + "inherits": ["reelboard", "nrf52840-s140v7"], + "flash-method": "openocd" +} diff --git a/targets/reelboard.json b/targets/reelboard.json new file mode 100644 index 00000000..240eb371 --- /dev/null +++ b/targets/reelboard.json @@ -0,0 +1,9 @@ +{ + "inherits": ["nrf52840"], + "build-tags": ["reelboard"], + "serial": "uart", + "flash-method": "msd", + "msd-volume-name": ["reel-board"], + "msd-firmware-name": "firmware.hex", + "openocd-interface": "cmsis-dap" +} diff --git a/targets/riscv-qemu.json b/targets/riscv-qemu.json new file mode 100644 index 00000000..31808933 --- /dev/null +++ b/targets/riscv-qemu.json @@ -0,0 +1,21 @@ +{ + "inherits": [ + "riscv32" + ], + "features": "+32bit,+a,+c,+m,+zihintpause,+zmmul,-b,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-f,-h,-relax,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xesppie,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b", + "build-tags": [ + "virt", + "qemu" + ], + "scheduler": "cores", + "default-stack-size": 8192, + "cflags": [ + "-march=rv32imaczihintpause", + "-DTINYGO_CORES=4" + ], + "ldflags": [ + "--defsym=__num_stacks=4" + ], + "linkerscript": "targets/riscv-qemu.ld", + "emulator": "qemu-system-riscv32 -machine virt,aclint=on -smp 4 -nographic -bios none -device virtio-rng-device -kernel {}" +} diff --git a/targets/riscv-qemu.ld b/targets/riscv-qemu.ld new file mode 100644 index 00000000..822c00d1 --- /dev/null +++ b/targets/riscv-qemu.ld @@ -0,0 +1,16 @@ + +/* Memory map: + * https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c + * Looks like we can use any address starting from 0x80000000 (so 2GB of space). + * However, using a large space slows down tests. + */ +MEMORY +{ + RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 100M +} + +REGION_ALIAS("FLASH_TEXT", RAM) + +_stack_size = 2K; + +INCLUDE "targets/riscv.ld" diff --git a/targets/riscv.json b/targets/riscv.json new file mode 100644 index 00000000..920110da --- /dev/null +++ b/targets/riscv.json @@ -0,0 +1,25 @@ +{ + "goos": "linux", + "goarch": "arm", + "build-tags": ["tinygo.riscv", "baremetal", "linux", "arm"], + "gc": "conservative", + "linker": "ld.lld", + "rtlib": "compiler-rt", + "libc": "picolibc", + "cflags": [ + "-Werror", + "-mno-relax", + "-fno-exceptions", "-fno-unwind-tables", "-fno-asynchronous-unwind-tables", + "-ffunction-sections", "-fdata-sections" + ], + "ldflags": [ + "--gc-sections" + ], + "extra-files": [ + "src/device/riscv/start.S", + "src/internal/task/task_stack_tinygoriscv.S", + "src/runtime/asm_riscv.S", + "src/device/riscv/handleinterrupt.S" + ], + "gdb": ["riscv64-unknown-elf-gdb"] +} diff --git a/targets/riscv.ld b/targets/riscv.ld new file mode 100644 index 00000000..a668d1d6 --- /dev/null +++ b/targets/riscv.ld @@ -0,0 +1,85 @@ +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + *(.text.handleInterruptASM) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + } >FLASH_TEXT + + /* Put the stack at the bottom of RAM, so that the application will + * crash on stack overflow instead of silently corrupting memory. + * See: http://blog.japaric.io/stack-overflow-protection/ */ + .stack0 (NOLOAD) : + { + . = ALIGN(16); + . += _stack_size; + _stack_top = .; + } >RAM + + .stack1 (NOLOAD) : + { + . = ALIGN(16); + . += DEFINED(__num_stacks) && __num_stacks >= 2 ? _stack_size : 0; + _stack1_top = .; + } >RAM + + .stack2 (NOLOAD) : + { + . = ALIGN(16); + . += DEFINED(__num_stacks) && __num_stacks >= 3 ? _stack_size : 0; + _stack2_top = .; + } >RAM + + .stack3 (NOLOAD) : + { + . = ALIGN(16); + . += DEFINED(__num_stacks) && __num_stacks >= 4 ? _stack_size : 0; + _stack3_top = .; + } >RAM + + /* Start address (in flash) of .data, used by startup code. */ + _sidata = LOADADDR(.data); + + /* Globals with initial value */ + .data : + { + . = ALIGN(4); + /* see https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register */ + PROVIDE( __global_pointer$ = . + (4K / 2) ); + _sdata = .; /* used by startup code */ + *(.sdata) + *(.data .data.*) + . = ALIGN(4); + _edata = .; /* used by startup code */ + } >RAM AT>FLASH_TEXT + + /* Zero-initialized globals */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* used by startup code */ + *(.sbss) + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* used by startup code */ + } >RAM + + /DISCARD/ : + { + *(.eh_frame) /* causes 'no memory region specified' error in lld */ + } +} + +/* For the memory allocator. */ +_heap_start = ALIGN(_ebss, 16); +_heap_end = ORIGIN(RAM) + LENGTH(RAM); +_globals_start = _sdata; +_globals_end = _ebss; diff --git a/targets/riscv32.json b/targets/riscv32.json new file mode 100644 index 00000000..7666fb3b --- /dev/null +++ b/targets/riscv32.json @@ -0,0 +1,19 @@ +{ + "inherits": ["riscv"], + "llvm-target": "riscv32-unknown-none", + "cpu": "generic-rv32", + "target-abi": "ilp32", + "build-tags": ["tinygo.riscv32"], + "scheduler": "tasks", + "default-stack-size": 2048, + "cflags": [ + "-march=rv32imac" + ], + "ldflags": [ + "-melf32lriscv" + ], + "gdb": [ + "gdb-multiarch", + "gdb" + ] +} diff --git a/targets/riscv64.json b/targets/riscv64.json new file mode 100644 index 00000000..8f44ce53 --- /dev/null +++ b/targets/riscv64.json @@ -0,0 +1,13 @@ +{ + "inherits": ["riscv"], + "llvm-target": "riscv64-unknown-none", + "cpu": "generic-rv64", + "target-abi": "lp64", + "build-tags": ["tinygo.riscv64"], + "cflags": [ + "-march=rv64gc" + ], + "ldflags": [ + "-melf64lriscv" + ] +} diff --git a/targets/rp2040-boot-stage2.S b/targets/rp2040-boot-stage2.S new file mode 100644 index 00000000..e5135c9d --- /dev/null +++ b/targets/rp2040-boot-stage2.S @@ -0,0 +1,471 @@ +// +// Implementation of RP2040 stage 2 boot loader. This code is derived from the +// Winbond W25Q080 implementation (as found in the Pico) in the official Pico SDK. +// +// This implementation has been made 'stand-alone' by including necessary code / +// symbols from the included files in the reference implementation directly into +// the source. It has also been modified to include the conditional logic from +// the CircuitPython implementation that supports additional flash chips. The +// CircuitPython source is here: +// https://github.com/adafruit/circuitpython/blob/main/ports/raspberrypi/stage2.c.jinja +// +// This file cannot be assembled directly, instead assemble the board-specific file +// (such as pico-boot-stage2.S) which defines the parameters specific to the flash +// chip included on that board. +// +// Care has been taken to preserve ordering and it has been verified the generated +// binary is byte-for-byte identical to the reference code binary when assembled for +// the Pico. +// +// Note: the stage 2 boot loader must be 256 bytes in length and have a checksum +// present. In TinyGo, the linker script is responsible for allocating 256 bytes +// for the .boot2 section and the build logic patches the checksum into the +// binary after linking, controlled by the '.json' flag 'rp2040-boot-patch'. +// +// The stage 2 bootstrap section can be inspected in an elf file using this command: +// objdump -s -j .boot2 .elf +// +// Original Source: +// https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/boot_stage2/boot2_w25q080.S +// + + +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Winbond W25Q080 +// Also supports W25Q16JV (which has some different SR instructions) +// Also supports AT25SF081 +// Also supports S25FL132K0 +// +// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode +// +// Details: * Check status register 2 to determine if QSPI mode is enabled, +// and perform an SR2 programming cycle if necessary. +// * Use SSI to perform a dummy 0xEB read command, with the mode +// continuation bits set, so that the flash will not require +// 0xEB instruction prefix on subsequent reads. +// * Configure SSI to write address, mode bits, but no instruction. +// SSI + flash are now jointly in a state where continuous reads +// can take place. +// * Jump to exit pointer passed in via lr. Bootrom passes null, +// in which case this code uses a default 256 byte flash offset +// +// Building: * This code must be position-independent, and use stack only +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + + +// +// Expanded include files +// +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_STATUS1 0x05 +#define CMD_READ_STATUS2 0x35 +#define CMD_WRITE_STATUS1 0x01 +#define CMD_WRITE_STATUS2 0x31 +#define SREG_DATA 0x02 // Enable quad-SPI mode + +#define XIP_BASE 0x10000000 +#define XIP_SSI_BASE 0x18000000 +#define PADS_QSPI_BASE 0x40020000 +#define PPB_BASE 0xe0000000 + +#define M0PLUS_VTOR_OFFSET 0x0000ed08 + +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c +#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010 +#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014 + +#define SSI_CTRLR0_OFFSET 0x00000000 +#define SSI_CTRLR1_OFFSET 0x00000004 +#define SSI_SSIENR_OFFSET 0x00000008 +#define SSI_BAUDR_OFFSET 0x00000014 +#define SSI_SR_OFFSET 0x00000028 +#define SSI_DR0_OFFSET 0x00000060 +#define SSI_RX_SAMPLE_DLY_OFFSET 0x000000f0 + +#define SSI_CTRLR0_DFS_32_LSB 16 + +#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD 0x2 +#define SSI_CTRLR0_SPI_FRF_LSB 21 + +#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX 0x0 +#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ 0x3 +#define SSI_CTRLR0_TMOD_LSB 8 + +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A 0x1 +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A 0x2 + +#define SSI_SPI_CTRLR0_OFFSET 0x000000f4 + +#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE 0x0 +#define SSI_SPI_CTRLR0_INST_L_VALUE_8B 0x2 + +#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB 0 +#define SSI_SPI_CTRLR0_ADDR_L_LSB 2 +#define SSI_SPI_CTRLR0_INST_L_LSB 8 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB 11 +#define SSI_SPI_CTRLR0_XIP_CMD_LSB 24 + +#define SSI_SR_BUSY_BITS 0x00000001 +#define SSI_SR_TFE_BITS 0x00000004 + + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive, even integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. + +#define PICO_FLASH_SPI_CLKDIV BOARD_PICO_FLASH_SPI_CLKDIV +#if PICO_FLASH_SPI_CLKDIV & 1 +#error PICO_FLASH_SPI_CLKDIV must be even +#endif + +#if BOARD_QUAD_OK==1 +// Define interface width: single/dual/quad IO +#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD +#define TRANSACTION_TYPE SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD +#define INSTRUCTION_LENGTH SSI_SPI_CTRLR0_INST_L_VALUE_NONE +#define READ_INSTRUCTION MODE_CONTINUOUS_READ +#define ADDR_L 8 // 6 for address, 2 for mode +#else +#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_STD +#define TRANSACTION_TYPE SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A +#define INSTRUCTION_LENGTH SSI_SPI_CTRLR0_INST_L_VALUE_8B +#define READ_INSTRUCTION BOARD_CMD_READ +#define ADDR_L 6 // * 4 = 24 +#endif + +// The flash-chip specific read isntruction +#define CMD_READ BOARD_CMD_READ + +// "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Quad I/O" command sequence. +// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the +// next read does not require the 0xeb instruction prefix. +#define MODE_CONTINUOUS_READ 0xa0 + +// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles +// are required. +#define WAIT_CYCLES BOARD_WAIT_CYCLES + + +// If defined, we will read status reg, compare to SREG_DATA, and overwrite +// with our value if the SR doesn't match. +// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to +// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. +// This isn't great because it will remove block protections. +// A better solution is to use a volatile SR write if your device supports it. +#define PROGRAM_STATUS_REG + +.syntax unified +.cpu cortex-m0plus +.thumb +.section .boot2, "ax" + +// The exit point is passed in lr. If entered from bootrom, this will be the +// flash address immediately following this second stage (0x10000100). +// Otherwise it will be a return address -- second stage being called as a +// function by user code, after copying out of XIP region. r3 holds SSI base, +// r0...2 used as temporaries. Other GPRs not used. +.global _stage2_boot +.type _stage2_boot,%function +.thumb_func +_stage2_boot: + push {lr} + + // Set pad configuration: + // - SCLK 8mA drive, no slew limiting + // - SDx disable input Schmitt to reduce delay + + ldr r3, =PADS_QSPI_BASE + movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS) + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] + ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] + movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS + bics r0, r1 +#if BOARD_QUAD_OK==1 + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] +#endif + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] +#if BOARD_QUAD_OK==1 + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] +#endif + + ldr r3, =XIP_SSI_BASE + + // Disable SSI to allow further config + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Set baud rate + movs r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] + + // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means, + // if the flash launches data on SCLK posedge, we capture it at the time that + // the next SCLK posedge is launched. This is shortly before that posedge + // arrives at the flash, so data hold time should be ok. For + // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect. + + movs r1, #1 + movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance + str r1, [r3, r2] + +// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode +// (i.e. turn WPn and HOLDn into IO2/IO3) +#ifdef PROGRAM_STATUS_REG +program_sregs: +#define CTRL0_SPI_TXRX \ + (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ + (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRL0_SPI_TXRX) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + // Enable SSI and select slave 0 + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Check whether SR needs updating +#if BOARD_QUAD_OK==1 +# if BOARD_QUAD_ENABLE_STATUS_BYTE==1 + movs r0, #CMD_READ_STATUS1 +# elif BOARD_QUAD_ENABLE_STATUS_BYTE==2 + movs r0, #CMD_READ_STATUS2 +# endif + + bl read_flash_sreg + movs r2, #BOARD_QUAD_ENABLE_BIT_MASK + cmp r0, r2 + beq skip_sreg_programming + + // Send write enable command + movs r1, #CMD_WRITE_ENABLE + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Send status write command followed by data bytes +# if BOARD_SPLIT_STATUS_WRITE==1 +# if BOARD_QUAD_ENABLE_STATUS_BYTE==1 + movs r1, #CMD_WRITE_STATUS1 +# elif BOARD_QUAD_ENABLE_STATUS_BYTE==2 + movs r1, #CMD_WRITE_STATUS2 +# endif + str r1, [r3, #SSI_DR0_OFFSET] + str r2, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + //ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + +# else + movs r1, #CMD_WRITE_STATUS1 + str r1, [r3, #SSI_DR0_OFFSET] +# if BOARD_QUAD_ENABLE_STATUS_BYTE==2 + movs r0, #0 + str r0, [r3, #SSI_DR0_OFFSET] +# endif + str r2, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] +# if BOARD_QUAD_ENABLE_STATUS_BYTE==2 + ldr r1, [r3, #SSI_DR0_OFFSET] +# endif + +# endif + // Poll status register for write completion +1: + movs r0, #CMD_READ_STATUS1 + bl read_flash_sreg + movs r1, #1 + tst r0, r1 + bne 1b +#endif + +skip_sreg_programming: + + // Disable SSI again so that it can be reconfigured + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] +#endif + +// Currently the flash expects an 8 bit serial command prefix on every +// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O +// command, with mode bits set such that the flash will not expect a serial +// command prefix on *subsequent* transfers. We don't care about the results +// of the read, the important part is the mode bits. + +dummy_read: +#define CTRLR0_ENTER_XIP \ + (FRAME_FORMAT /* Quad I/O mode */ \ + << SSI_CTRLR0_SPI_FRF_LSB) | \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ + << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRLR0_ENTER_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + movs r1, #0x0 // NDF=0 (single 32b read) + str r1, [r3, #SSI_CTRLR1_OFFSET] + +#if BOARD_QUAD_OK==1 +#define SPI_CTRLR0_ENTER_XIP \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ + << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_ENTER_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register + str r1, [r0] + + movs r1, #1 // Re-enable SSI + str r1, [r3, #SSI_SSIENR_OFFSET] + + movs r1, #CMD_READ + str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO + movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 + str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction + + // Poll for completion + bl wait_ssi_ready + +// The flash is in a state where we can blast addresses in parallel, and get +// parallel data back. Now configure the SSI to translate XIP bus accesses +// into QSPI transfers of this form. + + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config +#endif + +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD +configure_ssi: +#define SPI_CTRLR0_XIP \ + (READ_INSTRUCTION /* Mode bits to keep flash in continuous read mode */ \ + << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (INSTRUCTION_LENGTH /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ + << SSI_SPI_CTRLR0_INST_L_LSB) | \ + (TRANSACTION_TYPE /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_XIP) + + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI + +// Bus accesses to the XIP window will now be transparently serviced by the +// external flash on cache miss. We are ready to run code from flash. + + +// +// Helper Includes +// + +// +// #include "boot2_helpers/exit_from_boot2.S" +// + +// If entered from the bootrom, lr (which we earlier pushed) will be 0, +// and we vector through the table at the start of the main flash image. +// Any regular function call will have a nonzero value for lr. +check_return: + pop {r0} + cmp r0, #0 + beq vector_into_flash + bx r0 +vector_into_flash: + ldr r0, =(XIP_BASE + 0x100) + ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET) + str r0, [r1] + ldmia r0, {r0, r1} + msr msp, r0 + bx r1 + +// +// #include "boot2_helpers/wait_ssi_ready.S" +// +wait_ssi_ready: + push {r0, r1, lr} + + // Command is complete when there is nothing left to send + // (TX FIFO empty) and SSI is no longer busy (CSn deasserted) +1: + ldr r1, [r3, #SSI_SR_OFFSET] + movs r0, #SSI_SR_TFE_BITS + tst r1, r0 + beq 1b + movs r0, #SSI_SR_BUSY_BITS + tst r1, r0 + bne 1b + + pop {r0, r1, pc} + + +#ifdef PROGRAM_STATUS_REG + +// +// #include "boot2_helpers/read_flash_sreg.S" +// + +// Pass status read cmd into r0. +// Returns status value in r0. +.global read_flash_sreg +.type read_flash_sreg,%function +.thumb_func +read_flash_sreg: + push {r1, lr} + str r0, [r3, #SSI_DR0_OFFSET] + // Dummy byte: + str r0, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + // Discard first byte and combine the next two + ldr r0, [r3, #SSI_DR0_OFFSET] + ldr r0, [r3, #SSI_DR0_OFFSET] + + pop {r1, pc} + +#endif + +.global literals +literals: +.ltorg + +.end diff --git a/targets/rp2040.json b/targets/rp2040.json new file mode 100644 index 00000000..3f9fea45 --- /dev/null +++ b/targets/rp2040.json @@ -0,0 +1,23 @@ +{ + "inherits": ["cortex-m0plus"], + "build-tags": ["rp2040", "rp"], + "scheduler": "cores", + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "serial": "usb", + "msd-volume-name": ["RPI-RP2"], + "msd-firmware-name": "firmware.uf2", + "binary-format": "uf2", + "uf2-family-id": "0xe48bff56", + "rp2040-boot-patch": true, + "extra-files": [ + "src/device/rp/rp2040.s" + ], + "ldflags": [ + "--defsym=__num_stacks=2" + ], + "linkerscript": "targets/rp2040.ld", + "openocd-interface": "picoprobe", + "openocd-transport": "swd", + "openocd-target": "rp2040" +} diff --git a/targets/rp2040.ld b/targets/rp2040.ld new file mode 100644 index 00000000..118735e3 --- /dev/null +++ b/targets/rp2040.ld @@ -0,0 +1,36 @@ +MEMORY +{ + /* Reserve exactly 256 bytes at start of flash for second stage bootloader */ + BOOT2_TEXT (rx) : ORIGIN = 0x10000000, LENGTH = 256 + FLASH_TEXT (rx) : ORIGIN = 0x10000000 + 256, LENGTH = __flash_size - 256 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256k +} + +_stack_size = 2K; + +SECTIONS +{ + /* Second stage bootloader is prepended to the image. It must be 256 bytes + and checksummed. The gap to the checksum is zero-padded. + */ + .boot2 : { + __boot2_start__ = .; + KEEP (*(.boot2)); + + /* Explicitly allocate space for CRC32 checksum at end of second stage + bootloader + */ + . = __boot2_start__ + 256 - 4; + LONG(0) + } > BOOT2_TEXT = 0x0 + + /* The second stage will always enter the image at the start of .text. + The debugger will use the ELF entry point, which is the _entry_point + symbol if present, otherwise defaults to start of .text. + This can be used to transfer control back to the bootrom on debugger + launches only, to perform proper flash setup. + */ +} + + +INCLUDE "targets/arm.ld" diff --git a/targets/rp2350.json b/targets/rp2350.json new file mode 100644 index 00000000..0487aa14 --- /dev/null +++ b/targets/rp2350.json @@ -0,0 +1,22 @@ +{ + "inherits": ["cortex-m33"], + "build-tags": ["rp2350", "rp"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "serial": "usb", + "msd-volume-name": ["RP2350"], + "msd-firmware-name": "firmware.uf2", + "binary-format": "uf2", + "uf2-family-id": "0xe48bff59","comment":"See page 393 of RP2350 datasheet: RP2350 Arm Secure image (i.e. one intended to be booted directly by the bootrom)", + "extra-files": [ + "src/device/rp/rp2350.s", + "targets/rp2350_embedded_block.s" + ], + "ldflags": [ + "--defsym=__flash_size=2M" + ], + "linkerscript": "targets/rp2350.ld", + "openocd-interface": "picoprobe", + "openocd-transport": "swd", + "openocd-target": "rp2350" +} diff --git a/targets/rp2350.ld b/targets/rp2350.ld new file mode 100644 index 00000000..5296a1fb --- /dev/null +++ b/targets/rp2350.ld @@ -0,0 +1,23 @@ +/* See Rust for a more complete reference: https://github.com/rp-rs/rp-hal/blob/main/rp235x-hal-examples/memory.x */ +MEMORY +{ + /* 2MiB safe default. */ + FLASH : ORIGIN = 0x10000000, LENGTH = __flash_size + /* RAM consists of 8 banks, SRAM0..SRAM7 with striped mapping. */ + SRAM : ORIGIN = 0x20000000, LENGTH = 512k + /* Banks 8 and 9 use direct mapping which can be + specailized for applications where predictable access time is beneficial. + i.e: Separate stacks for core0 and core1. */ + SRAM4 : ORIGIN = 0x20080000, LENGTH = 4k + SRAM5 : ORIGIN = 0x20081000, LENGTH = 4k + FLASH_TEXT (rx) : ORIGIN = 0x10000000, LENGTH = __flash_size + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 512k +} + +_stack_size = 2K; + +SECTIONS +{ +} + +INCLUDE "targets/arm.ld" diff --git a/targets/rp2350_embedded_block.s b/targets/rp2350_embedded_block.s new file mode 100644 index 00000000..f6202ed8 --- /dev/null +++ b/targets/rp2350_embedded_block.s @@ -0,0 +1,10 @@ +// Minimum viable block image from datasheet section 5.9.5.1, "Minimum Arm IMAGE_DEF" +.section .after_isr_vector, "a" +.p2align 2 +embedded_block: +.word 0xffffded3 +.word 0x10210142 +.word 0x000001ff +.word 0x00000000 +.word 0xab123579 +embedded_block_end: diff --git a/targets/rp2350b.json b/targets/rp2350b.json new file mode 100644 index 00000000..5db4d484 --- /dev/null +++ b/targets/rp2350b.json @@ -0,0 +1,5 @@ +{ + "inherits": ["rp2350"], + "build-tags": ["rp2350b"], + "serial-port": ["2e8a:000f"] +} \ No newline at end of file diff --git a/targets/simavr.json b/targets/simavr.json new file mode 100644 index 00000000..012f2d94 --- /dev/null +++ b/targets/simavr.json @@ -0,0 +1,5 @@ +{ + "inherits": ["atmega1284p"], + "scheduler": "tasks", + "default-stack-size": 384 +} diff --git a/targets/stm32.ld b/targets/stm32.ld new file mode 100644 index 00000000..2953742e --- /dev/null +++ b/targets/stm32.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" diff --git a/targets/stm32f103rb.ld b/targets/stm32f103rb.ld new file mode 100644 index 00000000..358f87bc --- /dev/null +++ b/targets/stm32f103rb.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" diff --git a/targets/stm32f405.ld b/targets/stm32f405.ld new file mode 100644 index 00000000..af014af0 --- /dev/null +++ b/targets/stm32f405.ld @@ -0,0 +1,9 @@ +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 1M + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/stm32f407.ld b/targets/stm32f407.ld new file mode 100644 index 00000000..2709ca04 --- /dev/null +++ b/targets/stm32f407.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 1M + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/stm32f469.ld b/targets/stm32f469.ld new file mode 100644 index 00000000..ae559548 --- /dev/null +++ b/targets/stm32f469.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 2M + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/stm32f469disco.json b/targets/stm32f469disco.json new file mode 100644 index 00000000..37deaa3a --- /dev/null +++ b/targets/stm32f469disco.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["stm32f469disco", "stm32f469", "stm32f4", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32f469.ld", + "extra-files": [ + "src/device/stm32/stm32f469.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink", + "openocd-target": "stm32f4x" +} diff --git a/targets/stm32f4disco-1.json b/targets/stm32f4disco-1.json new file mode 100644 index 00000000..173ef3d3 --- /dev/null +++ b/targets/stm32f4disco-1.json @@ -0,0 +1,4 @@ +{ + "inherits": ["stm32f4disco"], + "openocd-interface": "stlink-v2-1" +} diff --git a/targets/stm32f4disco.json b/targets/stm32f4disco.json new file mode 100644 index 00000000..4485c41d --- /dev/null +++ b/targets/stm32f4disco.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["stm32f4disco", "stm32f407", "stm32f4", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32f407.ld", + "extra-files": [ + "src/device/stm32/stm32f407.s" + ], + "flash-method": "openocd", + "openocd-interface": "stlink-v2", + "openocd-target": "stm32f4x" +} diff --git a/targets/stm32f7x2zetx.ld b/targets/stm32f7x2zetx.ld new file mode 100644 index 00000000..83454f4e --- /dev/null +++ b/targets/stm32f7x2zetx.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 512K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/stm32l031k6.ld b/targets/stm32l031k6.ld new file mode 100644 index 00000000..f9995bc0 --- /dev/null +++ b/targets/stm32l031k6.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" \ No newline at end of file diff --git a/targets/stm32l072czt6.ld b/targets/stm32l072czt6.ld new file mode 100644 index 00000000..358f87bc --- /dev/null +++ b/targets/stm32l072czt6.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +} + +_stack_size = 2K; + +INCLUDE "targets/arm.ld" diff --git a/targets/stm32l0x2.json b/targets/stm32l0x2.json new file mode 100644 index 00000000..13b42cc5 --- /dev/null +++ b/targets/stm32l0x2.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "cortex-m0plus" + ], + "build-tags": [ + "stm32l0", + "stm32l0x2", + "stm32" + ], + "extra-files": [ + "src/device/stm32/stm32l0x2.s" + ] +} \ No newline at end of file diff --git a/targets/stm32l4x2.ld b/targets/stm32l4x2.ld new file mode 100644 index 00000000..0b236026 --- /dev/null +++ b/targets/stm32l4x2.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 256K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" \ No newline at end of file diff --git a/targets/stm32l4x5.ld b/targets/stm32l4x5.ld new file mode 100644 index 00000000..ccd47486 --- /dev/null +++ b/targets/stm32l4x5.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" \ No newline at end of file diff --git a/targets/stm32l4x6.ld b/targets/stm32l4x6.ld new file mode 100644 index 00000000..4f1ed773 --- /dev/null +++ b/targets/stm32l4x6.ld @@ -0,0 +1,11 @@ + +MEMORY +{ + FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K + RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" diff --git a/targets/stm32l5x2xe.ld b/targets/stm32l5x2xe.ld new file mode 100644 index 00000000..88a58649 --- /dev/null +++ b/targets/stm32l5x2xe.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 512K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" \ No newline at end of file diff --git a/targets/stm32wl5x_cm4.json b/targets/stm32wl5x_cm4.json new file mode 100644 index 00000000..00d8bbb8 --- /dev/null +++ b/targets/stm32wl5x_cm4.json @@ -0,0 +1,8 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": [ "stm32wl5x_cm4","stm32wlx", "stm32"], + "extra-files": [ + "src/device/stm32/stm32wl5x_cm4.s" + ], + "linkerscript": "targets/stm32wlx.ld" +} diff --git a/targets/stm32wle5.json b/targets/stm32wle5.json new file mode 100644 index 00000000..f24f28f2 --- /dev/null +++ b/targets/stm32wle5.json @@ -0,0 +1,8 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": [ "stm32wle5","stm32wlx", "stm32"], + "extra-files": [ + "src/device/stm32/stm32wle5.s" + ], + "linkerscript": "targets/stm32wlx.ld" +} diff --git a/targets/stm32wlx.ld b/targets/stm32wlx.ld new file mode 100644 index 00000000..59b61690 --- /dev/null +++ b/targets/stm32wlx.ld @@ -0,0 +1,10 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 256K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +} + +_stack_size = 4K; + +INCLUDE "targets/arm.ld" \ No newline at end of file diff --git a/targets/swan.json b/targets/swan.json new file mode 100644 index 00000000..fbb46a55 --- /dev/null +++ b/targets/swan.json @@ -0,0 +1,13 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["swan", "stm32l4r5", "stm32l4x5", "stm32l4", "stm32"], + "serial": "uart", + "linkerscript": "targets/stm32l4x5.ld", + "extra-files": [ + "src/device/stm32/stm32l4x5.s" + ], + "flash-method": "command", + "flash-command": "dfu-util --alt 0 --dfuse-address 0x08000000 --download {bin}", + "openocd-interface": "stlink", + "openocd-target": "stm32l4x" + } \ No newline at end of file diff --git a/targets/teensy36.json b/targets/teensy36.json new file mode 100644 index 00000000..253e3970 --- /dev/null +++ b/targets/teensy36.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m4"], + "build-tags": ["teensy36", "teensy", "mk66f18", "nxp"], + "serial": "uart", + "linkerscript": "targets/nxpmk66f18.ld", + "extra-files": [ + "src/device/nxp/mk66f18.s", + "targets/teensy36.s" + ], + "flash-command": "teensy_loader_cli -mmcu=mk66fx1m0 -v -w {hex}" +} + diff --git a/targets/teensy36.s b/targets/teensy36.s new file mode 100644 index 00000000..ebfaac38 --- /dev/null +++ b/targets/teensy36.s @@ -0,0 +1,19 @@ +.section .flash_config +.global __flash_config +__flash_config: + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xFF + .byte 0xDE + .byte 0xF9 + .byte 0xFF + .byte 0xFF diff --git a/targets/teensy40.json b/targets/teensy40.json new file mode 100644 index 00000000..223db6f6 --- /dev/null +++ b/targets/teensy40.json @@ -0,0 +1,13 @@ +{ + "inherits": ["cortex-m7"], + "build-tags": ["teensy40", "teensy", "mimxrt1062", "nxp"], + "serial": "uart", + "automatic-stack-size": false, + "linkerscript": "targets/mimxrt1062-teensy40.ld", + "extra-files": [ + "src/device/nxp/mimxrt1062.s", + "targets/teensy40.s" + ], + "flash-command": "teensy_loader_cli -mmcu=imxrt1062 -v -w {hex}" +} + diff --git a/targets/teensy40.s b/targets/teensy40.s new file mode 100644 index 00000000..3f7c8aa7 --- /dev/null +++ b/targets/teensy40.s @@ -0,0 +1,199 @@ +// ----------------------------------------------------------------------------- +// file: teensy40.s +// desc: various startup and configuration data for Teensy 4.0. +// ----------------------------------------------------------------------------- +// References +// i.MX RT1060 Processor Reference Manual +// - Section 9.7.1 "Image Vector Table and Boot Data" +// Teensyduino 1.53 by Paul Stoffregen (PJRC) +// - cores/teensy4/bootdata.c +// - cores/teensy4/startup.c +// ----------------------------------------------------------------------------- + +.section .boot_data +.global __boot_data +__boot_data: + .word 0x60000000 // boot start location + .word _image_size // flash size + .word 0 // plugin flag, use 0 to indicate normal (non-plugin) ROM image + +.section .ivt +.global __ivt +__ivt: + .word 0x402000D1 // header (version 4.0) + .word _svectors // image entry function + .word 0 // reserved + .word 0 // DCD info (optional, set to 0|NULL if unused) + .word __boot_data // boot data struct + .word __ivt // self + .word 0 // command sequence file (CSF) not provided in image + .word 0 // reserved + +.section .flash_config +.global __flash_config +__flash_config: + // 448 byte common FlexSPI configuration block, 8.6.3.1 page 223 (RT1060 rev 0) + // MCU_Flashloader_Reference_Manual.pdf, 8.2.1, Table 8-2, page 72-75 + .word 0x42464346 // Tag 0x00 + .word 0x56010000 // Version + .word 0 // reserved + .word 0x00020101 // columnAdressWidth,dataSetupTime,dataHoldTime,readSampleClkSrc + + .word 0x00000000 // waitTimeCfgCommands,-,deviceModeCfgEnable + .word 0 // deviceModeSeq + .word 0 // deviceModeArg + .word 0x00000000 // -,-,-,configCmdEnable + + .word 0 // configCmdSeqs 0x20 + .word 0 + .word 0 + .word 0 + + .word 0 // cfgCmdArgs 0x30 + .word 0 + .word 0 + .word 0 + + .word 0x00000000 // controllerMiscOption 0x40 + .word 0x00030401 // lutCustomSeqEnable,serialClkFreq,sflashPadType,deviceType + .word 0 // reserved + .word 0 // reserved + + .word 0x00200000 // sflashA1Size (Teensy 4.0) 0x50 + //.word 0x00800000 // sflashA1Size (Teensy 4.1) 0x50 + + .word 0 // sflashA2Size + .word 0 // sflashB1Size + .word 0 // sflashB2Size + + .word 0 // csPadSettingOverride 0x60 + .word 0 // sclkPadSettingOverride + .word 0 // dataPadSettingOverride + .word 0 // dqsPadSettingOverride + + .word 0 // timeoutInMs 0x70 + .word 0 // commandInterval + .word 0 // dataValidTime + .word 0x00000000 // busyBitPolarity,busyOffset + + .word 0x0A1804EB // lookupTable[0] 0x80 + .word 0x26043206 // lookupTable[1] + .word 0 // lookupTable[2] + .word 0 // lookupTable[3] + + .word 0x24040405 // lookupTable[4] 0x90 + .word 0 // lookupTable[5] + .word 0 // lookupTable[6] + .word 0 // lookupTable[7] + + .word 0 // lookupTable[8] 0xA0 + .word 0 // lookupTable[9] + .word 0 // lookupTable[10] + .word 0 // lookupTable[11] + + .word 0x00000406 // lookupTable[12] 0xB0 + .word 0 // lookupTable[13] + .word 0 // lookupTable[14] + .word 0 // lookupTable[15] + + .word 0 // lookupTable[16] 0xC0 + .word 0 // lookupTable[17] + .word 0 // lookupTable[18] + .word 0 // lookupTable[19] + + .word 0x08180420 // lookupTable[20] 0xD0 + .word 0 // lookupTable[21] + .word 0 // lookupTable[22] + .word 0 // lookupTable[23] + + .word 0 // lookupTable[24] 0xE0 + .word 0 // lookupTable[25] + .word 0 // lookupTable[26] + .word 0 // lookupTable[27] + + .word 0 // lookupTable[28] 0xF0 + .word 0 // lookupTable[29] + .word 0 // lookupTable[30] + .word 0 // lookupTable[31] + + .word 0x081804D8 // lookupTable[32] 0x100 + .word 0 // lookupTable[33] + .word 0 // lookupTable[34] + .word 0 // lookupTable[35] + + .word 0x08180402 // lookupTable[36] 0x110 + .word 0x00002004 // lookupTable[37] + .word 0 // lookupTable[38] + .word 0 // lookupTable[39] + + .word 0 // lookupTable[40] 0x120 + .word 0 // lookupTable[41] + .word 0 // lookupTable[42] + .word 0 // lookupTable[43] + + .word 0x00000460 // lookupTable[44] 0x130 + .word 0 // lookupTable[45] + .word 0 // lookupTable[46] + .word 0 // lookupTable[47] + + .word 0 // lookupTable[48] 0x140 + .word 0 // lookupTable[49] + .word 0 // lookupTable[50] + .word 0 // lookupTable[51] + + .word 0 // lookupTable[52] 0x150 + .word 0 // lookupTable[53] + .word 0 // lookupTable[54] + .word 0 // lookupTable[55] + + .word 0 // lookupTable[56] 0x160 + .word 0 // lookupTable[57] + .word 0 // lookupTable[58] + .word 0 // lookupTable[59] + + .word 0 // lookupTable[60] 0x170 + .word 0 // lookupTable[61] + .word 0 // lookupTable[62] + .word 0 // lookupTable[63] + + .word 0 // LUT 0: Read 0x180 + .word 0 // LUT 1: ReadStatus + .word 0 // LUT 3: WriteEnable + .word 0 // LUT 5: EraseSector + + .word 0 // LUT 9: PageProgram 0x190 + .word 0 // LUT 11: ChipErase + .word 0 // LUT 15: Dummy + .word 0 // LUT unused? + + .word 0 // LUT unused? 0x1A0 + .word 0 // LUT unused? + .word 0 // LUT unused? + .word 0 // LUT unused? + + .word 0 // reserved 0x1B0 + .word 0 // reserved + .word 0 // reserved + .word 0 // reserved + + // 64 byte Serial NOR configuration block (8.6.3.2, page 346) + + .word 256 // pageSize 0x1C0 + .word 4096 // sectorSize + .word 1 // ipCmdSerialClkFreq + .word 0 // reserved + + .word 0x00010000 // block size 0x1D0 + .word 0 // reserved + .word 0 // reserved + .word 0 // reserved + + .word 0 // reserved 0x1E0 + .word 0 // reserved + .word 0 // reserved + .word 0 // reserved + + .word 0 // reserved 0x1F0 + .word 0 // reserved + .word 0 // reserved + .word 0 // reserved diff --git a/targets/teensy41.json b/targets/teensy41.json new file mode 100644 index 00000000..8866bc48 --- /dev/null +++ b/targets/teensy41.json @@ -0,0 +1,12 @@ +{ + "inherits": ["cortex-m7"], + "build-tags": ["teensy41", "teensy", "mimxrt1062", "nxp"], + "serial": "uart", + "automatic-stack-size": false, + "linkerscript": "targets/mimxrt1062-teensy40.ld", + "extra-files": [ + "src/device/nxp/mimxrt1062.s", + "targets/teensy40.s" + ], + "flash-command": "teensy_loader_cli -mmcu=imxrt1062 -v -w {hex}" +} diff --git a/targets/thingplus-rp2040.json b/targets/thingplus-rp2040.json new file mode 100644 index 00000000..6718b86d --- /dev/null +++ b/targets/thingplus-rp2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["1b4f:0026"], + "build-tags": ["thingplus_rp2040"], + "ldflags": [ + "--defsym=__flash_size=16M" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/thumby.json b/targets/thumby.json new file mode 100644 index 00000000..41cbc5e1 --- /dev/null +++ b/targets/thumby.json @@ -0,0 +1,14 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:0005"], + "build-tags": ["thumby"], + "default-stack-size": 8192, + "ldflags": [ + "--defsym=__flash_size=2048K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/tiny2350.json b/targets/tiny2350.json new file mode 100644 index 00000000..660e0964 --- /dev/null +++ b/targets/tiny2350.json @@ -0,0 +1,10 @@ +{ + "inherits": [ + "rp2350" + ], + "build-tags": ["tiny2350"], + "ldflags": [ + "--defsym=__flash_size=4M" + ], + "serial-port": ["2e8a:000f"] +} diff --git a/targets/tkey.json b/targets/tkey.json new file mode 100644 index 00000000..3a52cae2 --- /dev/null +++ b/targets/tkey.json @@ -0,0 +1,13 @@ +{ + "inherits": ["riscv32"], + "build-tags": ["tkey"], + "features": "+32bit,+c,+zmmul,-a,-b,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-f,-h,-m,-relax,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xesppie,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b", + "cflags": [ + "-march=rv32iczmmul" + ], + "linkerscript": "targets/tkey.ld", + "scheduler": "none", + "gc": "conservative", + "flash-command": "tkey-runapp {bin}", + "serial": "uart" +} diff --git a/targets/tkey.ld b/targets/tkey.ld new file mode 100644 index 00000000..09becf40 --- /dev/null +++ b/targets/tkey.ld @@ -0,0 +1,11 @@ + +MEMORY +{ + RAM (rwx) : ORIGIN = 0x40000000, LENGTH = 0x20000 /* 128 KB */ +} + +REGION_ALIAS("FLASH_TEXT", RAM); + +_stack_size = 2K; + +INCLUDE "targets/riscv.ld" diff --git a/targets/trinket-m0.json b/targets/trinket-m0.json new file mode 100644 index 00000000..91dd48b9 --- /dev/null +++ b/targets/trinket-m0.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd21e18a"], + "build-tags": ["trinket_m0"], + "serial": "usb", + "serial-port": ["239a:801e"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["TRINKETBOOT"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/trinkey-qt2040-boot-stage2.S b/targets/trinkey-qt2040-boot-stage2.S new file mode 100644 index 00000000..5683979d --- /dev/null +++ b/targets/trinkey-qt2040-boot-stage2.S @@ -0,0 +1,17 @@ +// Adafruit Trinkey QT2040 Stage 2 Bootloader + +// +// This file defines the parameters specific to the flash-chip found +// on the Adafruit Trinkey QT2040. The generic implementation is in +// rp2040-boot-stage2.S +// + +#define BOARD_PICO_FLASH_SPI_CLKDIV 4 +#define BOARD_CMD_READ 0xe7 +#define BOARD_QUAD_OK 1 +#define BOARD_QUAD_ENABLE_STATUS_BYTE 2 +#define BOARD_QUAD_ENABLE_BIT_MASK 2 +#define BOARD_SPLIT_STATUS_WRITE 1 +#define BOARD_WAIT_CYCLES 2 + +#include "rp2040-boot-stage2.S" diff --git a/targets/trinkey-qt2040.json b/targets/trinkey-qt2040.json new file mode 100644 index 00000000..23ae3f6c --- /dev/null +++ b/targets/trinkey-qt2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["239a:8109"], + "build-tags": ["trinkey_qt2040"], + "ldflags": [ + "--defsym=__flash_size=8192K" + ], + "extra-files": [ + "targets/trinkey-qt2040-boot-stage2.S" + ] +} diff --git a/targets/tufty2040.json b/targets/tufty2040.json new file mode 100644 index 00000000..11c4e334 --- /dev/null +++ b/targets/tufty2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:0003"], + "build-tags": ["tufty2040"], + "ldflags": [ + "--defsym=__flash_size=1020K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/wasi.json b/targets/wasi.json new file mode 100644 index 00000000..21d56941 --- /dev/null +++ b/targets/wasi.json @@ -0,0 +1,3 @@ +{ + "inherits": ["wasip1"] +} diff --git a/targets/wasip1.json b/targets/wasip1.json new file mode 100644 index 00000000..8abc65e1 --- /dev/null +++ b/targets/wasip1.json @@ -0,0 +1,30 @@ +{ + "llvm-target": "wasm32-unknown-wasi", + "cpu": "generic", + "features": "+bulk-memory,+mutable-globals,+nontrapping-fptoint,+sign-ext,-multivalue,-reference-types", + "build-tags": ["tinygo.wasm"], + "goos": "wasip1", + "goarch": "wasm", + "linker": "wasm-ld", + "libc": "wasi-libc", + "rtlib": "compiler-rt", + "gc": "precise", + "scheduler": "asyncify", + "default-stack-size": 65536, + "cflags": [ + "-mbulk-memory", + "-mnontrapping-fptoint", + "-mno-multivalue", + "-mno-reference-types", + "-msign-ext" + ], + "ldflags": [ + "--stack-first", + "--no-demangle" + ], + "extra-files": [ + "src/runtime/asm_tinygowasm.S", + "src/runtime/gc_boehm.c" + ], + "emulator": "wasmtime run --dir={tmpDir}::/tmp {}" +} diff --git a/targets/wasip2.json b/targets/wasip2.json new file mode 100644 index 00000000..66e79eda --- /dev/null +++ b/targets/wasip2.json @@ -0,0 +1,33 @@ +{ + "llvm-target": "wasm32-unknown-wasi", + "cpu": "generic", + "features": "+bulk-memory,+mutable-globals,+nontrapping-fptoint,+sign-ext,-multivalue,-reference-types", + "build-tags": ["tinygo.wasm", "wasip2"], + "buildmode": "c-shared", + "goos": "linux", + "goarch": "arm", + "linker": "wasm-ld", + "libc": "wasmbuiltins", + "rtlib": "compiler-rt", + "gc": "precise", + "scheduler": "asyncify", + "default-stack-size": 65536, + "cflags": [ + "-mbulk-memory", + "-mnontrapping-fptoint", + "-mno-multivalue", + "-mno-reference-types", + "-msign-ext" + ], + "ldflags": [ + "--stack-first", + "--no-demangle", + "--no-entry" + ], + "extra-files": [ + "src/runtime/asm_tinygowasm.S" + ], + "emulator": "wasmtime run --wasm component-model -Sinherit-network -Sallow-ip-name-lookup --dir={tmpDir}::/tmp {}", + "wit-package": "{root}/lib/wasi-cli/wit/", + "wit-world": "wasi:cli/command" +} diff --git a/targets/wasm-undefined.txt b/targets/wasm-undefined.txt new file mode 100644 index 00000000..ccb6c13c --- /dev/null +++ b/targets/wasm-undefined.txt @@ -0,0 +1,16 @@ +syscall/js.copyBytesToGo +syscall/js.copyBytesToJS +syscall/js.finalizeRef +syscall/js.stringVal +syscall/js.valueCall +syscall/js.valueDelete +syscall/js.valueGet +syscall/js.valueIndex +syscall/js.valueInstanceOf +syscall/js.valueInvoke +syscall/js.valueLength +syscall/js.valueLoadString +syscall/js.valueNew +syscall/js.valuePrepareString +syscall/js.valueSet +syscall/js.valueSetIndex diff --git a/targets/wasm-unknown.json b/targets/wasm-unknown.json new file mode 100644 index 00000000..d64fa575 --- /dev/null +++ b/targets/wasm-unknown.json @@ -0,0 +1,30 @@ +{ + "llvm-target": "wasm32-unknown-unknown", + "cpu": "generic", + "features": "+mutable-globals,+nontrapping-fptoint,+sign-ext,-multivalue,-reference-types", + "build-tags": ["tinygo.wasm", "wasm_unknown"], + "buildmode": "c-shared", + "goos": "linux", + "goarch": "arm", + "linker": "wasm-ld", + "rtlib": "compiler-rt", + "libc": "wasmbuiltins", + "scheduler": "none", + "gc": "leaking", + "default-stack-size": 4096, + "cflags": [ + "-mnontrapping-fptoint", + "-mno-multivalue", + "-mno-reference-types", + "-msign-ext" + ], + "ldflags": [ + "--stack-first", + "--no-demangle", + "--no-entry" + ], + "extra-files": [ + "src/runtime/asm_tinygowasm.S" + ], + "emulator": "wasmtime run --dir={tmpDir}::/tmp {}" +} diff --git a/targets/wasm.json b/targets/wasm.json new file mode 100644 index 00000000..a8641636 --- /dev/null +++ b/targets/wasm.json @@ -0,0 +1,31 @@ +{ + "llvm-target": "wasm32-unknown-wasi", + "cpu": "generic", + "features": "+bulk-memory,+mutable-globals,+nontrapping-fptoint,+sign-ext,-multivalue,-reference-types", + "build-tags": ["tinygo.wasm"], + "goos": "js", + "goarch": "wasm", + "linker": "wasm-ld", + "libc": "wasi-libc", + "rtlib": "compiler-rt", + "gc": "precise", + "scheduler": "asyncify", + "default-stack-size": 65536, + "cflags": [ + "-mbulk-memory", + "-mnontrapping-fptoint", + "-mno-multivalue", + "-mno-reference-types", + "-msign-ext" + ], + "ldflags": [ + "--allow-undefined-file={root}/targets/wasm-undefined.txt", + "--stack-first", + "--no-demangle" + ], + "extra-files": [ + "src/runtime/asm_tinygowasm.S", + "src/runtime/gc_boehm.c" + ], + "emulator": "node {root}/targets/wasm_exec.js {}" +} diff --git a/targets/wasm_exec.js b/targets/wasm_exec.js new file mode 100644 index 00000000..fa731a98 --- /dev/null +++ b/targets/wasm_exec.js @@ -0,0 +1,553 @@ +// Copyright 2018 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. +// +// This file has been modified for use by the TinyGo compiler. + +(() => { + // Map multiple JavaScript environments to a single common API, + // preferring web standards over Node.js API. + // + // Environments considered: + // - Browsers + // - Node.js + // - Electron + // - Parcel + + if (typeof global !== "undefined") { + // global already exists + } else if (typeof window !== "undefined") { + window.global = window; + } else if (typeof self !== "undefined") { + self.global = self; + } else { + throw new Error("cannot export Go (neither global, window nor self is defined)"); + } + + if (!global.require && typeof require !== "undefined") { + global.require = require; + } + + if (!global.fs && global.require) { + global.fs = require("node:fs"); + } + + const enosys = () => { + const err = new Error("not implemented"); + err.code = "ENOSYS"; + return err; + }; + + if (!global.fs) { + let outputBuf = ""; + global.fs = { + constants: { O_WRONLY: -1, O_RDWR: -1, O_CREAT: -1, O_TRUNC: -1, O_APPEND: -1, O_EXCL: -1 }, // unused + writeSync(fd, buf) { + outputBuf += decoder.decode(buf); + const nl = outputBuf.lastIndexOf("\n"); + if (nl != -1) { + console.log(outputBuf.substr(0, nl)); + outputBuf = outputBuf.substr(nl + 1); + } + return buf.length; + }, + write(fd, buf, offset, length, position, callback) { + if (offset !== 0 || length !== buf.length || position !== null) { + callback(enosys()); + return; + } + const n = this.writeSync(fd, buf); + callback(null, n); + }, + chmod(path, mode, callback) { callback(enosys()); }, + chown(path, uid, gid, callback) { callback(enosys()); }, + close(fd, callback) { callback(enosys()); }, + fchmod(fd, mode, callback) { callback(enosys()); }, + fchown(fd, uid, gid, callback) { callback(enosys()); }, + fstat(fd, callback) { callback(enosys()); }, + fsync(fd, callback) { callback(null); }, + ftruncate(fd, length, callback) { callback(enosys()); }, + lchown(path, uid, gid, callback) { callback(enosys()); }, + link(path, link, callback) { callback(enosys()); }, + lstat(path, callback) { callback(enosys()); }, + mkdir(path, perm, callback) { callback(enosys()); }, + open(path, flags, mode, callback) { callback(enosys()); }, + read(fd, buffer, offset, length, position, callback) { callback(enosys()); }, + readdir(path, callback) { callback(enosys()); }, + readlink(path, callback) { callback(enosys()); }, + rename(from, to, callback) { callback(enosys()); }, + rmdir(path, callback) { callback(enosys()); }, + stat(path, callback) { callback(enosys()); }, + symlink(path, link, callback) { callback(enosys()); }, + truncate(path, length, callback) { callback(enosys()); }, + unlink(path, callback) { callback(enosys()); }, + utimes(path, atime, mtime, callback) { callback(enosys()); }, + }; + } + + if (!global.process) { + global.process = { + getuid() { return -1; }, + getgid() { return -1; }, + geteuid() { return -1; }, + getegid() { return -1; }, + getgroups() { throw enosys(); }, + pid: -1, + ppid: -1, + umask() { throw enosys(); }, + cwd() { throw enosys(); }, + chdir() { throw enosys(); }, + } + } + + if (!global.crypto) { + const nodeCrypto = require("node:crypto"); + global.crypto = { + getRandomValues(b) { + nodeCrypto.randomFillSync(b); + }, + }; + } + + if (!global.performance) { + global.performance = { + now() { + const [sec, nsec] = process.hrtime(); + return sec * 1000 + nsec / 1000000; + }, + }; + } + + if (!global.TextEncoder) { + global.TextEncoder = require("node:util").TextEncoder; + } + + if (!global.TextDecoder) { + global.TextDecoder = require("node:util").TextDecoder; + } + + // End of polyfills for common API. + + const encoder = new TextEncoder("utf-8"); + const decoder = new TextDecoder("utf-8"); + let reinterpretBuf = new DataView(new ArrayBuffer(8)); + var logLine = []; + const wasmExit = {}; // thrown to exit via proc_exit (not an error) + + global.Go = class { + constructor() { + this._callbackTimeouts = new Map(); + this._nextCallbackTimeoutID = 1; + + const mem = () => { + // The buffer may change when requesting more memory. + return new DataView(this._inst.exports.memory.buffer); + } + + const unboxValue = (v_ref) => { + reinterpretBuf.setBigInt64(0, v_ref, true); + const f = reinterpretBuf.getFloat64(0, true); + if (f === 0) { + return undefined; + } + if (!isNaN(f)) { + return f; + } + + const id = v_ref & 0xffffffffn; + return this._values[id]; + } + + + const loadValue = (addr) => { + let v_ref = mem().getBigUint64(addr, true); + return unboxValue(v_ref); + } + + const boxValue = (v) => { + const nanHead = 0x7FF80000n; + + if (typeof v === "number") { + if (isNaN(v)) { + return nanHead << 32n; + } + if (v === 0) { + return (nanHead << 32n) | 1n; + } + reinterpretBuf.setFloat64(0, v, true); + return reinterpretBuf.getBigInt64(0, true); + } + + switch (v) { + case undefined: + return 0n; + case null: + return (nanHead << 32n) | 2n; + case true: + return (nanHead << 32n) | 3n; + case false: + return (nanHead << 32n) | 4n; + } + + let id = this._ids.get(v); + if (id === undefined) { + id = this._idPool.pop(); + if (id === undefined) { + id = BigInt(this._values.length); + } + this._values[id] = v; + this._goRefCounts[id] = 0; + this._ids.set(v, id); + } + this._goRefCounts[id]++; + let typeFlag = 1n; + switch (typeof v) { + case "string": + typeFlag = 2n; + break; + case "symbol": + typeFlag = 3n; + break; + case "function": + typeFlag = 4n; + break; + } + return id | ((nanHead | typeFlag) << 32n); + } + + const storeValue = (addr, v) => { + let v_ref = boxValue(v); + mem().setBigUint64(addr, v_ref, true); + } + + const loadSlice = (array, len, cap) => { + return new Uint8Array(this._inst.exports.memory.buffer, array, len); + } + + const loadSliceOfValues = (array, len, cap) => { + const a = new Array(len); + for (let i = 0; i < len; i++) { + a[i] = loadValue(array + i * 8); + } + return a; + } + + const loadString = (ptr, len) => { + return decoder.decode(new DataView(this._inst.exports.memory.buffer, ptr, len)); + } + + const timeOrigin = Date.now() - performance.now(); + this.importObject = { + wasi_snapshot_preview1: { + // https://github.com/WebAssembly/WASI/blob/main/phases/snapshot/docs.md#fd_write + fd_write: function(fd, iovs_ptr, iovs_len, nwritten_ptr) { + let nwritten = 0; + if (fd == 1) { + for (let iovs_i=0; iovs_i 0, // dummy + fd_fdstat_get: () => 0, // dummy + fd_seek: () => 0, // dummy + proc_exit: (code) => { + this.exited = true; + this.exitCode = code; + this._resolveExitPromise(); + throw wasmExit; + }, + random_get: (bufPtr, bufLen) => { + crypto.getRandomValues(loadSlice(bufPtr, bufLen)); + return 0; + }, + }, + gojs: { + // func ticks() int64 + "runtime.ticks": () => { + return BigInt((timeOrigin + performance.now()) * 1e6); + }, + + // func sleepTicks(timeout int64) + "runtime.sleepTicks": (timeout) => { + // Do not sleep, only reactivate scheduler after the given timeout. + setTimeout(() => { + if (this.exited) return; + try { + this._inst.exports.go_scheduler(); + } catch (e) { + if (e !== wasmExit) throw e; + } + }, Number(timeout)/1e6); + }, + + // func finalizeRef(v ref) + "syscall/js.finalizeRef": (v_ref) => { + // Note: TinyGo does not support finalizers so this is only called + // for one specific case, by js.go:jsString. and can/might leak memory. + const id = v_ref & 0xffffffffn; + if (this._goRefCounts?.[id] !== undefined) { + this._goRefCounts[id]--; + if (this._goRefCounts[id] === 0) { + const v = this._values[id]; + this._values[id] = null; + this._ids.delete(v); + this._idPool.push(id); + } + } else { + console.error("syscall/js.finalizeRef: unknown id", id); + } + }, + + // func stringVal(value string) ref + "syscall/js.stringVal": (value_ptr, value_len) => { + value_ptr >>>= 0; + const s = loadString(value_ptr, value_len); + return boxValue(s); + }, + + // func valueGet(v ref, p string) ref + "syscall/js.valueGet": (v_ref, p_ptr, p_len) => { + let prop = loadString(p_ptr, p_len); + let v = unboxValue(v_ref); + let result = Reflect.get(v, prop); + return boxValue(result); + }, + + // func valueSet(v ref, p string, x ref) + "syscall/js.valueSet": (v_ref, p_ptr, p_len, x_ref) => { + const v = unboxValue(v_ref); + const p = loadString(p_ptr, p_len); + const x = unboxValue(x_ref); + Reflect.set(v, p, x); + }, + + // func valueDelete(v ref, p string) + "syscall/js.valueDelete": (v_ref, p_ptr, p_len) => { + const v = unboxValue(v_ref); + const p = loadString(p_ptr, p_len); + Reflect.deleteProperty(v, p); + }, + + // func valueIndex(v ref, i int) ref + "syscall/js.valueIndex": (v_ref, i) => { + return boxValue(Reflect.get(unboxValue(v_ref), i)); + }, + + // valueSetIndex(v ref, i int, x ref) + "syscall/js.valueSetIndex": (v_ref, i, x_ref) => { + Reflect.set(unboxValue(v_ref), i, unboxValue(x_ref)); + }, + + // func valueCall(v ref, m string, args []ref) (ref, bool) + "syscall/js.valueCall": (ret_addr, v_ref, m_ptr, m_len, args_ptr, args_len, args_cap) => { + const v = unboxValue(v_ref); + const name = loadString(m_ptr, m_len); + const args = loadSliceOfValues(args_ptr, args_len, args_cap); + try { + const m = Reflect.get(v, name); + storeValue(ret_addr, Reflect.apply(m, v, args)); + mem().setUint8(ret_addr + 8, 1); + } catch (err) { + storeValue(ret_addr, err); + mem().setUint8(ret_addr + 8, 0); + } + }, + + // func valueInvoke(v ref, args []ref) (ref, bool) + "syscall/js.valueInvoke": (ret_addr, v_ref, args_ptr, args_len, args_cap) => { + try { + const v = unboxValue(v_ref); + const args = loadSliceOfValues(args_ptr, args_len, args_cap); + storeValue(ret_addr, Reflect.apply(v, undefined, args)); + mem().setUint8(ret_addr + 8, 1); + } catch (err) { + storeValue(ret_addr, err); + mem().setUint8(ret_addr + 8, 0); + } + }, + + // func valueNew(v ref, args []ref) (ref, bool) + "syscall/js.valueNew": (ret_addr, v_ref, args_ptr, args_len, args_cap) => { + const v = unboxValue(v_ref); + const args = loadSliceOfValues(args_ptr, args_len, args_cap); + try { + storeValue(ret_addr, Reflect.construct(v, args)); + mem().setUint8(ret_addr + 8, 1); + } catch (err) { + storeValue(ret_addr, err); + mem().setUint8(ret_addr+ 8, 0); + } + }, + + // func valueLength(v ref) int + "syscall/js.valueLength": (v_ref) => { + return unboxValue(v_ref).length; + }, + + // valuePrepareString(v ref) (ref, int) + "syscall/js.valuePrepareString": (ret_addr, v_ref) => { + const s = String(unboxValue(v_ref)); + const str = encoder.encode(s); + storeValue(ret_addr, str); + mem().setInt32(ret_addr + 8, str.length, true); + }, + + // valueLoadString(v ref, b []byte) + "syscall/js.valueLoadString": (v_ref, slice_ptr, slice_len, slice_cap) => { + const str = unboxValue(v_ref); + loadSlice(slice_ptr, slice_len, slice_cap).set(str); + }, + + // func valueInstanceOf(v ref, t ref) bool + "syscall/js.valueInstanceOf": (v_ref, t_ref) => { + return unboxValue(v_ref) instanceof unboxValue(t_ref); + }, + + // func copyBytesToGo(dst []byte, src ref) (int, bool) + "syscall/js.copyBytesToGo": (ret_addr, dest_addr, dest_len, dest_cap, src_ref) => { + let num_bytes_copied_addr = ret_addr; + let returned_status_addr = ret_addr + 4; // Address of returned boolean status variable + + const dst = loadSlice(dest_addr, dest_len); + const src = unboxValue(src_ref); + if (!(src instanceof Uint8Array || src instanceof Uint8ClampedArray)) { + mem().setUint8(returned_status_addr, 0); // Return "not ok" status + return; + } + const toCopy = src.subarray(0, dst.length); + dst.set(toCopy); + mem().setUint32(num_bytes_copied_addr, toCopy.length, true); + mem().setUint8(returned_status_addr, 1); // Return "ok" status + }, + + // copyBytesToJS(dst ref, src []byte) (int, bool) + // Originally copied from upstream Go project, then modified: + // https://github.com/golang/go/blob/3f995c3f3b43033013013e6c7ccc93a9b1411ca9/misc/wasm/wasm_exec.js#L404-L416 + "syscall/js.copyBytesToJS": (ret_addr, dst_ref, src_addr, src_len, src_cap) => { + let num_bytes_copied_addr = ret_addr; + let returned_status_addr = ret_addr + 4; // Address of returned boolean status variable + + const dst = unboxValue(dst_ref); + const src = loadSlice(src_addr, src_len); + if (!(dst instanceof Uint8Array || dst instanceof Uint8ClampedArray)) { + mem().setUint8(returned_status_addr, 0); // Return "not ok" status + return; + } + const toCopy = src.subarray(0, dst.length); + dst.set(toCopy); + mem().setUint32(num_bytes_copied_addr, toCopy.length, true); + mem().setUint8(returned_status_addr, 1); // Return "ok" status + }, + } + }; + + // Go 1.20 uses 'env'. Go 1.21 uses 'gojs'. + // For compatibility, we use both as long as Go 1.20 is supported. + this.importObject.env = this.importObject.gojs; + } + + async run(instance) { + this._inst = instance; + this._values = [ // JS values that Go currently has references to, indexed by reference id + NaN, + 0, + null, + true, + false, + global, + this, + ]; + this._goRefCounts = []; // number of references that Go has to a JS value, indexed by reference id + this._ids = new Map(); // mapping from JS values to reference ids + this._idPool = []; // unused ids that have been garbage collected + this.exited = false; // whether the Go program has exited + this.exitCode = 0; + + if (this._inst.exports._start) { + let exitPromise = new Promise((resolve, reject) => { + this._resolveExitPromise = resolve; + }); + + // Run program, but catch the wasmExit exception that's thrown + // to return back here. + try { + this._inst.exports._start(); + } catch (e) { + if (e !== wasmExit) throw e; + } + + await exitPromise; + return this.exitCode; + } else { + this._inst.exports._initialize(); + } + } + + _resume() { + if (this.exited) { + throw new Error("Go program has already exited"); + } + try { + this._inst.exports.resume(); + } catch (e) { + if (e !== wasmExit) throw e; + } + if (this.exited) { + this._resolveExitPromise(); + } + } + + _makeFuncWrapper(id) { + const go = this; + return function () { + const event = { id: id, this: this, args: arguments }; + go._pendingEvent = event; + go._resume(); + return event.result; + }; + } + } + + if ( + global.require && + global.require.main === module && + global.process && + global.process.versions && + !global.process.versions.electron + ) { + if (process.argv.length != 3) { + console.error("usage: go_js_wasm_exec [wasm binary] [arguments]"); + process.exit(1); + } + + const go = new Go(); + WebAssembly.instantiate(fs.readFileSync(process.argv[2]), go.importObject).then(async (result) => { + let exitCode = await go.run(result.instance); + process.exit(exitCode); + }).catch((err) => { + console.error(err); + process.exit(1); + }); + } +})(); diff --git a/targets/waveshare-rp2040-tiny.json b/targets/waveshare-rp2040-tiny.json new file mode 100644 index 00000000..74b651b5 --- /dev/null +++ b/targets/waveshare-rp2040-tiny.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:0003"], + "build-tags": ["waveshare_rp2040_tiny"], + "ldflags": [ + "--defsym=__flash_size=1020K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/waveshare-rp2040-zero.json b/targets/waveshare-rp2040-zero.json new file mode 100644 index 00000000..a31c4e84 --- /dev/null +++ b/targets/waveshare-rp2040-zero.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:0003"], + "build-tags": ["waveshare_rp2040_zero"], + "ldflags": [ + "--defsym=__flash_size=1020K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/wioterminal.json b/targets/wioterminal.json new file mode 100644 index 00000000..64b505de --- /dev/null +++ b/targets/wioterminal.json @@ -0,0 +1,11 @@ +{ + "inherits": ["atsamd51p19a"], + "build-tags": ["wioterminal"], + "serial": "usb", + "serial-port": ["2886:802d"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["Arduino"], + "msd-firmware-name": "firmware.uf2", + "openocd-verify": true +} diff --git a/targets/x9pro.json b/targets/x9pro.json new file mode 100644 index 00000000..9b966b4b --- /dev/null +++ b/targets/x9pro.json @@ -0,0 +1,9 @@ +{ + "inherits": ["nrf52"], + "build-tags": ["x9pro"], + "serial": "uart", + "flash-method": "openocd", + "flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset", + "openocd-interface": "jlink", + "openocd-transport": "swd" +} diff --git a/targets/xiao-ble.json b/targets/xiao-ble.json new file mode 100644 index 00000000..a9359cd4 --- /dev/null +++ b/targets/xiao-ble.json @@ -0,0 +1,6 @@ +{ + "inherits": ["nrf52840", "nrf52840-s140v7-uf2"], + "build-tags": ["xiao_ble"], + "serial-port": ["2886:8045"], + "msd-volume-name": ["XIAO-SENSE"] +} diff --git a/targets/xiao-esp32c3.json b/targets/xiao-esp32c3.json new file mode 100644 index 00000000..d292fa48 --- /dev/null +++ b/targets/xiao-esp32c3.json @@ -0,0 +1,4 @@ +{ + "inherits": ["esp32c3"], + "build-tags": ["xiao_esp32c3"] +} diff --git a/targets/xiao-rp2040.json b/targets/xiao-rp2040.json new file mode 100644 index 00000000..02a36c06 --- /dev/null +++ b/targets/xiao-rp2040.json @@ -0,0 +1,13 @@ +{ + "inherits": [ + "rp2040" + ], + "serial-port": ["2e8a:000a"], + "build-tags": ["xiao_rp2040"], + "ldflags": [ + "--defsym=__flash_size=1020K" + ], + "extra-files": [ + "targets/pico-boot-stage2.S" + ] +} diff --git a/targets/xiao.json b/targets/xiao.json new file mode 100644 index 00000000..f5878743 --- /dev/null +++ b/targets/xiao.json @@ -0,0 +1,10 @@ +{ + "inherits": ["atsamd21g18a"], + "build-tags": ["xiao"], + "serial": "usb", + "serial-port": ["2886:802f"], + "flash-1200-bps-reset": "true", + "flash-method": "msd", + "msd-volume-name": ["Arduino","Seeed XIAO"], + "msd-firmware-name": "firmware.uf2" +} diff --git a/targets/xtensa.json b/targets/xtensa.json new file mode 100644 index 00000000..893a3eb7 --- /dev/null +++ b/targets/xtensa.json @@ -0,0 +1,18 @@ +{ + "llvm-target": "xtensa", + "goos": "linux", + "goarch": "arm", + "build-tags": ["xtensa", "baremetal", "linux", "arm"], + "gc": "conservative", + "scheduler": "none", + "cflags": [ + "-Werror", + "-fshort-enums", + "-Wno-macro-redefined", + "-fno-exceptions", "-fno-unwind-tables", "-fno-asynchronous-unwind-tables", + "-ffunction-sections", "-fdata-sections" + ], + "ldflags": [ + "--gc-sections" + ] +} From 0c11c93b3a416b3df8bcc3a1bb193d6b41a857e0 Mon Sep 17 00:00:00 2001 From: Li Jie Date: Sat, 26 Jul 2025 10:52:58 +1000 Subject: [PATCH 2/9] docs: add LICENSE file for targets directory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add license attribution for target configuration files derived from TinyGo project: - Document source from https://github.com/tinygo-org/tinygo/tree/release/targets - Include complete BSD 3-Clause license from TinyGo project - Clarify licensing terms for target configuration files - Ensure proper attribution to TinyGo Authors and Go Authors - Maintain compliance with original license requirements This ensures proper license compliance when using TinyGo's target configurations in the llgo project. 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude --- targets/LICENSE | 61 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 targets/LICENSE diff --git a/targets/LICENSE b/targets/LICENSE new file mode 100644 index 00000000..d5f1b9a8 --- /dev/null +++ b/targets/LICENSE @@ -0,0 +1,61 @@ +Target Configuration Files License +===================================== + +The target configuration files in this directory are derived from the TinyGo project +(https://github.com/tinygo-org/tinygo/tree/release/targets) and are subject to the +TinyGo project's license terms. + +Original source: https://github.com/tinygo-org/tinygo/tree/release/targets +License: BSD 3-Clause License (same as TinyGo project) + +-------------------------------------------------------------------------------- + +TinyGo License (BSD 3-Clause) +============================== + +Copyright (c) 2018-2025 The TinyGo Authors. All rights reserved. + +TinyGo includes portions of the Go standard library. +Copyright (c) 2009-2024 The Go Authors. All rights reserved. + +TinyGo includes portions of LLVM, which is under the Apache License v2.0 with +LLVM Exceptions. See https://llvm.org/LICENSE.txt for license information. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + + * Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above +copyright notice, this list of conditions and the following disclaimer +in the documentation and/or other materials provided with the +distribution. + * Neither the name of the copyright holder nor the names of its +contributors may be used to endorse or promote products derived from +this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +-------------------------------------------------------------------------------- + +Usage in llgo project +====================== + +These target configuration files have been adapted for use in the llgo project +to provide cross-compilation support for embedded platforms. The files maintain +their original structure and content while being integrated into llgo's build +system. + +Any modifications or adaptations to these files for llgo-specific use are +released under the same BSD 3-Clause license terms as the original TinyGo project. \ No newline at end of file From 5424b53b623abc665892f28090539d28383abf87 Mon Sep 17 00:00:00 2001 From: Li Jie Date: Sat, 26 Jul 2025 12:05:19 +1000 Subject: [PATCH 3/9] feat(crosscompile): extend Export struct and add target-based configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Add LLVMTarget, CPU, Features, BuildTags fields to Export struct - Implement UseTarget() function for target name-based configuration loading - Add UseWithTarget() function combining target and goos/goarch fallback - Include comprehensive unit tests for target integration - Support 206+ embedded platform configurations with inheritance 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude --- .../{cosscompile.go => crosscompile.go} | 131 ++++++++++++- internal/crosscompile/crosscompile_test.go | 179 ++++++++++++++++++ 2 files changed, 306 insertions(+), 4 deletions(-) rename internal/crosscompile/{cosscompile.go => crosscompile.go} (58%) diff --git a/internal/crosscompile/cosscompile.go b/internal/crosscompile/crosscompile.go similarity index 58% rename from internal/crosscompile/cosscompile.go rename to internal/crosscompile/crosscompile.go index f066c8ac..17bd05aa 100644 --- a/internal/crosscompile/cosscompile.go +++ b/internal/crosscompile/crosscompile.go @@ -2,12 +2,15 @@ package crosscompile import ( "errors" + "fmt" "io/fs" "os" "path/filepath" "runtime" + "strings" "github.com/goplus/llgo/internal/env" + "github.com/goplus/llgo/internal/targets" "github.com/goplus/llgo/internal/xtool/llvm" ) @@ -17,6 +20,15 @@ type Export struct { CFLAGS []string LDFLAGS []string EXTRAFLAGS []string + + // Additional fields from target configuration + LLVMTarget string + CPU string + Features string + BuildTags []string + GOOS string + GOARCH string + Linker string // Linker to use (e.g., "ld.lld", "avr-ld") } const wasiSdkUrl = "https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-25/wasi-sdk-25.0-x86_64-macos.tar.gz" @@ -109,8 +121,8 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { "-I" + includeDir, } // Add WebAssembly linker flags - export.LDFLAGS = []string{ - "-target", targetTriple, + export.LDFLAGS = append(export.LDFLAGS, export.CCFLAGS...) + export.LDFLAGS = append(export.LDFLAGS, []string{ "-Wno-override-module", "-Wl,--error-limit=0", "-L" + libDir, @@ -134,18 +146,18 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { "-lwasi-emulated-signal", "-fwasm-exceptions", "-mllvm", "-wasm-enable-sjlj", - } + }...) // Add thread support if enabled if wasiThreads { export.CCFLAGS = append( export.CCFLAGS, "-pthread", ) + export.LDFLAGS = append(export.LDFLAGS, export.CCFLAGS...) export.LDFLAGS = append( export.LDFLAGS, "-lwasi-emulated-pthread", "-lpthread", - "-pthread", // global is immutable if -pthread is not specified ) } @@ -194,3 +206,114 @@ func Use(goos, goarch string, wasiThreads bool) (export Export, err error) { } return } + +// useTarget loads configuration from a target name (e.g., "rp2040", "wasi") +func useTarget(targetName string) (export Export, err error) { + resolver := targets.NewDefaultResolver() + + config, err := resolver.Resolve(targetName) + if err != nil { + return export, fmt.Errorf("failed to resolve target %s: %w", targetName, err) + } + + // Convert target config to Export - only export necessary fields + export.BuildTags = config.BuildTags + export.GOOS = config.GOOS + export.GOARCH = config.GOARCH + + // Convert LLVMTarget, CPU, Features to CCFLAGS/LDFLAGS + var ccflags []string + var ldflags []string + + target := config.LLVMTarget + if target == "" { + target = llvm.GetTargetTriple(config.GOOS, config.GOARCH) + } + + ccflags = append(ccflags, "-Wno-override-module", "--target="+config.LLVMTarget) + + // Inspired by tinygo + cpu := config.CPU + if cpu != "" { + if strings.HasPrefix(target, "i386") || strings.HasPrefix(target, "x86_64") { + ccflags = append(ccflags, "-march="+cpu) + } else if strings.HasPrefix(target, "avr") { + ccflags = append(ccflags, "-mmcu="+cpu) + } else { + ccflags = append(ccflags, "-mcpu="+cpu) + } + // Only add -mllvm flags for non-WebAssembly linkers + if config.Linker == "ld.lld" { + ldflags = append(ldflags, "-mllvm", "-mcpu="+cpu) + } + } + + // Handle Features + if config.Features != "" { + // Only add -mllvm flags for non-WebAssembly linkers + if config.Linker == "ld.lld" { + ldflags = append(ldflags, "-mllvm", "-mattr="+config.Features) + } + } + + // Handle Linker - keep it for external usage + export.Linker = config.Linker + + // Combine with config flags + export.CFLAGS = config.CFlags + export.CCFLAGS = ccflags + export.LDFLAGS = append(ldflags, filterCompatibleLDFlags(config.LDFlags)...) + export.EXTRAFLAGS = []string{} + + return export, nil +} + +// UseWithTarget extends the original Use function to support target-based configuration +// If targetName is provided, it takes precedence over goos/goarch +func UseWithTarget(goos, goarch string, wasiThreads bool, targetName string) (export Export, err error) { + if targetName != "" { + return useTarget(targetName) + } + return Use(goos, goarch, wasiThreads) +} + +// filterCompatibleLDFlags filters out linker flags that are incompatible with clang/lld +func filterCompatibleLDFlags(ldflags []string) []string { + if len(ldflags) == 0 { + return ldflags + } + + var filtered []string + + incompatiblePrefixes := []string{ + "--defsym=", // Use -Wl,--defsym= instead + "-T", // Linker script, needs special handling + } + + i := 0 + for i < len(ldflags) { + flag := ldflags[i] + + // Check incompatible prefixes + skip := false + for _, prefix := range incompatiblePrefixes { + if strings.HasPrefix(flag, prefix) { + skip = true + break + } + } + if skip { + // Skip -T and its argument if separate + if flag == "-T" && i+1 < len(ldflags) { + i += 2 // Skip both -T and the script path + } else { + i++ + } + continue + } + filtered = append(filtered, flag) + i++ + } + + return filtered +} diff --git a/internal/crosscompile/crosscompile_test.go b/internal/crosscompile/crosscompile_test.go index 9ce9bbe9..53161cd6 100644 --- a/internal/crosscompile/crosscompile_test.go +++ b/internal/crosscompile/crosscompile_test.go @@ -6,6 +6,7 @@ package crosscompile import ( "os" "runtime" + "slices" "testing" ) @@ -154,3 +155,181 @@ func TestUseCrossCompileSDK(t *testing.T) { }) } } + +func TestUseTarget(t *testing.T) { + // Test cases for target-based configuration + testCases := []struct { + name string + targetName string + expectError bool + expectLLVM string + expectCPU string + }{ + { + name: "WASI Target", + targetName: "wasi", + expectError: false, + expectLLVM: "", + expectCPU: "generic", + }, + { + name: "RP2040 Target", + targetName: "rp2040", + expectError: false, + expectLLVM: "thumbv6m-unknown-unknown-eabi", + expectCPU: "cortex-m0plus", + }, + { + name: "Cortex-M Target", + targetName: "cortex-m", + expectError: false, + expectLLVM: "", + expectCPU: "", + }, + { + name: "Arduino Target (with filtered flags)", + targetName: "arduino", + expectError: false, + expectLLVM: "avr", + expectCPU: "atmega328p", + }, + { + name: "Nonexistent Target", + targetName: "nonexistent-target", + expectError: true, + }, + } + + for _, tc := range testCases { + t.Run(tc.name, func(t *testing.T) { + export, err := useTarget(tc.targetName) + + if tc.expectError { + if err == nil { + t.Errorf("Expected error for target %s, but got none", tc.targetName) + } + return + } + + if err != nil { + t.Fatalf("Unexpected error for target %s: %v", tc.targetName, err) + } + + // Check if LLVM target is in CCFLAGS + if tc.expectLLVM != "" { + found := false + expectedFlag := "--target=" + tc.expectLLVM + for _, flag := range export.CCFLAGS { + if flag == expectedFlag { + found = true + break + } + } + if !found { + t.Errorf("Expected LLVM target %s in CCFLAGS, got %v", expectedFlag, export.CCFLAGS) + } + } + + // Check if CPU is in CCFLAGS + if tc.expectCPU != "" { + found := false + expectedFlags := []string{"-mmcu=" + tc.expectCPU, "-mcpu=" + tc.expectCPU} + for _, flag := range export.CCFLAGS { + for _, expectedFlag := range expectedFlags { + if flag == expectedFlag { + found = true + break + } + } + } + if !found { + t.Errorf("Expected CPU %s in CCFLAGS, got %v", tc.expectCPU, export.CCFLAGS) + } + } + + t.Logf("Target %s: BuildTags=%v, CFlags=%v, CCFlags=%v, LDFlags=%v", + tc.targetName, export.BuildTags, export.CFLAGS, export.CCFLAGS, export.LDFLAGS) + }) + } +} + +func TestUseWithTarget(t *testing.T) { + // Test target-based configuration takes precedence + export, err := UseWithTarget("linux", "amd64", false, "wasi") + if err != nil { + t.Fatalf("Unexpected error: %v", err) + } + + // Check if LLVM target is in CCFLAGS + found := slices.Contains(export.CCFLAGS, "-mcpu=generic") + if !found { + t.Errorf("Expected CPU generic in CCFLAGS, got %v", export.CCFLAGS) + } + + // Test fallback to goos/goarch when no target specified + export, err = UseWithTarget(runtime.GOOS, runtime.GOARCH, false, "") + if err != nil { + t.Fatalf("Unexpected error: %v", err) + } + + // Should use native configuration (only check for macOS since that's where tests run) + if runtime.GOOS == "darwin" && len(export.LDFLAGS) == 0 { + t.Error("Expected LDFLAGS to be set for native build") + } +} + +func TestFilterCompatibleLDFlags(t *testing.T) { + testCases := []struct { + name string + input []string + expected []string + }{ + { + name: "Empty flags", + input: []string{}, + expected: []string{}, + }, + { + name: "Compatible flags only", + input: []string{"-lm", "-lpthread"}, + expected: []string{"-lm", "-lpthread"}, + }, + { + name: "Incompatible flags filtered", + input: []string{"--gc-sections", "-lm", "--emit-relocs", "-lpthread"}, + expected: []string{"--gc-sections", "-lm", "--emit-relocs", "-lpthread"}, + }, + { + name: "Defsym flags filtered", + input: []string{"--defsym=_stack_size=512", "-lm", "--defsym=_bootloader_size=512"}, + expected: []string{"-lm"}, + }, + { + name: "Linker script flags filtered", + input: []string{"-T", "script.ld", "-lm"}, + expected: []string{"-lm"}, + }, + { + name: "Mixed compatible and incompatible", + input: []string{"-lm", "--gc-sections", "--defsym=test=1", "-lpthread", "--no-demangle"}, + expected: []string{"-lm", "--gc-sections", "-lpthread", "--no-demangle"}, + }, + } + + for _, tc := range testCases { + t.Run(tc.name, func(t *testing.T) { + result := filterCompatibleLDFlags(tc.input) + + if len(result) != len(tc.expected) { + t.Errorf("Expected %d flags, got %d: %v", len(tc.expected), len(result), result) + return + } + + for i, expected := range tc.expected { + if result[i] != expected { + t.Errorf("Expected flag[%d] = %s, got %s", i, expected, result[i]) + } + } + }) + } +} From f571dde5383fbf7a2ca72911814e767749b58f29 Mon Sep 17 00:00:00 2001 From: Li Jie Date: Sat, 26 Jul 2025 12:05:33 +1000 Subject: [PATCH 4/9] feat(build): integrate target configuration system into build pipeline MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Add Target field to build.Config struct - Update build system to use crosscompile.UseWithTarget() - Enable target-based cross-compilation in build pipeline - Maintain backward compatibility with existing GOOS/GOARCH workflow 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude --- internal/build/build.go | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/internal/build/build.go b/internal/build/build.go index 0a698dc3..46a2da6d 100644 --- a/internal/build/build.go +++ b/internal/build/build.go @@ -70,6 +70,7 @@ const ( type Config struct { Goos string Goarch string + Target string // target name (e.g., "rp2040", "wasi") - takes precedence over Goos/Goarch BinPath string AppExt string // ".exe" on Windows, empty on Unix OutFile string // only valid for ModeBuild when len(pkgs) == 1 @@ -251,7 +252,7 @@ func Do(args []string, conf *Config) ([]Package, error) { os.Setenv("PATH", env.BinDir()+":"+os.Getenv("PATH")) // TODO(xsw): check windows output := conf.OutFile != "" - export, err := crosscompile.Use(conf.Goos, conf.Goarch, IsWasiThreadsEnabled()) + export, err := crosscompile.UseWithTarget(conf.Goos, conf.Goarch, IsWasiThreadsEnabled(), conf.Target) check(err) ctx := &context{env: env, conf: cfg, progSSA: progSSA, prog: prog, dedup: dedup, patches: patches, built: make(map[string]none), initial: initial, mode: mode, From 0136344282669166de342a4deb77a5276f0e0dab Mon Sep 17 00:00:00 2001 From: Li Jie Date: Sat, 26 Jul 2025 12:05:55 +1000 Subject: [PATCH 5/9] feat(cmd): add -target flag support for build commands MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Add Target flag variable to support -target parameter - Update AddBuildFlags to include target platform option - Enable syntax: -target platform (e.g., rp2040, wasi) 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude --- cmd/internal/flags/flags.go | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cmd/internal/flags/flags.go b/cmd/internal/flags/flags.go index 56aa39d7..e21f27b6 100644 --- a/cmd/internal/flags/flags.go +++ b/cmd/internal/flags/flags.go @@ -13,11 +13,13 @@ func AddOutputFlags(fs *flag.FlagSet) { var Verbose bool var BuildEnv string var Tags string +var Target string func AddBuildFlags(fs *flag.FlagSet) { fs.BoolVar(&Verbose, "v", false, "Verbose mode") fs.StringVar(&Tags, "tags", "", "Build tags") fs.StringVar(&BuildEnv, "buildenv", "", "Build environment") + fs.StringVar(&Target, "target", "", "Target platform (e.g., rp2040, wasi)") } var Gen bool From daf0d7e56e990b83b6be77113c44d47137373e80 Mon Sep 17 00:00:00 2001 From: Li Jie Date: Tue, 29 Jul 2025 15:12:25 +0800 Subject: [PATCH 6/9] feat(cmd): enable -target parameter for build, run, and test commands MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Update build command: llgo build -target platform - Update run command: llgo run -target platform - Update test command: llgo test -target platform - Wire target flag to build configuration - Update usage documentation for new parameter Examples: - llgo build -target rp2040 ./firmware - llgo run -target wasi ./main.go - llgo test -target cortex-m ./tests 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude --- cmd/internal/build/build.go | 3 ++- cmd/internal/run/run.go | 7 ++--- cmd/internal/test/test.go | 3 ++- internal/build/build.go | 53 ++++++++++++++++++++++++++----------- 4 files changed, 45 insertions(+), 21 deletions(-) diff --git a/cmd/internal/build/build.go b/cmd/internal/build/build.go index d88f1666..39ab5db8 100644 --- a/cmd/internal/build/build.go +++ b/cmd/internal/build/build.go @@ -29,7 +29,7 @@ import ( // llgo build var Cmd = &base.Command{ - UsageLine: "llgo build [-o output] [build flags] [packages]", + UsageLine: "llgo build [-o output] [-target platform] [build flags] [packages]", Short: "Compile packages and dependencies", } @@ -50,6 +50,7 @@ func runCmd(cmd *base.Command, args []string) { conf.Tags = flags.Tags conf.Verbose = flags.Verbose conf.OutFile = flags.OutputFile + conf.Target = flags.Target args = cmd.Flag.Args() diff --git a/cmd/internal/run/run.go b/cmd/internal/run/run.go index 3df0c199..93b7bb41 100644 --- a/cmd/internal/run/run.go +++ b/cmd/internal/run/run.go @@ -34,7 +34,7 @@ var ( // llgo run var Cmd = &base.Command{ - UsageLine: "llgo run [build flags] package [arguments...]", + UsageLine: "llgo run [-target platform] [build flags] package [arguments...]", Short: "Compile and run Go program", } @@ -54,11 +54,11 @@ func init() { } func runCmd(cmd *base.Command, args []string) { - runCmdEx(cmd, args, build.ModeRun) + runCmdEx(cmd, args, build.ModeRun) // support target } func runCmpTest(cmd *base.Command, args []string) { - runCmdEx(cmd, args, build.ModeCmpTest) + runCmdEx(cmd, args, build.ModeCmpTest) // no target support } func runCmdEx(cmd *base.Command, args []string, mode build.Mode) { @@ -71,6 +71,7 @@ func runCmdEx(cmd *base.Command, args []string, mode build.Mode) { conf.Tags = flags.Tags conf.Verbose = flags.Verbose conf.GenExpect = flags.Gen + conf.Target = flags.Target args = cmd.Flag.Args() args, runArgs, err := parseRunArgs(args) diff --git a/cmd/internal/test/test.go b/cmd/internal/test/test.go index 64e49927..34516381 100644 --- a/cmd/internal/test/test.go +++ b/cmd/internal/test/test.go @@ -11,7 +11,7 @@ import ( // llgo test var Cmd = &base.Command{ - UsageLine: "llgo test [build flags] package [arguments...]", + UsageLine: "llgo test [-target platform] [build flags] package [arguments...]", Short: "Compile and run Go test", } @@ -29,6 +29,7 @@ func runCmd(cmd *base.Command, args []string) { conf := build.NewDefaultConf(build.ModeTest) conf.Tags = flags.Tags conf.Verbose = flags.Verbose + conf.Target = flags.Target args = cmd.Flag.Args() _, err := build.Do(args, conf) diff --git a/internal/build/build.go b/internal/build/build.go index 46a2da6d..abfc4a3d 100644 --- a/internal/build/build.go +++ b/internal/build/build.go @@ -70,7 +70,7 @@ const ( type Config struct { Goos string Goarch string - Target string // target name (e.g., "rp2040", "wasi") - takes precedence over Goos/Goarch + Target string // target name (e.g., "rp2040", "wasi") - takes precedence over Goos/Goarch BinPath string AppExt string // ".exe" on Windows, empty on Unix OutFile string // only valid for ModeBuild when len(pkgs) == 1 @@ -150,6 +150,20 @@ func Do(args []string, conf *Config) ([]Package, error) { if conf.Goarch == "" { conf.Goarch = runtime.GOARCH } + // Handle crosscompile configuration first to set correct GOOS/GOARCH + export, err := crosscompile.UseWithTarget(conf.Goos, conf.Goarch, IsWasiThreadsEnabled(), conf.Target) + if err != nil { + return nil, fmt.Errorf("failed to setup crosscompile: %w", err) + } + + // Update GOOS/GOARCH from export if target was used + if conf.Target != "" && export.GOOS != "" { + conf.Goos = export.GOOS + } + if conf.Target != "" && export.GOARCH != "" { + conf.Goarch = export.GOARCH + } + verbose := conf.Verbose patterns := args tags := "llgo" @@ -161,6 +175,7 @@ func Do(args []string, conf *Config) ([]Package, error) { BuildFlags: []string{"-tags=" + tags}, Fset: token.NewFileSet(), Tests: conf.Mode == ModeTest, + Env: append(slices.Clone(os.Environ()), "GOOS="+conf.Goos, "GOARCH="+conf.Goarch), } if conf.Mode == ModeTest { cfg.Mode |= packages.NeedForTest @@ -252,8 +267,6 @@ func Do(args []string, conf *Config) ([]Package, error) { os.Setenv("PATH", env.BinDir()+":"+os.Getenv("PATH")) // TODO(xsw): check windows output := conf.OutFile != "" - export, err := crosscompile.UseWithTarget(conf.Goos, conf.Goarch, IsWasiThreadsEnabled(), conf.Target) - check(err) ctx := &context{env: env, conf: cfg, progSSA: progSSA, prog: prog, dedup: dedup, patches: patches, built: make(map[string]none), initial: initial, mode: mode, output: output, @@ -371,6 +384,15 @@ func (c *context) compiler() *clang.Cmd { return cmd } +func (c *context) linker() *clang.Cmd { + cmd := c.env.Clang() + if c.crossCompile.Linker != "" { + cmd = clang.New(c.crossCompile.Linker) + } + cmd.Verbose = c.buildConf.Verbose + return cmd +} + func buildAllPkgs(ctx *context, initial []*packages.Package, verbose bool) (pkgs []*aPackage, err error) { pkgs, errPkgs := allPkgs(ctx, initial, verbose) for _, errPkg := range errPkgs { @@ -541,14 +563,14 @@ func linkMainPkg(ctx *context, pkg *packages.Package, pkgs []*aPackage, global l pkgsMap[v.Package] = v allPkgs = append(allPkgs, v.Package) } - var llFiles []string + var objFiles []string var linkArgs []string packages.Visit(allPkgs, nil, func(p *packages.Package) { aPkg := pkgsMap[p] if p.ExportFile != "" && aPkg != nil { // skip packages that only contain declarations linkArgs = append(linkArgs, aPkg.LinkArgs...) - llFiles = append(llFiles, aPkg.LLFiles...) - llFiles = append(llFiles, aPkg.ExportFile) + objFiles = append(objFiles, aPkg.LLFiles...) + objFiles = append(objFiles, aPkg.ExportFile) need1, need2 := isNeedRuntimeOrPyInit(ctx, p) if !needRuntime { needRuntime = need1 @@ -558,18 +580,19 @@ func linkMainPkg(ctx *context, pkg *packages.Package, pkgs []*aPackage, global l } } }) - entryLLFile, err := genMainModuleFile(ctx, llssa.PkgRuntime, pkg, needRuntime, needPyInit) + entryObjFile, err := genMainModuleFile(ctx, llssa.PkgRuntime, pkg, needRuntime, needPyInit) check(err) // defer os.Remove(entryLLFile) - llFiles = append(llFiles, entryLLFile) + objFiles = append(objFiles, entryObjFile) if global != nil { export, err := exportObject(ctx, pkg.PkgPath+".global", pkg.ExportFile+"-global", []byte(global.String())) check(err) - llFiles = append(llFiles, export) + objFiles = append(objFiles, export) } - err = compileAndLinkLLFiles(ctx, app, llFiles, linkArgs, verbose) + err = linkObjFiles(ctx, app, objFiles, linkArgs, verbose) + err = linkObjFiles(ctx, app, objFiles, linkArgs, verbose) check(err) switch mode { @@ -626,7 +649,7 @@ func linkMainPkg(ctx *context, pkg *packages.Package, pkgs []*aPackage, global l } } -func compileAndLinkLLFiles(ctx *context, app string, llFiles, linkArgs []string, verbose bool) error { +func linkObjFiles(ctx *context, app string, objFiles, linkArgs []string, verbose bool) error { buildArgs := []string{"-o", app} buildArgs = append(buildArgs, linkArgs...) @@ -638,12 +661,9 @@ func compileAndLinkLLFiles(ctx *context, app string, llFiles, linkArgs []string, buildArgs = append(buildArgs, ctx.crossCompile.CCFLAGS...) buildArgs = append(buildArgs, ctx.crossCompile.LDFLAGS...) buildArgs = append(buildArgs, ctx.crossCompile.EXTRAFLAGS...) - buildArgs = append(buildArgs, llFiles...) - if verbose { - buildArgs = append(buildArgs, "-v") - } + buildArgs = append(buildArgs, objFiles...) - cmd := ctx.compiler() + cmd := ctx.linker() cmd.Verbose = verbose return cmd.Link(buildArgs...) } @@ -820,6 +840,7 @@ func exportObject(ctx *context, pkgPath string, exportFile string, data []byte) exportFile += ".o" args := []string{"-o", exportFile, "-c", f.Name(), "-Wno-override-module"} args = append(args, ctx.crossCompile.CCFLAGS...) + args = append(args, ctx.crossCompile.CFLAGS...) if ctx.buildConf.Verbose { fmt.Fprintln(os.Stderr, "clang", args) } From 6f829d0d43c6f69331b6d38dec5529121e7db4d4 Mon Sep 17 00:00:00 2001 From: Li Jie Date: Wed, 30 Jul 2025 11:05:06 +0800 Subject: [PATCH 7/9] add empty demo for build -target tests --- _demo/empty/empty.go | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 _demo/empty/empty.go diff --git a/_demo/empty/empty.go b/_demo/empty/empty.go new file mode 100644 index 00000000..da29a2ca --- /dev/null +++ b/_demo/empty/empty.go @@ -0,0 +1,4 @@ +package main + +func main() { +} From 49a5d3a35058b33043bfbdad636880de9c459ca9 Mon Sep 17 00:00:00 2001 From: Li Jie Date: Wed, 30 Jul 2025 11:05:55 +0800 Subject: [PATCH 8/9] dummy _start function for libc-free cases --- internal/build/build.go | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/internal/build/build.go b/internal/build/build.go index abfc4a3d..9cea6b4b 100644 --- a/internal/build/build.go +++ b/internal/build/build.go @@ -658,7 +658,6 @@ func linkObjFiles(ctx *context, app string, objFiles, linkArgs []string, verbose buildArgs = append(buildArgs, "-gdwarf-4") } - buildArgs = append(buildArgs, ctx.crossCompile.CCFLAGS...) buildArgs = append(buildArgs, ctx.crossCompile.LDFLAGS...) buildArgs = append(buildArgs, ctx.crossCompile.EXTRAFLAGS...) buildArgs = append(buildArgs, objFiles...) @@ -712,9 +711,23 @@ call i32 @setvbuf(ptr %stdout_ptr, ptr null, i32 2, %size_t 0) call i32 @setvbuf(ptr %stderr_ptr, ptr null, i32 2, %size_t 0) ` } + // TODO(lijie): workaround for libc-free + // Remove main/_start when -buildmode and libc are ready + startDefine := ` +define weak void @_start() { + ; argc = 0 + %argc_val = icmp eq i32 0, 0 + %argc = zext i1 %argc_val to i32 + ; argv = null + %argv = inttoptr i64 0 to i8** + call i32 @main(i32 %argc, i8** %argv) + ret void +} +` mainDefine := "define i32 @main(i32 noundef %0, ptr nocapture noundef readnone %1) local_unnamed_addr" if isWasmTarget(ctx.buildConf.Goos) { mainDefine = "define hidden noundef i32 @__main_argc_argv(i32 noundef %0, ptr nocapture noundef readnone %1) local_unnamed_addr" + startDefine = "" } mainCode := fmt.Sprintf(`; ModuleID = 'main' source_filename = "main" @@ -735,6 +748,8 @@ define weak void @"syscall.init"() { ret void } +%s + %s { _llgo_0: store i32 %%0, ptr @__llgo_argc, align 4 @@ -749,7 +764,7 @@ _llgo_0: } `, declSizeT, stdioDecl, pyInitDecl, rtInitDecl, mainPkgPath, mainPkgPath, - mainDefine, stdioNobuf, + startDefine, mainDefine, stdioNobuf, pyInit, rtInit, mainPkgPath, mainPkgPath) return exportObject(ctx, pkg.PkgPath+".main", pkg.ExportFile+"-main", []byte(mainCode)) From b773de08158e15abc843b99f3cef38aed57fbfbd Mon Sep 17 00:00:00 2001 From: Li Jie Date: Wed, 30 Jul 2025 11:53:01 +0800 Subject: [PATCH 9/9] ci: add build -target tests --- .github/workflows/targets.yml | 180 ++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) create mode 100644 .github/workflows/targets.yml diff --git a/.github/workflows/targets.yml b/.github/workflows/targets.yml new file mode 100644 index 00000000..5305398f --- /dev/null +++ b/.github/workflows/targets.yml @@ -0,0 +1,180 @@ + +name: Targets + +on: + push: + branches: ["**"] + pull_request: + branches: ["**"] + +jobs: + llgo: + continue-on-error: true + strategy: + matrix: + os: + - macos-latest + - ubuntu-24.04 + llvm: [19] + runs-on: ${{matrix.os}} + steps: + - uses: actions/checkout@v4 + - name: Install dependencies + uses: ./.github/actions/setup-deps + with: + llvm-version: ${{matrix.llvm}} + + - name: Set up Go for build + uses: ./.github/actions/setup-go + with: + go-version: "1.24.2" + + - name: Install + run: | + go install ./... + echo "LLGO_ROOT=$GITHUB_WORKSPACE" >> $GITHUB_ENV + + - name: Build targets + run: | + cd _demo/empty + for target in \ + ae-rp2040 \ + arduino-leonardo \ + arduino-mega1280 \ + arduino-mega2560 \ + arduino-mkr1000 \ + arduino-mkrwifi1010 \ + arduino-nano-new \ + arduino-nano \ + arduino-nano33 \ + arduino-zero \ + arduino \ + atmega1280 \ + atmega1284p \ + atmega2560 \ + atmega328p \ + atmega328pb \ + atmega32u4 \ + atsamd21e18a \ + atsamd21g18a \ + atsamd51g19a \ + atsamd51j19a \ + atsamd51j20a \ + atsamd51p19a \ + atsamd51p20a \ + atsame51j19a \ + atsame54-xpro \ + atsame54p20a \ + attiny1616 \ + attiny85 \ + badger2040-w \ + badger2040 \ + bluepill-clone \ + bluepill \ + btt-skr-pico \ + challenger-rp2040 \ + circuitplay-express \ + cortex-m-qemu \ + cortex-m0 \ + cortex-m0plus \ + cortex-m3 \ + cortex-m33 \ + cortex-m4 \ + cortex-m7 \ + digispark \ + elecrow-rp2040 \ + elecrow-rp2350 \ + esp-c3-32s-kit \ + esp32-c3-devkit-rust-1 \ + esp32c3-12f \ + esp32c3-supermini \ + esp32c3 \ + fe310 \ + feather-m0-express \ + feather-m0 \ + feather-m4-can \ + feather-m4 \ + feather-rp2040 \ + feather-stm32f405 \ + gameboy-advance \ + gemma-m0 \ + gnse \ + gobadge \ + gopher-badge \ + gopherbot \ + grandcentral-m4 \ + hifive1b \ + itsybitsy-m0 \ + itsybitsy-m4 \ + k210 \ + kb2040 \ + lgt92 \ + lorae5 \ + m5stamp-c3 \ + macropad-rp2040 \ + maixbit \ + makerfabs-esp32c3spi35 \ + matrixportal-m4 \ + metro-m4-airlift \ + mksnanov3 \ + nano-rp2040 \ + nintendoswitch \ + nucleo-f103rb \ + nucleo-f722ze \ + nucleo-l031k6 \ + nucleo-l432kc \ + nucleo-l476rg \ + nucleo-l552ze \ + nucleo-wl55jc \ + p1am-100 \ + pga2350 \ + pico-plus2 \ + pico-w \ + pico \ + pico2-w \ + pico2 \ + pybadge \ + pygamer \ + pyportal \ + qtpy-esp32c3 \ + qtpy-rp2040 \ + qtpy \ + riscv-qemu \ + riscv32 \ + riscv64 \ + rp2040 \ + rp2350 \ + rp2350b \ + simavr \ + stm32f469disco \ + stm32f4disco-1 \ + stm32f4disco \ + stm32l0x2 \ + stm32wl5x_cm4 \ + stm32wle5 \ + swan \ + teensy36 \ + teensy40 \ + teensy41 \ + thingplus-rp2040 \ + thumby \ + tiny2350 \ + tkey \ + trinket-m0 \ + trinkey-qt2040 \ + tufty2040 \ + wasip2 \ + wasm-unknown \ + waveshare-rp2040-tiny \ + waveshare-rp2040-zero \ + wioterminal \ + xiao-esp32c3 \ + xiao-rp2040 \ + xiao; do + ../../llgo.sh build -v -target $target -o hello.out . >/dev/null 2>&1 + if [ $? -eq 0 ]; then + echo ✅ $target `file hello.out` + else + echo ❌ $target + fi + done