Files
llgo/targets/device/rp/rp2350.s
2025-08-20 10:27:01 +08:00

184 lines
6.2 KiB
ArmAsm

// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from rp2350.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/RaspberryPi
/*
//
// Dual Cortex-M33 or Hazard3 processors at 150MHz
// 520kB on-chip SRAM, in 10 independent banks
// Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD
// 8kB of one-time-programmable storage (OTP)
// Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus
// Additional 16MB flash/PSRAM accessible via optional second chip-select
// On-chip switched-mode power supply to generate core voltage
// Low-quiescent-current LDO mode can be enabled for sleep states
// 2x on-chip PLLs for internal or external clock generation
// GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered)
// Security features:
// Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP
// Protected OTP storage for optional boot decryption key
// Global bus filtering based on Arm or RISC-V security/privilege levels
// Peripherals, GPIOs and DMA channels individually assignable to security domains
// Hardware mitigations for fault injection attacks
// Hardware SHA-256 accelerator
// Peripherals:
// 2x UARTs
// 2x SPI controllers
// 2x I2C controllers
// 24x PWM channels
// USB 1.1 controller and PHY, with host and device support
// 12x PIO state machines
// 1x HSTX peripheral
//
*/
// Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause
.syntax unified
// This is the default handler for interrupts, if triggered but not defined.
.section .text.Default_Handler
.global Default_Handler
.type Default_Handler, %function
Default_Handler:
wfe
b Default_Handler
.size Default_Handler, .-Default_Handler
// Avoid the need for repeated .weak and .set instructions.
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
// Must set the "a" flag on the section:
// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
.section .isr_vector, "a", %progbits
.global __isr_vector
__isr_vector:
// Interrupt vector as defined by Cortex-M, starting with the stack top.
// On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
// _stack_top and Reset_Handler.
.long _stack_top
.long Reset_Handler
.long NMI_Handler
.long HardFault_Handler
.long MemoryManagement_Handler
.long BusFault_Handler
.long UsageFault_Handler
.long 0
.long 0
.long 0
.long 0
.long SVC_Handler
.long DebugMon_Handler
.long 0
.long PendSV_Handler
.long SysTick_Handler
// Extra interrupts for peripherals defined by the hardware vendor.
.long TIMER0_IRQ_0_IRQHandler
.long TIMER0_IRQ_1_IRQHandler
.long TIMER0_IRQ_2_IRQHandler
.long TIMER0_IRQ_3_IRQHandler
.long TIMER1_IRQ_0_IRQHandler
.long TIMER1_IRQ_1_IRQHandler
.long TIMER1_IRQ_2_IRQHandler
.long TIMER1_IRQ_3_IRQHandler
.long PWM_IRQ_WRAP_0_IRQHandler
.long PWM_IRQ_WRAP_1_IRQHandler
.long DMA_IRQ_0_IRQHandler
.long DMA_IRQ_1_IRQHandler
.long DMA_IRQ_2_IRQHandler
.long DMA_IRQ_3_IRQHandler
.long USBCTRL_IRQ_IRQHandler
.long PIO0_IRQ_0_IRQHandler
.long PIO0_IRQ_1_IRQHandler
.long PIO1_IRQ_0_IRQHandler
.long PIO1_IRQ_1_IRQHandler
.long PIO2_IRQ_0_IRQHandler
.long PIO2_IRQ_1_IRQHandler
.long IO_IRQ_BANK0_IRQHandler
.long IO_IRQ_BANK0_NS_IRQHandler
.long IO_IRQ_QSPI_IRQHandler
.long IO_IRQ_QSPI_NS_IRQHandler
.long SIO_IRQ_FIFO_IRQHandler
.long SIO_IRQ_BELL_IRQHandler
.long SIO_IRQ_FIFO_NS_IRQHandler
.long SIO_IRQ_BELL_NS_IRQHandler
.long SIO_IRQ_MTIMECMP_IRQHandler
.long CLOCKS_IRQ_IRQHandler
.long SPI0_IRQ_IRQHandler
.long SPI1_IRQ_IRQHandler
.long UART0_IRQ_IRQHandler
.long UART1_IRQ_IRQHandler
.long ADC_IRQ_FIFO_IRQHandler
.long I2C0_IRQ_IRQHandler
.long I2C1_IRQ_IRQHandler
.long OTP_IRQ_IRQHandler
.long TRNG_IRQ_IRQHandler
.long 0
.long 0
.long PLL_SYS_IRQ_IRQHandler
.long PLL_USB_IRQ_IRQHandler
.long POWMAN_IRQ_POW_IRQHandler
.long POWMAN_IRQ_TIMER_IRQHandler
// Define default implementations for interrupts, redirecting to
// Default_Handler when not implemented.
IRQ NMI_Handler
IRQ HardFault_Handler
IRQ MemoryManagement_Handler
IRQ BusFault_Handler
IRQ UsageFault_Handler
IRQ SVC_Handler
IRQ DebugMon_Handler
IRQ PendSV_Handler
IRQ SysTick_Handler
IRQ TIMER0_IRQ_0_IRQHandler
IRQ TIMER0_IRQ_1_IRQHandler
IRQ TIMER0_IRQ_2_IRQHandler
IRQ TIMER0_IRQ_3_IRQHandler
IRQ TIMER1_IRQ_0_IRQHandler
IRQ TIMER1_IRQ_1_IRQHandler
IRQ TIMER1_IRQ_2_IRQHandler
IRQ TIMER1_IRQ_3_IRQHandler
IRQ PWM_IRQ_WRAP_0_IRQHandler
IRQ PWM_IRQ_WRAP_1_IRQHandler
IRQ DMA_IRQ_0_IRQHandler
IRQ DMA_IRQ_1_IRQHandler
IRQ DMA_IRQ_2_IRQHandler
IRQ DMA_IRQ_3_IRQHandler
IRQ USBCTRL_IRQ_IRQHandler
IRQ PIO0_IRQ_0_IRQHandler
IRQ PIO0_IRQ_1_IRQHandler
IRQ PIO1_IRQ_0_IRQHandler
IRQ PIO1_IRQ_1_IRQHandler
IRQ PIO2_IRQ_0_IRQHandler
IRQ PIO2_IRQ_1_IRQHandler
IRQ IO_IRQ_BANK0_IRQHandler
IRQ IO_IRQ_BANK0_NS_IRQHandler
IRQ IO_IRQ_QSPI_IRQHandler
IRQ IO_IRQ_QSPI_NS_IRQHandler
IRQ SIO_IRQ_FIFO_IRQHandler
IRQ SIO_IRQ_BELL_IRQHandler
IRQ SIO_IRQ_FIFO_NS_IRQHandler
IRQ SIO_IRQ_BELL_NS_IRQHandler
IRQ SIO_IRQ_MTIMECMP_IRQHandler
IRQ CLOCKS_IRQ_IRQHandler
IRQ SPI0_IRQ_IRQHandler
IRQ SPI1_IRQ_IRQHandler
IRQ UART0_IRQ_IRQHandler
IRQ UART1_IRQ_IRQHandler
IRQ ADC_IRQ_FIFO_IRQHandler
IRQ I2C0_IRQ_IRQHandler
IRQ I2C1_IRQ_IRQHandler
IRQ OTP_IRQ_IRQHandler
IRQ TRNG_IRQ_IRQHandler
IRQ PLL_SYS_IRQ_IRQHandler
IRQ PLL_USB_IRQ_IRQHandler
IRQ POWMAN_IRQ_POW_IRQHandler
IRQ POWMAN_IRQ_TIMER_IRQHandler
.size __isr_vector, .-__isr_vector